DEE3233/Rds2005/fkee

MOSFET 1. Introduction Metal oxide semiconductor field effect transistor One of the most important devices used in the design and construction of IC for digital computers. Thermal stability, more popular in computer circuit design Two types of MOSFET : Depletion type Enhancement type

Depletion and enhancement define their basic mode of operation MOSFET symbol:
p-channel D SS S n-channel D G S
S p-channel D SS n-channel D G S

Fig 1(a) Depletion type MOSFET symbols symbols 2. Depletion-type MOSFET 2.1 Basic Construction

Fig 1(b) Enhancement type MOSFET

P-type material is formed from a silicon base and referred to as the substrate. Substrate is internally connected to the source (S) terminal. The source S and drain D terminals are connected through metallic contacts to ndoped regions linked by an n-channel. SiO2 is a particular type of insulator, referred to as a dielectric.

21

DEE3233/Rds2005/fkee

Fig 2. n-channel depletion type MOSFET The reason for the label MOSFET is now fairly obvious: metal for the drain, source and gate connections to the proper surfaceThe oxide for the SiO2 insulating layer. The semiconductor for the basic structure on which the n and p-type regions are diffused. 2.2 Basic Operation and Characteristics -- N-channel depletion type VGS is set to 0V by the direct connection from one terminal to the other. VDS is applied across the drain-to-source terminals. The result is an attraction for the positive potential at the drain by the free electron of the n-channel and a current similar to that established through the channel of the JFET.

22

DEE3233/Rds2005/fkee

Fig 2. n-channel depletion type MOSFET with VGS=0 and an applied voltage VDD In Fig 3, VGS has been set at a negative voltage (-1V) Negative potential at gate will tend to pressure electron towards the p-type substrate and attract holes from the p-type substrate. Depending on negative bias established by VGS, a level recombination between electron and hoes will occur.--- it will reduce the number of free electron in the nchannel available for conduction. The more negative bias, the higher the rate of recombination ID decrease, negative bias for VGS increase

23

DEE3233/Rds2005/fkee

Fig 3. Reduction in free carriers in channel due to a negative potential at the gate terminal. Positive value of VGS , the positive gate will draw additional electrons from p-type substrate due to reverse leakage current and establish new carries through the collisions resulting between accelerating particles VGS increase in positive direction, ID will increase at a rapid rate The application of a positive VGS has enhanced the level of free carriers in the channel compared to that encountered with VGS =0V.

24

DEE3233/Rds2005/fkee

Figure 4. Drain and transfer characteristics for an n-channel depletion type MOSFET. The region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region, with the region between cut off and the saturation level of IDSS referred to as depletion region. 2.3 Basic Operation and Characteristics -- P-channel depletion type. Voltage polarities and the current directions are reversed VDS having negative values from cut off at VGS = VP in the positive VGS region to IDSS and then continue to increase for increasingly negative values of VGS.

(a)

(b)

(c)

25

DEE3233/Rds2005/fkee

Fig 5. p-channel depletion type MOSFET with IDSS= 6 mA and Vp=+6V 3. Enhancement Type MOSFET The transfer curve is not defined by Shockleys equations ID is now cut off until the VGS reaches a specific magnitude Current control in an n-channel device is now effected by a +VGS rather than the range of negative voltage encountered for n-channel JFETs and n-channel depletion type MOSFET.

Fig 6. n-channel enhancement type MOSFET P-type is formed from silicon base, referred to as substrate The absence of the channel between the 2 n-doped regions. This is primary difference between the construction of depletion type and enhancement type. The construction type of an enhancement type MOSFET is quite similar to that of the depletion type MOSFET. 3.1 Basic Operation and Characteristic N-channel enhancement type VGS=0, VDS some value, the absence of an n-channel will result in a current of effectively 0A

26

DEE3233/Rds2005/fkee

VDS some positive voltage, VGS=0V, and terminal SS is directly connected to the source, there are in fact 2 reversed-biased p-n junction between the n-doped regions and p substrate to oppose any significant flow between drain and source.

VDS and VGS have been set at some positive voltage greater than 0V, establishing the D and G at a positive potential with respect to the source The positive potential at the gate will pressure the holes in the p substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p-substrate The result is a depletion region near the SiO2 insulating layer void of holes

Fig 7. Channel formation in the n-channel enhancement-type MOSFET. The electrons will in the p substrate will be attracted to the +G and accumulate in the region near the surface of the SiO2 layer The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal VGS increase, the concentration of electrons near the SiO2 surface increase until eventually the induced n-type region can support a measurable flow between D and S

27

DEE3233/Rds2005/fkee

The level of VGS that results in the significant increase in drain current is called the threshold voltage, VT. VGS increase beyond the VT level the density of the carriers in the induced channel will increase and ID also increase If VGS constant and increase the level of VDS, ID will eventually reach a saturation level as occurred for the JFET Applying Kirchoffs voltage law to the terminal voltage of the MOSFET VDG = VDS- VGS

Fig 8 Change in channel and depletion region with increasing level of VDS for a fixed value of VGS. If VGS fixed at some value, 8V, VDS increased from 2 5V, the VDG will drop from -6V to -3V and the gate will become less and less positive with respect to the drain Reduce the attractive force for free carriers (electrons) Saturation level for VDS is elated to the level of applied VGS by VDsat = VGS-VT

28

DEE3233/Rds2005/fkee

For fixed value of VT, the higher level VGS, the more the saturation level for VDS for values of VGS less than the threshold level, the drain current of an enhancementtype MOSFET is 0mA for levels of VGS> VT, ID is related to the applied VGS by
I D = k (VGS VT )
2

k Constant that is a function of the construction of the device

k=

(V

I D (ON )

GS ( ON )

VT )

ID(ON) and VGS(ON) are the values for each at particular point on the characteristics of the device.

Fig 10. Sketching transfer characteristics for an n-channel enhancement type MOSFET from the drain characteristics.

29

DEE3233/Rds2005/fkee

3.2 Basic Operation and Characteristic p-channel enhancement type The construction of a p-channel enhancement type MOSFET is exactly the reverse of that appearing in Fig 6. There is now an n-type substrate and p-doped regions under the drain and source connections. All the voltage polarities and the current directions are reversed. The transfer characteristics will be the mirror image (about the ID axis) of the transfer curve for the n-channel enhancement type, with ID increasing with increasingly negative values of VGS beyond VT.

(a)

(b)

(c)

Fig 11. p-channel enhancement type MOSFET with VT=2V, and k = 0.5 x 10-3 A/V2

30

DEE3233/Rds2005/fkee

4. Depletion Type MOSFETs Biasing. The similarities in appearance between the transfer curves of JFETs and depletiontype MOSFETs permit a similar analysis of each in the dc domain. The primary difference between the two is the fact that depletion-type MOSFETs permit operating points with positive values of VG and levels of I D that exceeds S
I DSS

The analysis is the same if the JFET is replaced by a depletion-type MOSFET The only undefined part of the analysis is how to plot Shockleys equation for positive values of VG S

5. Enhancement-Type MOSFETs Biasing. The transfer characteristics of the enhancement-type MOSFETs are quite different from those encountered for the JFET and depletion-type MOSFETs Graphical solution quite different from the proceeding sections. For the n-channel enhancement-type MOSFET, the drain current is zero for levels of gate-to-source voltage less than the threshold level VG S
ID = 0A if VGS < VGS (Th )
(T ) h (T ) h

as shown in Fig 12.

For levels of VG greater than VGS S

I D = k (VGS VGS (Th ) ) 2

, the drain current is defined by :

The level of drain current I D (ON

, threshold voltage and VGS (ON

are provided in

specification sheets. Two point can be defined immediately as shown in Fig 12. To complete the curve, the constant k must be determined from the specification sheet data by substituting into equation,
I D = k (VGS VGS (Th ) ) 2

I D ( ON ) = k (VGS ( ON ) VGS (Th ) ) 2

k=

(V

I D ( ON )

GS ( ON )

VGS (Th ) )

After k is defined, other levels of I D can be determined for chosen values VG . S

31

DEE3233/Rds2005/fkee

Typically , a point between VGS

VG S
(O ) N

(T ) h

and VGS (ON

and one just greater than

will provide a sufficient number of points to plot equation

I D = k (VGS VGS (Th ) ) 2

Fig 12. Transfer characteristics of an n-channel enhancement-type MOSFET.

5.1 Feedback Biasing Arrangement. A popular arrangement for enhancement-type MOSFETs is provided in Fig 13. Resistor RG brings a suitable large voltage to the gate to drive the MOSFET on. For the dc analysis:
I G = 0mA and V RG = 0V

32

DEE3233/Rds2005/fkee

V DD
VDD
S hort circuitsince , IG=0m A and V =0V RG

ID RD

RD
Vo

D
+

C2
RG
Vi

D
G
+

G
+

VDS
-

VGS

C1

VGS

VDD + I D RD + VDS = 0

Fig 13. Feedback biasing arrangement

Fig14. DC equivalent of the network

A direct connect exists between drain and gate, resulting in V D =VG and
V DS =VGS

For the output circuit (loop) : V DD + I D R D +V DS = 0 Which becomes the following after substituting V DS =VGS
VGS = V DD I D R D --- a straight line

the result is an equation that relates the same two variables as equation
I D = k (VGS VGS (Th ) ) 2 , permitting the plot of each on the same set of axes.

Determine the two points that will define the plot on the graph by substituting
I D = 0mA into
VGS = V DD I D R D , gives

VGS = V DD | I D =0

Substituting VGS = 0V into VGS = VDD I D R D , gives

ID = VDD RD
VGS =0

33

DEE3233/Rds2005/fkee

The plots that have been defined appear in Fig 15 with the resulting operating point.

Fig 15. Determining the Q-point for the network of Fig 13 5.2 Voltage- Divider- Biasing Arrangement. A second popular biasing arrangement for the enhancement-type MOSFET appears in Fig 16.
V DD

R1

RD
D

IG = 0A G VG + VGS + V RS = 0
+

VGS
1

S
RS

V DD + I D R D + V DS + VRS = 0

R2

Fig 16. Voltage divider biasing arrangement for an n-channel enhancement MOSFET.
I G = 0 A results in the following equations for VG as derived from an application of

the voltage-divider rule:

34

DEE3233/Rds2005/fkee

VG =

R2V DD R1 + R2

Applying Kirchoffs voltage law around the indicated loop 1, will result in
VG +VGS +VRS = 0 VGS =VG V RS

or

VGS = VG I D RS

For the output section (loop 2):

VDD + I D RD +VDS +VRS = 0 V DS = V DD V RS V RD V DS = V DD I D ( RS + R D )

The characteristics are plot of I D versus VG S 2 curves can be plotted on the same graph and a solution determined at their intersection.
S Once I DQ and VG Q

are known, all remaining quantities of the network such as

VD , S

V D , V S can be determined.

6. P Channel FETs For p-channel FETs, a mirror image of the transfer curves is employed, and the defined current directions are reversed as shown in Fig 19 for the various types of FETs. Note for each configuration of figure 19 that each supply voltage is now a negative voltage drawing current in the indicated direction. Due to similarities between the analysis of n-channel and p-channel devices, one can actually assume an n-channel device and reverse the supply voltage and perform the entire analysis. When the results are obtained, the magnitude of each quantity will be correct, although the current direction and voltage polarities will have to be reversed.

35

DEE3233/Rds2005/fkee

Fig 17. P-channel configuration.

36