Program 1 Aim: To design a full adder using half adders.

System decription: A full adder adds binary numbers and accounts for values carried in as well as out. A onebit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in (in theory from a past addition). The circuit produces a two-bit output sum typically represented by the signals Cout and S, where Inputs Outputs A B Cin Cout S 0 0 0 0 0 1 0 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 1 1 1 1 1 . The one-bit full adder's truth table is:

Example full adder logic diagram; the AND and OR gates can be replaced with NAND gates for the same results A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with and . Executions: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity ha is port(a,b:in std_logic; s,c:out std_logic); end ha; architecture Behavioral of ha is begin s<=a xor b; c<=a and b; end Behavioral; library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all entity fa is port(a,b,cin:in std_logic; s,cout:out std_logic); end fa; architecture Behavioral of fa is component ha is port(a,b:in std_logic; s,c:out std_logic); end component; signal x,y,z:std_logic; begin b1:ha port map(a,b,x,y); b2:ha port map(x,cin,s,z); cout<=y or z; end Behavioral; Results:

Program 2

Aim: To design an 8x1 multiplixer using a 2x1 mux. System description : In digital circuit design, the selector wires are of digital value. In the case of a 2-to-1 multiplexer, a logic value of 0 would connect to the output while a logic value of 1 would connect to the output. In larger multiplexers, the number of selector pins is equal to where is the number of inputs. Executions: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity mux is port(i:in std_logic_vector(3 downto 0); s:in std_logic_vector(1 downto 0); e:in std_logic; y:out std_logic); end mux; architecture Behavioral of mux is begin process(i,s,e) is begin if e='0' then case s is when "00"=> y<=i(0); when "01"=> y<=i(1); when "10"=> y<=i(2); when others=> y<=i(3); end case; else y<='0'; end if; end process; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity mux81 is port(i:in std_logic_vector(7 downto 0); s:in std_logic_vector(2 downto 0); --e:in std_logic; y:out std_logic); end mux81; architecture Behavioral of mux81 is component mux is port(i:in std_logic_vector(3 downto 0); s:in std_logic_vector(1 downto 0); e:in std_logic; y:out std_logic); end component; signal z1,z2:std_logic; begin process e is begin if e=0 then b1:mux port map(i(3 downto 0),s(1 downto 0),not(s(2)),z1); b2:mux port map(i(7 downto 4),s(1 downto 0),s(2),z2); y<=z1 or z2; else y<=0; end if; end process; end Behavioral; Results:

Program 3

Aim: To design a 1x4 Demultiplexer. System description : Demultiplexers take one data input and a number of selection inputs, and they have several outputs. They forward the data input to one of the outputs depending on the values of the selection inputs. Demultiplexers are sometimes convenient for designing general purpose logic, because if the demultiplexer's input is always true, the demultiplexer acts as a decoder. This means that any function of the selection bits can be constructed by logically OR-ing the correct set of outputs. Executions: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity demux1x4 is port(x:in std_logic; y:out std_logic_vector(3 downto 0); s:in std_logic_vector(1 downto 0)); end demux1x4; architecture Behavioral of demux1x4 is begin process(s,x) is begin case s is when "00"=>y(0)<=x;y(1)<='Z';y(2)<='Z';y(3)<='Z'; when "01"=>y(0)<='Z';y(1)<=x;y(2)<='Z';y(3)<='Z'; when "10"=>y(0)<='Z';y(1)<='Z';y(2)<=x;y(3)<='Z'; when others=>y(0)<='Z';y(1)<='Z';y(2)<='Z';y(3)<=x; end case; end process; end Behavioral; Results:

Program 4

Aim: To design a 4x2 priority encoder . System description : A priority encoder is a circuit or algorithm that compresses multiple binary inputs into a smaller number of outputs. The output of a priority encoder is the binary representation of the ordinal number starting from zero of the most significant input bit. They are often used to control interrupt requests by acting on the highest priority request. If two or more inputs are given at the same time, the input having the highest priority will take precedence. An example of a single bit 4 to 2 encoder is shown, where highest-priority inputs are to the left and "x" indicates an irrelevant value - i.e. any input value there yields the same output since it is superseded by higher-priority input. I3 I2 I1 I0 O1 O0 0 0 0 x 0 0 0 0 1 x 0 1 0 1 x x 1 0 1 x x x 1 1 4 to 2 priority encoder Executions:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity pEncoder4x2 is port(x:in std_logic_vector(3 downto 0); e:in std_logic; a:out std_logic; y:out std_logic_vector(1 downto 0)); end pEncoder4x2; architecture Behavioral of pEncoder4x2 is begin process(x,e) is begin if e='1' then case x is when "0000"=>y<="00";a<='0'; when "0001"=>y<="00";a<='1'; when "0010"=>y<="01";a<='1';

when "0011"=>y<="01";a<='1'; when "0100"=>y<="10";a<='1'; when "0101"=>y<="10";a<='1'; when "0110"=>y<="10";a<='1'; when "0111"=>y<="10";a<='1'; when others=>y<="11";a<='1'; end case; else y<="00"; a<='0'; end if; end process; end Behavioral;

Results:

Program 5

Aim: To design a D flip flop. System decription

D flip-flop symbol The D ip-op is the most common flip-flop in use today. It is better known as data or delay flip-flop (as its output Q looks like a delay of input D). The Q output takes on the state of the D input at the moment of a positive edge at the clock pin (or negative edge if the clock input is active low).[23] It is called the D flip-flop for this reason, since the output takes the value of the D input or data input, and delays it by one clock cycle. The D flip-flop can be interpreted as a primitive memory cell, zero-order hold, or delay line. Whenever the clock pulses, the value of Qnext is D and Qprev otherwise. Truth table: Clock Rising edge Rising edge NonRising D Q 0 0 1 1 X Qpre
v

Qpre
v

X X

('X' denotes a Don't care condition, meaning the signal is irrelevant)

Execution library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dff is

port(d:in bit; q:out bit; clk:in bit); end dff; architecture Behavioral of dff is signal ds:bit; begin process(clk) is begin if(clk'event and clk='1') then ds<=d; end if; end process; process(ds) is begin q<=ds; end process; end Behavioral;

Result:

Program 6

Aim: To design a JK flip flop. System decription The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R = 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will hold the current state. The characteristic equation of the JK flip-flop is:

and the corresponding truth table is: JK Flip Flop operation[25] Characteristic Excitation table table JK Qnex Comme Qne Comme Q JK nt nt t xt hold state reset set 0 0 0X 0 1 1X 1 0 X1 No change Set Reset No change

00 Q 01 0 10 1 11 Q

toggle 1 1 X 0

Execution library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity jkff is port(j,k:in bit; q:out bit clk:in bit); end jkff;

architecture Behavioral of jkff is signal jks:bit;

begin process(clk) is -constant delay :time :=450 ps; variable jk:bit_vector(1 downto 0); begin if (clk'event and clk='1') then jk:=j&k; case jk is when "00"=>jks<=jks after 1 ns; when "01"=>jks<='0' after 1 ns; when "10"=>jks<='1' after 1 ns; when others=>jks<=not (jks) after 1ns; end case; end if; end process; process(jks) is begin q<=jks; end process; end Behavioral; Result:

Program 7

Aim: To design a universal shift register. System decription The purpose of the parallel-in/ parallel-out shift register is to take in parallel data, shift it, then output it as shown below. A universal shift register is a do-everything device in addition to the parallel-in/ parallel-out function.

Above we apply four bit of data to a parallel-in/ parallel-out shift register at DA DB DC DD. The mode control, which may be multiple inputs, controls parallel loading vs shifting. The mode control may also control the direction of shifting in some real devices. The data will be shifted one bit position for each clock pulse. The shifted data is available at the outputs QA QB QC QD . The "data in" and "data out" are provided for cascading of multiple stages. Though, above, we can only cascade data for right shifting. We could accommodate cascading of left-shift data by adding a pair of left pointing signals, "data in" and "data out", above. Execution library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uni_shifter is port(s:in std_logic_vector(1 downto 0); --00 no shift;01 right shift;10 left shift;11 load; i:in std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end uni_shifter; architecture Behavioral of uni_shifter is signal isig:std_logic_vector(3 downto 0);

begin -- isig<=i; process(s) is begin case s is when "00"=> isig<=isig; when "01"=> isig(0)<=i(1); isig(1)<=i(2); isig(2)<=i(3); isig(3)<='0'; when "10"=> isig(0)<='0'; isig(1)<=i(0); isig(2)<=i(1); isig(3)<=i(2); when others=> isig<=i; end case; end process; process(isig) is begin y<=isig; end process; end Behavioral;

Result:

PROGRAM 8
Aim: Implementation of Barrel shifter in behavioral model. THEORY: A barrel shifter is a digital circuit that can shift a data word by a specified number of bits in one clock cycle. It can be implemented as a sequence of multiplexers (mux), and in such an implementation the output of one mux is connected to the input of the next mux in a way that depends on the shift distance.

Execution: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity barrel_shifter is port(ins:in std_logic_vector(7 downto 0);--input bit stream outs:out std_logic_vector(7 downto 0);--output bit stream; n:in std_logic_vector(2 downto 0);--number of shift in single clk cycle d:in std_logic;--direction of shift=>0=right shift;1=left shift clk:in std_logic);--clock end barrel_shifter; architecture Behavioral of barrel_shifter is signal k:integer; signal temp:std_logic_vector(7 downto 0); begin process (n) is begin case n is when "000"=>k<=0; when "001"=>k<=1; when "010"=>k<=2; when "011"=>k<=3; when "100"=>k<=4; when "101"=>k<=5; when "110"=>k<=6; when others=>k<=7; end case; end process; process (clk,ins,d) is variable j:integer; begin if clk='1' and clk'event then if d='1' then for j in 0 to 7 loop if j>=k then

temp(j)<=ins(j-k); else temp(j)<='0'; end if; end loop; else for j in 0 to 7 loop if j>=k then temp(j-k)<=ins(j); else temp(7-j)<='0'; end if; end loop; end if; end if ; end process; process(temp)is begin outs<=temp; end process; end Behavioral; RESULT: LEFT SHIFT 3 BITS:

RIGHT SHIFT 3 BITS

PROGRAM 9
Aim: Implementation of pulse counter in behavioral model. THEORY: A pulse counter counts the numbers of pulses in a given clock as an input under a sampling environment .It also provide the information of counting overflow. Block diagram

Execution: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity pulse_counter is generic (max:natural:=64); port(clk,sample:in std_logic; count:out integer range 0 to max-1; overflow:out boolean); end pulse_counter; architecture Behavioral of pulse_counter is begin process(clk,sample)is variable lc:natural;--local counter --signal sc:boolean;--start counting begin

if clk'event and clk='1' then if sample='1' then lc:=lc+1; if lc>=max then overflow<=true; lc:=0; else overflow<=false; end if; else lc:=lc; end if; end if; count <=lc; end process; end Behavioral; RESULT:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --detection of sequence..1011 entity sequence_detector is port(i,clk:in std_logic; z:out std_logic; reset:in std_logic); end sequence_detector; architecture Behavioral of sequence_detector is type stattype is (a,b,c,d); signal state:stattype; begin process (clk,i,reset) is begin if (reset='1') then z<='0'; state<=a; elsif(rising_edge(clk)) then z<='0'; case state is when a=> if i<='1' then state<=b; else state<=a; end if; when b=> if i<='0' then state<=c; else state<=b; end if; when c=> if i<='1' then state<=d; else state<=a;

end if; when d=> if i<='1' then state<=a; z<='1'; else state<=c; end if; when others=> NULL; end case; end if; end process; end Behavioral;