UTC 4052

ANALOG MULTIPLEXERS /DEMULTIPLEXERS

DESCRIPTION
The UTC 4052 analog multiplexers is digitally controlled analog switch. The device feature low ON impedance and very low OFF leakage current. Control of analog signals up to the complete supply voltage range can be achieved.

CMOS

SOP-16

FEATURES
*Triple Diode Protection on Control Inputs *Switch Function is Break Before Make *Supply Voltage Range=3.0 Vdc to 18 Vdc *Analog Voltage Range(VDD-VEE)=3.0 to 18V *Note:VEE must beVss *Linearized Transfer Characterisstics *Low-noise-12nV/Cycle ,f1.0kHz Typical

DIP-16

ABSOLUTE MAXIMUM RATINGS*1

PARAMETER SYMBOL RATING UNIT
V V mA mA mW C C C VDD -0.5 ~ +18.0 DC Supply Voltage (Referenced to VEE,VssVEE) Input or Output Voltage (DC or Transient) (Referenced to Vin,Vout -0.5 ~ VDD+0.5 Vss for Control Inputs and VEE for switch I/O) Input Current (DC or Transient) per Control Pin Iin 10 Switch Through Current ISW 25 Power Dissipation *2 700 PD DIP-16 500 SOP-16 Ambient Temperature Range TA -55 ~ +125 Storage Temperature Range Tstg -65 ~ +150 Lead Temperature (8-Second Soldering) TLEAD 260 *1. Maximum Ratings are those values beyond which damage to the device may occur. *2. Temperature Derating : 7.0 mW/ From 65 ~ 125

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UTC 4052
Dual 4-Channel Analog Multiplexer/Demultiplexer
6 CONTROLS 10 9 12 14 SWITCHES IN/OUT 15 11 1 5 2 4 INHIBIT A B X0 X1 X2 X3 Y0 Y1 Y2 Y3 Y 9 Y1 INH VEE Vss X 13 Y2 COMMONS OUT/IN Y Y3 2 3 4 5 6 7 8 15 14 13 12 11 10 9 Y0

CMOS
PIN ASSIGMENT
1 16 VDD X2 X1 X X0 X3 A B

VDD=PIN16, VSS=PIN8, VEE=PIN7 Note: Control Inputs referenced to Vss. Analog Inputs and Outputs reference to VEE. VEE must be <Vss.

ELECTRICAL CHARACTERISTICS
PARAMETER SYMBOL TEST CONDITIONS -55C MIN MAX MIN
3.0 18 3.0

25C 125C UNIT TYP*3 MAX MIN MAX

18 3.0 18 V

SUPPLY REQUIREMENTS (Voltages Referenced to VEE) Power Current Per VDD VDD-3.0VssVEE Range Quiescent Current Per Package IDD

Control Inputs: Vin=Vss or VDD,Switch I/O : VEEVI/OVDD, andVswitch500mV *4 5.0 0.005 5.0 VDD=5.0V 10 0.010 10 VDD=10V 20 0.015 20 VDD=15V Total Supply Current ID(AV) TA=25only (The (Dynamic Plus channel component, Quiescent, Per (Vin-Vout) /Ron, is not Package included.) VDD=5.0V (0.07A/kHz)f+IDD VDD=10V Typical (0.20A/kHz)f+IDD VDD=15V (0.36A/kHz)f+IDD CONTROL INPUTS-INHIBIT, A, B, C (Voltages Referenced to Vss) Low-Level Input VIL Ron=per spec, Voltage Ioff=per spec VDD=5.0V 1.5 2.25 1.5 3.0 4.50 3.0 VDD=10V 4.0 6.75 4.0 VDD=15V High-Level Input VIH Ron=per spec, Voltage Ioff=per spec 3.5 3.5 2.75 3.5 VDD=5.0V 7.0 7.0 5.50 7.0 VDD=10V 11 11 8.25 11 VDD=15V

150 300 600

1.5 3.0 4.0

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PARAMETER SYMBOL TEST CONDITIONS -55C MIN MAX MIN
Input Leakage Iin VDD=15V ,Vin=0 or VDD 0.1 10-5 0.1 Current Input Capacitance Cin 5.0 7.5 SWITCHES IN/OUT AND COMMONS OUT/IN X,Y,Z(Voltages Referenced to VEE) Recommended VI/O Peak-to-Peak Voltage Into or Out of the Switch Recommended Static Vswitch or Dynamic Voltage Across the Switch *4 (Figure 3) Output Offset Voo Voltage ON Resistance Ron Channel On or Off 0 VDD 0 VDD

CMOS
25C 125C UNIT TYP*3 MAX MIN MAX
1.0 A pF 0 VDD Vpp

Channel On

600

600

300

mV

Vin=0V,No Load Vswitch500mV * Vin=VIL or VIH (Control), and Vin=0 to VDD(Switch) VDD=5.0V VDD=10V VDD=15V VDD=5.0V VDD=10V VDD=15V
4

10

800 400 220 70 50 45

100

250 120 80 25 10 10 0.05

1050 500 280 70 50 45

100

1200 520 300 135 95 65

1000

ON Resistance Between Any Two Channels in the Same Package Off-Channel Leakage Current(Figure 8)

Ron

Ioff

VDD=15V ,Vin=VIL or VIH

(Control) Channel to Channel or Any One Channel

nA

Capacitance, CI/O Inhibit=VDD 10 pF Switch I/O Capacitance, CO/I Inhibit=VDD 32 pF Common O/I Capacitance, CI/O Pins Not Adjacent 0.15 pF Feedthrough Pins Adjacent 0.47 (Channel Off) *3. Data labeled Typ is not to be used for design purposes, but is intended as an indication of the ICs potential *performance. *4. For voltage drops across the switch (Vswitch) > 600 mV ( > 300 mV at high temperature), excessive VDD *current may be drawn, i.e. the current out of the switch may contain both VDD and switch input components. The *reliability of the device will be unaffected unless the Maximum Ratings are exceeded. (See first page of this data *sheet.)

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ELECTRICAL CHARACTERISTICS *5 (CL = 50 pF, TA = 25) (VEE
PARAMETER
Propagation Delay Times(Figure 4) Switch Input to Switch Output Propagation Delay Times(Figure 4) Inhibit to Output

CMOS
VSS unless otherwise indicated)

SYMBOL
tPLH,tPHL RL=10k

TEST CONDITIONS VDD-VEE= 5.0, tPLH,tPHL=(0.17 ns/pF) CL+21.5 ns VDD-VEE=10, tPLH,tPHL=(0.08 ns/pF) CL+8.0 ns VDD-VEE=15, tPLH,tPHL=(0.06 ns/pF) CL+7.0 ns

MIN TYP
30 12 10

*6

MAX UNIT
75 30 25 ns

Propagation Delay Times(Figure 4) Control Input to Output Second Harmonic Distortion Bandwidth (Figure 5)

tPHZ,tPLZ RL=10k,VEE=Vss tPZH,tPZL Output1 or 0 to High Impedance, or High Impedance to1 or 0 Level VDD-VEE= 5.0 VDD-VEE=10 VDD-VEE=15 tPLN,tPHL RL=10k,VEE=Vss VDD-VEE= 5.0 VDD-VEE=10 VDD-VEE=15 RL=10k, f=1kHz, Vin=5Vpp, VDD-VEE=10 BW RL=1k, Vin=1/2(VDD-VEE)p-p, CL=50pF, 20 Log (Vout/Vin)=-3dB, VDD-VEE=10 RL=1k, Vin=1/2(VDD-VEE)p-p, Fin=30MHz, VDD-VEE=10

300 155 125 325 130 90 0.07 17

600 310 250 650 260 180

ns

ns % MHz

Off Channel -50 Feedthrough Attenuation dB (Figure 5) Channel Separation -50 RL=1k, Vin=1/2(VDD-VEE)p-p, fin=3.0MHz, dB (Figure 6) VDD-VEE=10 Crosstalk ,Control Input 75 R1=1k, RL=10k, to Common O/I (Figure mV Control tTLH=tTHL=20ns ,Inhibit=Vss), VDD-VEE=10 7) *5. The formulas given are for the typical characteristics only at 25 . *6. Data labelled Typ is not lo be used for design purposes but In intended as an indication of the ICs potential *performance.

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VDD IN/OUT VDD VDD OUT/IN

CMOS

VEE

VDD LEVEL CONVERTED CONTROL VEE Figure 1.Switch Circuit Schematic

16 INH A B ON Switches X0 Y0 X0 Y1 X1 Y2 X2 Y3 X3 None X1 X2 X3 Y0 Y1 Y2 Y3 12 14 15 11 1 5 2 4 Figure 2. Functional Diagram 3 Y 13 X 6 10 9 LEVEL CONVERTER 8 Vss 7 VEE VDD BINARY TO 1-OF-4 DECODER WITH INHIBIT

IN/OUT CONTROL

OUT/IN

TRUTH TABLE Control Inputs Select Inhibit 0 0 0 0 1 B 0 0 1 1 X A 0 1 0 1 X

* X=Don't Care

TEST CIRCUITS

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ON SWITCH CONTROL SECTION OF IC V SOURCE PULSE GENERATOR A B C LOAD INH

CMOS
Vout RL CL

VDD VEE Figure 3.V Across Switch

VEE VDD

Figure 4. Propagation Delay Times, Control and Inhibit to Output

A,B,and C inputs used to tum ON or OFF the switch under tes.

A B C A B C

RL ON OFF Vout RL
Vin

Vout
Vss INH

RL
Vin

CL=50pF

INH

CL=50pF

VDD VEE 2 Figure 5. Bandwidth and Off-Channe Feedthrough Attenuation

VDD VEE 2 Figure 6. Channel Separation (Adjacent Channels Used For Setup)

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A B C CONTROL SECTION OF IC

CMOS
OFF CHANNEL UNDER TEST

INH

RL R1

Vout CL=50pF

OTHER CHANNEL(S)

VDD VEE VEE VDD VEE VDD

COMMON

Figure 7. Crosstalk,Control Input to Common O/I VDD

Figure 8. Off Channel Leakage

KEITHLEY 160 DIGITAL MULTIMETER

10K 1k RANGE
X-Y PLOTTER

VDD VEE=VSS

Figure 9. Channel Resistance(RON) Test Circuit

TYPICAL RESISTANCE CHARACTERISTIS

RON,"ON" RESISTANCE (OHMS)

350 RON,"ON" RESISTANCE (OHMS) 300 250 200 150 100 50 TA=125 25 -55

350 300 250 200 150 100 50 TA=125 25 -55

0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 Vin,INPUT VOLTAGE (VOLTS) Figure10.VDD=7.5V,VEE=-7.5V

0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 Vin,INPUT VOLTAGE (VOLTS) Figure11.VDD=5.0V,VEE=-5.0V

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700 600 RON,"ON" RESISTANCE (OHMS) 500 400 300 200 100 0 -10 -8.0 -6.0 -4.0 -2.0 0 0.2 4.0 6.0 8.0 10 TA=125 25 -55 RON,"ON" RESISTANCE (OHMS) 350 TA=25 300 250 200 150

CMOS
VDD=2.5V

5.0V 100 50 0 -10 7.5V

-8.0

-6.0

-4.0

-2.0

0.2

4.0

6.0

8.0

10

Vin,INPUT VOLTAGE (VOLTS) Figure12.VDD=2.5V,VEE=-2.5V

Vin, INPUT VOLTAGE (VOLTS) Figure13 Comparison at 25,VDD=-VEE

Figure A illustrates use of the onchip level converter detailed in Figures 2. The 0 ~ 5 V Digital Control signal is used to directly control a 9 Vpp analog signal. The digital control logic levels are determined by VDD and VSS. The VDD voltage is the logic high voltage; the VSS voltage is logic low. For the example, VDD = + 5 V = logic high at the control inputs; VSS = GND = 0 V = logic low. The maximum analog signal level is determined by VDD and VEE. The VDD voltage determines the maximum recommended peak above VSS. The VEE voltage determines the maximum swing below VSS. For the example, VDD VSS = 5 V maximum swing above VSS; VSS VEE = 5 V maximum swing below VSS. The example shows a 4.5 V signal which allows a 1/2 volt margin at each peak. If voltage transients above VDD and/or below VEE are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure B. These diodes should be small signal types able to absorb the maximum anticipated current surges during clipping. The absolute maximum potential difference between VDD and VEE is 18.0 V. Most parameters are specified up to 15 V which is the recommended maximum difference between VDD and VEE. Balanced supplies are not required. However, VSS must be greater than or equal to VEE. For example, VDD = + 10 V, VSS = + 5 V, and VEE 3 V is acceptable. See the Table below.

+5V VDD +5V 9 Vp-p SWITCH ANALOG SIGNAL I/O Vss VEE

-5V

+4.5V
COMMON O/I

9 Vp-p ANALOG SIGNAL

EXTERNAL CMOS DIGITAL CIRCUITRY

4052
0 ~ 5V DIGITAL CONTROL SIGNALS
INHIBIT, A,B,C

GND -4.5V

Figure A. Application Example

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V DD Dx AN ALO G I/O Dx VEE VEE C O MMO N O /I Dx V DD Dx

CMOS

Figure B.External G ermanium or Schottky C lipping D iodes

POSSIBLE SUPPLY CONNECTIONS

VDD IN VOLTS
+8 +5 +5 +5 +10

VSS IN VOLTS
0 0 0 0 +5

VEE IN VOITS
-8 -12 0 -5 -5

CONTROL INPUTS LOGIC HIGH/LOGIC LOW IN VOLTS

+8/0 +5/0 +5/0 +5/0 +10/+5

MAXIMUM ANALOG SIGNAL RANGE IN VOLTS

+8 ~ -8=16Vp-p +5 ~12=17Vp-p +5 ~ 0=5Vp-p +5 ~ -5=10Vp-p +10 ~ 5=15Vp-p

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