Lecture 20

Today we will Look at why our NMOS and PMOS inverters might not be the best inverter designs Introduce the CMOS inverter Analyze how the CMOS inverter works

NMOS Inverter
5V R
ID = 5/R
D

When VIN is logic 1, VOUT is logic 0.

5V R
ID = 0
D

VIN
5V

Constant nonzero VOUT current flows through transistor.

0V

VOUT
5V

+ VDS _

VIN Power is used even though no new 0V computation is being performed.

+ VDS _

When VIN changes to logic 0, transistor gets cutoff. ID goes to 0. Resistor voltage goes to zero. VOUT pulled up to 5 V.

PMOS Inverter
5V When VIN is logic 0, VOUT is logic 1. Constant nonzero VIN
5V ID = 0

5V

VIN
0V ID = -5/R

current flows through VDS VOUT transistor. + 5V

VDS VOUT + 0V

Power is used even though no new computation is being performed.

When VIN changes to logic 1, transistor gets cutoff. ID goes to 0. Resistor voltage goes to zero. VOUT pulled down to 0 V.

Analysis of CMOS Inverter

VDD (Logic 1)
S

D D

VOUT

We can follow the same procedure to solve for currents and voltages in the CMOS inverter as we did for the single NMOS and PMOS circuits. Remember, now we have two transistors so we write two I-V relationships and have twice the number of variables. We can roughly analyze the CMOS inverter graphically.

VIN

NMOS is pull-down device PMOS is pull-up device Each shuts off when not pulling

NMOS Inverter
ID saturation mode VGS = 3 V

X Linear ID vs VDS given by surrounding circuit X VGS = 1 V VDS

Linear KVL and KCL Equations

+
(p) V GS

VDD (Logic 1)
S

VGS(n) = VIN VGS(p) = VIN VDD

D D

VOUT + VDS(n) _

VGS(p) = VDS(n) - VDD ID(p) = -ID(n) VDS(n) = VOUT VDS(p) = VOUT VDD VDS(p) = VDS(n) - VDD

VIN
+V
GS(n )

Use these equations to write both I-V equations in terms of VDS(n) and ID(n)

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 0.9 V VDS(n) VDD

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 1.5 V VDS(n) VDD

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 2.0 V VDS(n) VDD

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 2.5 V VDS(n) VDD

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 3.0 V VDS(n) VDD

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 3.5 V VDS(n) VDD

CMOS Analysis
ID(n) As VIN goes up, VGS(n) gets bigger and VGS(p) gets less negative.
NMOS I-V curve PMOS I-V curve (written in terms of NMOS variables)

VIN = VGS(n) = 4.1 V VDS(n) VDD

CMOS Inverter VOUT vs. VIN

VOUT VDD
NMOS: cutoff PMOS: triode NMOS: saturation PMOS: triode NMOS: triode PMOS: saturation both sat. curve very steep here; only in C for small interval of VIN NMOS: triode PMOS: cutoff

VIN VDD

ID

CMOS Inverter ID

VDD

VIN

Important Points
No ID current flow in Regions A and E if nothing attached to output; current flows only during logic transition If another inverter (or other CMOS logic) attached to output, transistor gate terminals of attached stage do not permit current: current still flows only during logic transition
VDD S D VIN D VOUT1 VDD S D D VOUT2