EE 215E Signaling and Synchronization Lecture 8: PLL Basics

Sudhakar Pamarti, S dh k P ti University of California, Los Angeles

References
F. M. Gardner, Phaselock Techniques, Wiley Interscience F. M. Gardner, Charge Pump Phase Locked Loops, IEEE Transactions on Communications, vol. COM-28, no. 11, Nov 1980, pp. 1980 pp 18491858 J. Hein, J. Scott, z-Domain Model for Discrete-Time PLLs IEEE Trans on Circuits and Systems, Nov 1988 M. Perrott, al A M Perrott et al, A modeling approach for - fractional-N frequency synthesizers allowing straightforward noise analysis, IEEE JSSC, August 2002, pp. 1028-1038

S. Pamarti

Lecture Topics
Basic operation Type I vs. Type II PLLs Charge pump PLL
Continuous time model Linear analysis stability closed loop phase transfer function stability, Control voltage ripple

Linear, time-variant charge pump PLL models

S. Pamarti

Lecture Topics
Basic operation Type I vs. Type II PLLs Charge pump PLL
Continuous time model Linear analysis stability closed loop phase transfer function stability, Control voltage ripple

Linear, time-variant charge pump PLL models

S. Pamarti

Basic Operation

Negative feedback loop

In steady state, Out and Ref have a well-defined phase relationship E.g., they have the same frequency and same phase

Many applications
Frequency synthesis Synchronization of clocks Frequency discrimination q y
S. Pamarti

Voltage Control Oscillator

Ring/LC, differential/single-ended oscillators More on VCOs later
VCO

KVCO

ctrl

FVCO (t ) = KVCOVctrl (t ) rad / s, d VCO (t ) =

KVCOVctrl ( )d radians

S. Pamarti

Frequency Divider

Counts integer number of VCO cycles

Synchronous or asynchronous implementations

Many implementations
Static CMOS dynamic logic current mode logic (CML) CMOS, logic,

1 div (t ) = VCO (t ) N
S. Pamarti

Phase Comparator/Detector
0

err

err = ref div

0

err

Generates a voltage proportional to phase difference of inputs

More later on implementations

A PD gain can be defined, on average:

Vavg (t ) K PD (ref (t ) div (t ) 0 )

S. Pamarti

Loop Filter, F(s)

Many implementations
Passive, active, sampled More in later lectures

Filter classification
Based on number of integrators in F(s) Type I: no integrators Type II: one integrator Based on number of poles in F(s) 1st order, 2nd order, 3rd order, etc. d d d t

1 + s 2 Type I : F (s ) = 1, F (s ) = yp , , 1 + s 1 1 + s 2 1 + s 2 Type II : F (s ) = , F (s ) = . s s(1 + s p )

S. Pamarti

A Simple PLL Model

0 (t ) err

reff (t )

K PD div (t )

Vavg (t )

F (s )

Vctrl (t ) KVCO s

VCO (t )

1 N

Negative feedback loop tries to force err(t) = 0

In steady state i.e. in lock FVCO = N*Fref

More accurate models are required

Many components have discrete time operation

Reference: See Floyd Gardners Phaselock Techniques, Wiley Interscience for more details
S. Pamarti

Lecture Topics
Basic operation Type I vs. Type II PLLs Charge pump PLL
Continuous time model Linear analysis stability closed loop phase transfer function stability, Control voltage ripple

Linear, time-variant charge pump PLL models

S. Pamarti

Example Type I PLL

err (t )

ref (t )

VCTRL (t ) K ICP I avg (t ) VCO F (s ) 2 s 1 div (t ) N

VCO (t )

Example Type I loop filter

F (s ) = 1.

Non-zero values of Vctrl require that err 0 Leads to large phase errors
S. Pamarti

Type I, 1st Order PLL

0 (t ) err

reff (t )

F (s ) = 1 Vavg (t ) V (t ) KVCO K PD F (s ) ctrl s div (t ) 1 N

VCO (t )

Follows from standard linear systems theory that

VCO (s ) N 1 = , K = K PD KVCO rad / s ref (s ) 1+s K N

This PLL is inherently stable It has 1st order settling behavior

VCO (s ) N 1 = , K = K PD KVCO rad / s d ref (s ) 1+s K N
S. Pamarti

Type I, 1st Order PLL

0 (t ) err

reff (t )

F (s ) = 1 Vavg (t ) V (t ) KVCO K PD F (s ) ctrl s div (t ) 1 N

VCO (t )

A frequency step, initial will result in

initial err (t ) = 1 e Kt ) ( K
i.e. i e err 0 The filter can not remember the required Vctrl value So, Vavg 0 is required Not good for many applications
S. Pamarti

Other Type I PLL Problems

Gain < 0 Ref Div Vavg Gain > 0

err

PLL may go out of lock for large err Cycle slipping

Suppose Ref and Div have a frequency difference err can change in large jumps Remember: the frequency error accumulates as err Phase detector gain changes frequently Could be +ve or ve So, frequency of Div could show wild variations

Problems due to an inability to detect frequency error

S. Pamarti

Example Type II PLL : Charge Pump PLL

Ref ICP Div Up Vctrl
VCO

Up Dn

Dn D ICP

R C2

Vctrl

Current sources dump charge proportional to phase difference into a capacitor, C2 The capacitor, C2, stores/remembers Vctrl So, So err = 0
S. Pamarti

Lecture Topics
Component description Type I vs. Type II PLLs Type II, charge pump PLL
Continuous time model Linear analysis stability closed loop phase transfer function stability, Control voltage ripple

Linear, time-variant charge pump PLL model

S. Pamarti

Phase Frequency Detector

err 2

Up and Dn together contain the phase error information

Their time difference is proportional to the p p p phase error

S. Pamarti

Phase Frequency Detector

err
err 2
err = ref div

Up and Dn together contain the phase error information

Their time difference is proportional to the p p p phase error

A proportional voltage or current can be generated for F(s)

A charge pump is best suited for this purpose

S. Pamarti

Charge Pump Integer-N PLLs: LTI Model

err (t )

ref (t )

VCTRL (t ) K ICP I avg (t ) VCO F (s ) 2 s 1 div (t ) N

VCO (t )

Tref
err

Tref

Assumption: CP produces an average current during each g reference period.

Linear, time-invariant model

err avg

ICP

ICP

Ignores the non-linearity of the PFD Ignores position and width of current pulses Reasonable approximation for low bandwidth PLLs
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ICP

err = ICP err Tref 2

Common Charge Pump Integer-N PLLs

err (t )

ref (t )

VCTRL (t ) K ICP I avg (t ) VCO F (s ) 2 s 1 div (t ) N

VCO (t )

Loop filter is usually of Type II

S. Pamarti

Common Charge Pump Integer-N PLLs

err (t )

ref (t )

VCTRL (t ) K ICP I avg (t ) VCO F (s ) 2 s 1 div (t ) N

VCO (t )

Loop filter is usually of Type II

1 + s 2 F (s ) = R s s
2

S. Pamarti

RC 2 ,

Common Charge Pump Integer-N PLLs

err (t )

ref (t )

VCTRL (t ) K ICP I avg (t ) VCO F (s ) 2 s 1 div (t ) N

VCO (t )

Loop filter is usually of Type II

1 + s 2 F (s ) = R s s2
S. Pamarti

RC 2 ,

Common Charge Pump Integer-N PLLs

err (t )

ref (t )

VCTRL (t ) K ICP I avg (t ) VCO F (s ) 2 s 1 div (t ) N

VCO (t )

Loop filter is usually of Type II

1 + s 2 F (s ) = R s s2
S. Pamarti

b 1 1 + s 2 F (s ) = R b s (1 + s ) p 2

RC 2 ,

1+

C2 , p C1

C 1C 2 = 2 C1 + C 2 b

Common Charge Pump PLLs: Stability

20log10|T(j)|

T (s ) =

s 2 (1 + s p )
2

K (1 + s 2 )

0 dB

1/2

1/p = b/2

b 1 ICP KVCO R K = b 2N , PM tan1 (K 2 ) tan1 K 2 b

Unity gain freq.

S. Pamarti

Common Charge Pump PLLs: Stability

20log10|T j) Angle T j) 90

T (s ) =
PM 0 dB 1/2 K 180 1/p = b/2

s 2 (1 + s p )
2

K (1 + s 2 )

b 1 ICP KVCO R K = b 2N , PM tan1 (K 2 ) tan1 K 2 b

Unity gain freq.

Two poles at s = 0 cause instability The zero provides phase margin (PM)
Large K2 values give better PM

S. Pamarti

Common Charge Pump PLLs: Stability

20log10|T(j)| Angle{T(j)} 90 Decreasing b 180 1/p = b/2

T (s ) =

s 2 (1 + s p )
2

K (1 + s 2 )

0 dB

1/2

b 1 ICP KVCO R K = b 2N , PM tan1 (K 2 ) tan1 K 2 b

Decreasing b

Two poles at s = 0 cause instability The zero provides phase margin

Large K2 values give better PM Large b gives b L i better PM typically, b > 16 i used PM: i ll is d
S. Pamarti

Common CP PLLs: Closed Loop Response

N (1 + s 2 ) , 2 3 1 + s 2 + s 2 K + s 2 p K

A (s ) =

b 1 ICP KVCO R where K = b 2N ,

A pole-zero doublet exists at the zero location pole zero

Magnitude response of A(s) rises at the doublet Doublet slows down settling response

Decreasing b or K2 increases peaking

Frequency where peaking occurs is not necessarily K

S. Pamarti

Common CP PLLs: Closed Loop Response

N (1 + s 2 ) , 2 3 1 + s 2 + s 2 K + s 2 p K

A (s ) =

b 1 ICP KVCO R where K = b 2N ,

A pole-zero doublet exists at the zero location pole zero

Magnitude response of A(s) rises at the doublet Doublet slows down settling response

Decreasing b or K2 increases peaking b K

Frequency where peaking occurs is not necessarily K F. M. Gardner, Charge Pump Phase Locked Loops, IEEE Transactions , g p p , on Communications, vol. COM-28, no. 11, Nov 1980, pp. 18491858. S. Pamarti

Simple Design Procedure

Given quantities Calculate b:
Fref, N, KVCO (Hz/V), minimum phase margin, PMrequired required closed loop bandwidth, fBW (Hz)
PM required b 1 b tan 2
1

Calculate ICP, R, C2 such that

b 2NfBW f b ICP R = and RC 2 = d b 1 KVCO 2 fBW

Calculate C1 such that

C1 =

C2 b 1

Note: Multiple choices for (ICP, R, C2) are possible

Thermal noise, power considerations will help in making the choice noise More later

S. Pamarti

Integer-N PLL Design Issues

Sophisticated filter design is possible
Implementation concerns Not much room to play with

Several tools available

Mainly choose the components of a chosen filter structure Good example: Michael Perrotts PLL Design tool

The challenging problems in PLL design are usually elsewhere

Dealing with component variability How much phase margin is enough phase margin ?

S. Pamarti

2nd Order Vs 3rd Order Type II CP PLLs

2nd order PLL is a special case of the 3rd order PLL

b = infinity y

However, analysis has been application specific

Digital, wired communication analyses focus on 2nd order PLL
PM = tan1 (K 2 ) A (s ) = where 0 = N 1 + 2 s 0

2 1 + 2 s 0 + s 2 0

1 ICP KVCO 1 , = 0RC 2 2N C2 2

S. Pamarti

2nd Order Vs 3rd Order Type II CP PLLs

2nd order PLL is a special case of the 3rd order PLL

b = infinity y

However, analysis has been application specific

Digital, wired communication analyses focus on 2nd order PLL
20log10|A(j)| Decreasing

PM = tan1 (K 2 ) A (s ) = where 0 = N 1 + 2 s 0

Prediction from 3rd order PLL with b = 1/2 0 K

20log10|N| dB

2 1 + 2 s 0 + s 2 0

1 ICP KVCO 1 , = 0RC 2 2N C2 2

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Control Voltage Ripple

ICP Up Vctrl Dn ICP

VCO

Up Dn C1 = 0

R C2

C1

Vctrl

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Control Voltage Ripple

ICP Up Vctrl Dn ICP

VCO

Up Dn C1 = 0

R C2

C1

Vctrl C1 0

The ripple on Vctrl causes periodic jumps in VCO phase

Causes spikes in power spectral density of VCO output Bad for both wireless and wire-line communications

S. Pamarti

Effect of 3rd Loop Filter Pole on Ripple

3rd pole atten ates the ripple and its effects attenuates
Small b is desired for more attenuation Recall: small b reduces phase margin

Often choose K to be the geometric mean of 1/2, and 1/p

Used this in the design procedure mentioned earlier
S. Pamarti

Lecture Topics
Component description Problems with Type I PLL
Continuous time model

Charge pump PLL

Continuous time model Linear analysis stability, closed loop phase transfer function Control voltage ripple

Linear, time-variant charge pump PLL models

S. Pamarti

Problems with Continuous Time Model

PFD compares the phase only once every reference cycle

So, only samples of the VCO phase are fed back Also causes delay in the phase feedback

The charge pump, and loop filter operation depends on the position and the width of the Up Dn pulses Up,

S. Pamarti

Sampling in Charge Pump PLLs

T0

sin (2 f0t ) sin (2 f0t + (t ))

th

n
th

Assumptions
The excess phase is small: | ( )| << 2 p |(t)| The excess phase does not change too much over n

Then,

(nT0 ) T0 n 2
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Charge Pump Impulse Approximation

ref (t )
fREF
err [n ] ref [n ] Tref err [n ]

I err (t )

2
div [n ]
fREF

F (s )

Vctrl (t ) KVCO s

VCO (t )

1 N

Charge pumps current pulses

ICP

err [n ]

ICP

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Charge Pump Impulse Approximation

ref (t )
fREF

err [n ] ref [n ] Tref

2
div [n ]

err [n ]
ITM

ICP

I err (t )

F (s )

fREF fREF

Vctrl (t ) KVCO s

VCO (t )

1 N

Charge pumps current pulses approximated as impulses

I err (t ) =

n =

CP err

[n ] (t nTref )

ICP

err [n ]

ICP

M. Perrott M Perrott, et al A modeling approach for - fractional-N frequency synthesizers al, A fractional N allowing straightforward noise analysis, IEEE JSSC, August 2002, pp. 1028-1038

S. Pamarti

Links to the Continuous-Time Model

1 Tref

ref (t )

Tref 2
fREF

1 Tref

ICP

I err (t )

F (s )

Vctrl (t ) KVCO s

VCO (t )

1 N

Two assumptions
Signal replicas are aggressively filtered by F(s) and the VCO Reasonable because of F(s) and VCO Sampling aliases are negligible Reasonable because VCO phase does not jump sharply Assumptions i A ti inaccurate as fBW fref/10 t

Same as the continuous-time model under these assumptions

S. Pamarti

Better Models for Charge Pump PLLs

ref (t )
fREF

err [n ] ref [n ] Tref

2
div [n ]

err [n ]
ITM

ICP

I err (t )

F (s ) 1 N

fREF fREF

Vctrl (t ) KVCO s

VCO (t )

How to analyze the PLL ?

Aliasing, Aliasing frequency replicas cause problems

Approach #1: linear, discrete-time model

Inaccurate as bandwidth increases relative to fref

Approach #2: non-linear model non linear

S. Pamarti

Linear, Discrete-Time Model

ref [n ] err [n ] Tref 2 2 err [n ]
ICP

Feq (z )

KVCO 1z
1

VCO [n ]

div [n ]

1 N

Replace the analog portions of the PLL with discrete time equivalents
Use impulse invariance to obtain Feq(z) from F(s) Implicit sampling at fs = fref Higher fs can be used: fs = m*fref, m is a +ve integer

Stability: T(z) instead of T(s)

F. M. Gardner, Charge Pump Phase Locked Loops, IEEE Transactions on Communications, vol. COM-28, no. 11, Nov 1980, pp. 18491858.

S. Pamarti

Linear, Discrete-Time Model

Better prediction of PLL beha ior than the contin o s time behavior continuous model
F. M. Gardner, Charge Pump Phase Locked Loops, IEEE Transactions on Communications, vol. COM-28, no. 11, Nov 1980, pp. 18491858.

S. Pamarti

Stability of the 2nd order Type II CP PLL

ref 1 + K< ref 2

Overload limit: too large a Vctrl ripple will put the VCO out of range
Depends on the VCO implementation Note: fBW < freff/10 is a conservative estimate of this limit It follows from |KVCOVctrl| < fVCO K < ref/2 S. Pamarti

Stability of the 3rd order Type II CP PLL

reff 1 a b 1 + 1 + a b ref 2 a =e
2 b ref 2

K<

Extra pole imposes a tighter limit on the bandwidth for stability

S. Pamarti

Effect of Feedback Delay in PLLs

Ref Div Up PFD Dn Charge Pump Ierr Divide-by N td Loop VCO Filter, F(s) V ctrl td Out

Non-zero delay in the feedback is common in PLLs

E.g., E g clock distribution in chip-to-chip I/O

S. Pamarti

Effect of Feedback Delay in PLLs

Ref Div Up PFD Dn Charge Pump Ierr Divide-by N td Loop VCO Filter, F(s) V ctrl td Out

Non-zero delay in the feedback is common in PLLs

E.g., E g clock distribution in chip-to-chip I/O

Feedback delay degrades the phase margin of the PLL

Discrete-time model can be used to analyze the degradation
ref [n ]
err [n ] Tref err [n ]

2
div [n ]

ICP

Feq (z )

KVCO 1z
1

VCO [n ]

td fref f

1 N

S. Pamarti

Effect of Feedback Delay in PLLs

Ref Div Up PFD Dn Charge Pump Ierr Divide-by N td Loop VCO Filter, F(s) V ctrl td Out

Non-zero delay in the feedback is common in PLLs

E.g., E g clock distribution in chip-to-chip I/O

Feedback delay degrades the phase margin of the PLL

Discrete-time model can be used to analyze the degradation
ref [n ]
err [n ] Tref err [n ]

2 div [n ]

ICP

Feq (z )
1 N

KVCO 1z
1

VCO [n ]

td fref f

Can be shown that

PM PMt
S. Pamarti

fBW td 360 =0

Non-Linear Model of the CP PLL

ICP

err [n ]

VCO (t ) = gs (t tref [n ]) gs (t tdiv [n ]), gs (t ) = step response of G (s ) t f F (s )KVCO / s

tref [n ]

tdiv [n ]

No convenient way of handling the non linear dependence of non-linear VCO(t) on err[n]
Taylors series approximation of gs(t) ? Possible area of research, particularly in fractional-N PLLs

Co t o theoretic et ods Control t eo et c methods

State-space approaches, non-linear differential/difference equations Phase plane plots to understand non-linear behavior
S. Pamarti

Phase Portraits of the CP PLL

Typically, plots of VCO Vs dVCO(t)/dt

The PLL may lock to equilibrium points

S. Pamarti