CAD TOOLS FOR VLSI SIMULATION Page 1

SIMULATION: DEFINITION, MOTIVATION

Simulation: to construct and test a computer model of the circuit to be built. * It is useful because the costs of simulation are far less than the costs of fabricating the circuit directly. * Simulation only models those aspects of the circuit relevant to the level of abstraction concerned. * For VLSI circuits simulation is not a guaranteed way of verification as it is impossible to enumerate all combinations of input patterns and internal states. However, simulation can increase the belief in the correctness of the design.

CAD TOOLS FOR VLSI SIMULATION Page 2

LEVELS OF SIMULATION
From the lowest level to higher levels: * Device-level simulation: + used to test the effect of fabrication parameters; + used by technologists, not by circuit or system designers. * Circuit-level simulation (e.g. SPICE): + analog; + nodal/tableau equations; + numerical integration; + DC analysis. * Timing-level simulation: + analog, but with simplifications (macromodels, look-up tables); + piecewise-linear methods.

CAD TOOLS FOR VLSI SIMULATION Page 3

LEVELS OF SIMULATION (Continued)

* Switch-level simulation: + transistors are modelled as bidirectional switches; + mainly digital; + circuits extracted from mask patterns can directly be simulated; + see later for more details. * Gate-level (or logic) simulation: + gate mainly refers to elements to be found in a component library (e.g. for standard-cell design): NAND, NOR, MULTIPLEXER, D-FLIPFLOP, LATCH, etc.; + unidirectional signal flow; + also used for fault simulation and automatic test pattern generation; + see later for more details.

CAD TOOLS FOR VLSI SIMULATION Page 4

LEVELS OF SIMULATION (Continued)

* Register-transfer simulation: + circuit is seen as registers to store the state and combinational logic to compute the next state (finite state machine model). registers

comb. logic

* Behavioral-level simulation: + description in high-level language, e.g. VHDL (VHSIC Hardware Description Language).

CAD TOOLS FOR VLSI SIMULATION Page 5

LEVELS OF SIMULATION (Continued)

+ descriptions at different levels of abstractions coexist within the same simulation environment; + critical parts of the design are described at a lower level than non-critical parts, while it is inefficient or infeasible to model the whole circuit at the level of the most critical part; + it might be easier to test a subsystem with stimuli from the system itself, rather than describing the stimuli explicitly; * Hardware-software cosimulation: + useful in hardware-software codesign; + requires combination of multiple simulation techniques.

CAD TOOLS FOR VLSI SIMULATION Page 6

COMPONENTS OF A SIMULATOR
SIMULATOR KERNEL: * the routines for doing the real simulation. * detailed description for event-driven simulation follows. ROUTINES FOR PROCESSING OF CIRCUIT DESCRIPTION: * input format: either written by the designer or obtained through an interface with a schematic entry tool. * internal format: machine code or tables. * input format has to be compiled into internal format.

CAD TOOLS FOR VLSI SIMULATION Page 7

COMPONENTS OF A SIMULATOR (Continued)

ROUTINES FOR STIMULI PROCESSING: * stimuli: the input patterns for all time instants during the simulation. * they have to provide the kernel with the correct input patterns. ROUTINES FOR OUTPUT PROCESSING: * the simulator results are numbers; they have to be presented in a user-friendly form, e.g. as tables or waveforms.

CAD TOOLS FOR VLSI SIMULATION Page 8

GATE-LEVEL SIMULATION
SIGNAL MODELING Signal values are, of course, discrete. The minimum set consists of 0, 1 and X. X means unknown. GATE MODELING * Gate models should deal with multiple-valued logic. * Gate behavior can be represented by truth tables or compiled code. Nand-gate: in 1 in 2 out
0 0 0 1 1 1 X X X 0 1 X 0 1 X 0 1 X 1 1 1 1 0 X 1 X X

CAD TOOLS FOR VLSI SIMULATION Page 9

GATE-LEVEL SIMULATION
DELAY MODEL * inertial delay: a change to an input signal has to last at least a certain time before it can trigger any reaction. * propagation (or transport) delay: some time passes between the start of a signal change at the gate input and the start of a signal change at its output. * rise/fall delay: due to capacitances that have to be loaded or unloaded, there is a time difference between the moment an output starts to change and the moment the output has reached its final value.

CAD TOOLS FOR VLSI SIMULATION Page 10

DELAY MODEL EXAMPLE

in_1 in_2 out

in_2 1 0 in_1 1 0 time 0 1 2 3 4 5 6 7 8 9 Prop. delay = 2: 0 time 0 1 2 3 4 5 6 7 8 9 Rise delay = 2, fall delay = 3: out 1 0 time 0 1 2 3 4 5 6 7 8 9 out

CAD TOOLS FOR VLSI SIMULATION Page 11

COMPILER-DRIVEN SIMULATION
* Based on making executable-code model of circuit; * Efficient simulation mechanism (few machine instructions per gate); * Applicable to few delay models in synchronous circuits (e.g. zero-delay model). registers

combinational logic

CAD TOOLS FOR VLSI SIMULATION Page 12

ZERO-DELAY EXAMPLE
A B C D E n1 n2 n3 n4 n5 n6 n8 n7 n9 F

 A;  B;  C;  D;  E;  OR(n , n );  AND(n , n );  AND(n , n );  OR(n , n ); Fn ;

n1 n2 n3 n4 n5 n6 n7 n8 n9
1 2 4 6 5 3 7 8 9

CAD TOOLS FOR VLSI SIMULATION Page 13

UNIT-DELAY SIMULATION
* Provides some information on signal evolution in time, especially to detect glitches. time 0 1 2 3 4 n 1 1 0 n 2 1 0 n 3 1 0 n 4 1 0 n 5 1 0 n 6 1 0 n 7 1 0 n 8 1 0 n 9 1 0

CAD TOOLS FOR VLSI SIMULATION Page 14

UNIT-DELAY SIMULATION (Ctd.)

Two-array technique:
for (t tstart ; t  tend ; t  t + 1) f new[1]  A; new[2]  B; new[3]  C; new[4]  D; new[5]  E; new[6]  OR(old[1], old[2]); new[7]  AND(old[4], old[5]); new[8]  AND(old[6], old[3]); new[9]  OR(old[7], old[8]); F  new[9]; old  new;

CAD TOOLS FOR VLSI SIMULATION Page 15

EVENT-DRIVEN SIMULATION
* Event-driven simulation is a widely-used mechanism in gate-level simulators. * An event is a change of a signal value that may trigger new changes. * There is a queue of events ordered by the time the event is going to happen. * Basic steps: + the output of a gate G changes at time t i. + the fanout of the gate is inspected; it consists of the inputs of the gates G k that are connected to the output of gate G. + if the outputs of the gates G k change, they are scheduled to change at time t i ) D k, where D k is the delay associated with the transition.

CAD TOOLS FOR VLSI SIMULATION Page 16

IMPLEMENTATION OF EVENT QUEUE

Naive implementation with a linked list: ev 1 t1 ev 2 t1 ev 1 t2 ev 3 t2

Disadvantages: * inefficient use of computation time (search for position where to insert new event);

CAD TOOLS FOR VLSI SIMULATION Page 17

IMPLEMENTATION OF EVENT QUEUE (Continued)

Better implementation: time wheel with n time slots. * only simultaneous events are in the same linked list, except those events that are scheduled more than n time units ahead. t ) (k ) 1)D t ) nD t t)D t ) kD Time wheel implementation: array of linked lists.

CAD TOOLS FOR VLSI SIMULATION Page 18

SWITCH-LEVEL SIMULATION
Basic points: * A circuit is modeled as a network of nodes interconnected by transistors. * Signals have two components <s,v>: + strength (s): associated with impedance. Often the set of values is discrete. + level (v): associated with voltage. Possible values are: 0, 1 and X. * There are two types of nodes: + storage nodes: they have a capacitance value. Often the set of values is discrete. + input nodes: they act as sources of fixed value and can supply unlimited current. * The transistors: + act as bidirectional switches; + have a strength value (signals passing through a transistor have their strength reduced to this value).

CAD TOOLS FOR VLSI SIMULATION Page 19

STRENGTH MODELS
BRYANTS MODEL OF STRENGTH VALUES There are w distinct strength values: 1, 2, ..., k, ..., w. s = w s is the strength of an input signal. k < s < w s is the strength of a transistor. 1 vs v k s is the strength of a storage node.

* * * *

CAD TOOLS FOR VLSI SIMULATION Page 20

STRENGTH MODEL EXAMPLES

V dd V dd n 0(5) A
(3)

V dd n 0(5)
(3) (3)

n 0(5)
(3)

f Out

n 1(2) A Out n 2(1) B

(3)

n 1(1) A n 2(1) B

Out
(3)

n 1(1) A n 2(1) B

(4)

(3)

n 3(1)
(4) (3)

(3)

n 3(5) V ss (a)

n 3(5) V ss (b)

n 4(5) V ss (c)

CAD TOOLS FOR VLSI SIMULATION Page 21

NODE EVALUATION
HAYES #-OPERATOR * It combines several <s,v>-pairs seen by a node to give one <s,v>-pair, the actual signal on the node. * The signals with maximum s-values determine the new s-value; the new v-value is X unless all maximum signals are 0 or 1.

CAD TOOLS FOR VLSI SIMULATION Page 22

SWITCH-LEVEL SIMULATION TECHNIQUES

Main principles: * partition the circuit into subcircuits that can be seen as unidirectional elements. The interaction between these subcircuits can be as in gate-level simulation. * apply special methods to compute the steady-state of the subcircuits modelled at the switch level (similar to unit-delay simulation).

CAD TOOLS FOR VLSI SIMULATION Page 23

CIRCUIT PARTITIONING EXAMPLE

V dd V dd

V ss V ss