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TC7106A
1
TC7107
TC7107A
6
30 –
V IN POL
– MINUS SIGN BACKPLANE
CKW 44-Pin PQFP Formed Leads 0°C to +70°C 21 DRIVE
ANALOG BP
32
CLW 44-Pin PLCC — 0°C to +70°C COMMON V+
1
R OSC 100pF
100kΩ
COMMON (PIN 32)
3 CONVERSIONS/SEC
200mV FULL SCALE
7
40-Pin Plastic DIP 40-Pin CERDIP
Figure 1. TC7106/A/7/A Typical Operating Circuit
ABSOLUTE MAXIMUM RATINGS* Analog Input Voltage (either input) (Note 1) ......... V+ to V–
Reference Input Voltage (either input) ................. V+ to V–
TC7106A Clock Input ....................................................... GND to V+
Supply Voltage (V+ to V–) ........................................... 15 V Power Dissipation (Note 2) (TA ≤ 70°C)
Analog Input Voltage (either input) (Note 1) ......... V+ to V– 40-Pin CerDIP Package ...................................2.29W
Reference Input Voltage (either input) ................. V+ to V– 40-Pin Plastic DIP ............................................. 1.23W
Clock Input ........................................................ Test to V+ 44-Pin PLCC .....................................................1.23W
Package Power Dissipation (Note 2) (TA ≤ 70°C) 44-Pin PQFP .................................................... 1.00W
CerDIP ..............................................................2.29W Operating Temperature
Plastic DIP ........................................................1.23W “C” Devices ............................................ 0°C to +70°C
PLCC ................................................................1.23W “I” Devices ........................................ – 25°C to +85°C
PQFP ................................................................1.00W Storage Temperature ............................ – 65°C to +150°C
Operating Temperature Lead Temperature (Soldering, 10 sec) ................. +300°C
“C” Devices ............................................ 0°C to +70°C
“I” Devices ........................................ – 25°C to +85°C *Static-sensitive device. Unused devices must be stored in conductive
Storage Temperature ............................ – 65°C to +150°C material. Protect devices from static discharge and static fields. Stresses
above those listed under Absolute Maximum Ratings may cause perma-
Lead Temperature (Soldering, 60 sec) ................... 300°C
nent damage to the device. These are stress ratings only and functional
TC7107A operation of the device at these or any other conditions above those
Supply Voltage indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
V+ ................................................................................................ +6 V may affect device reliability.
V– ............................................................................................... – 9 V
8
TELCOM SEMICONDUCTOR, INC. 3-185
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
PIN CONFIGURATIONS
V+ 1 40 OSC 1 OSC 1 1 40 V +
NORMAL PIN REVERSE PIN
D1 2 CONFIGURATION 39 OSC 2 OSC 2 2 CONFIGURATION 39 D1
C1 3 38 OSC 3 OSC 3 3 38 C1
B1 4 37 TEST TEST 4 37 B 1
+ +
1's A1 5 36 V REF V REF 5 36 A 1 1's
F1 – –
VREF F1
6 35 VREF 6 35
+ +
CREF
G1 7 34 CREF 7 34 G1
– –
CREF
E1 8 33 CREF 8 33 E 1
9 32 ANALOG ANALOG 9 32 D2
D2 COMMON
COMMON
+ +
V IN
C2 10 31 V IN 10 31 C2
B 2 11 TC7106ACPL 30 V –
IN V– IN 11 TC7106AIJL 30 B 2
10's TC7107AIPL TC7107AIJL 10's
A 2 12 29 CAZ CAZ 12 29 A 2
F2 13 28 VBUFF VBUFF 13 28 F2
E 2 14 27 V INT V INT 14 27 E 2
D3 15 26 V – V – 15 26 D3
B 3 16 25 G G 2 16 25 B 3
2
100's 100's
F3 17 24 C 3 C 3 17 24 F3
100's 100's
E 3 18 23 A 3 A 3 18 23 E 3
1000's AB 4 19 22 G 3 G 3 19 22 AB 4 1000's
POL 20 21 BP/GND BP/GND 20 21 POL
(MINUS SIGN) (7106A/7107A) (7106A/7107A) (MINUS SIGN)
REF LO
REF HI
REF HI
OSC1
OSC2
OSC3
CREF
CREF
IN LO
BUFF
TEST
COM
IN HI
INT
A/Z
NC
C1
D1
V+
A1
B1
V–
6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 35 34
F1 7 39 REF LO NC 1 33 NC
G1 8 38 CREF NC 2 32 G2
E1 9 37 CREF TEST 3 31 C3
D2 10 36 COMMON OSC3 4 30 A3
C2 11 35 IN HI NC 5 29 G3
F2 15 31 BUFF D1 9 25 E3
E2 16 30 INT C1 10 24 F3
D3 17 29 V– B1 11 23 B3
18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22
B3
F3
E3
AB4
POL
NC
BP/GND
G3
A3
C3
G2
A1
F1
G1
E1
D2
C2
B2
A2
F2
E2
D3
PIN DESCRIPTION
Pin No.
40-Pin PDIP
Pin No.
40-Pin PDIP
2
(Normal) (Reverse) Symbol Description
1 (40) V+ Positive supply voltage.
2 (39) D1 Activates the D section of the units display.
3 (38) C1 Activates the C section of the units display.
4 (37) B1 Activates the B section of the units display.
5
6
(36)
(35)
A1
F1
Activates the A section of the units display.
Activates the F section of the units display.
3
7 (34) G1 Activates the G section of the units display.
8 (33) E1 Activates the E section of the units display.
9 (32) D2 Activates the D section of the tens display.
10 (31) C2 Activates the C section of the tens display.
11 (30) B2 Activates the B section of the tens display.
12
13
(29)
(28)
A2
F2
Activates the A section of the tens display.
Activates the F section of the tens display. 4
14 (27) E2 Activates the E section of the tens display.
15 (26) D3 Activates the D section of the hundreds display.
16 (25) B3 Activates the B section of the hundreds display.
17 (24) F3 Activates the F section of the hundreds display.
18 (23) E3 Activates the E section of the hundreds display.
19
20
21
(22)
(21)
(20)
AB4
POL
BP
Activates both halves of the 1 in the thousands display.
Activates the negative polarity display.
LCD Backplane drive output (TC7106A).
5
GND Digital ground (TC7107A).
22 (19) G3 Activates the G section of the hundreds display.
23 (18) A3 Activates the A section of the hundreds display.
24 (17) C3 Activates the C section of the hundreds display.
25 (16) G2 Activates the G section of the tens display.
26
27
(15)
(14)
V–
VINT
Negative power supply voltage.
Integrator output. Connection point for integration capacitor. See
6
INTEGRATING CAPACITOR section for more details
28 (13) VBUFF Integration resistor connection. Use a 47kΩ resistor for a 200mV full-
scale range and a 470kΩ resistor for 2V full-scale range.
29 (12) CAZ The size of the auto-zero capacitor influences system noise. Use a
0.47µF capacitor for 200mV full scale, and a 0.047µF capacitor for
2V full scale. See Paragraph on AUTO-ZERO CAPACITOR for more
30 (11) V –IN
details.
The analog LOW input is connected to this pin. 7
31 (10) V +IN The analog HIGH input signal is connected to this pin.
32 (9) ANALOG This pin is primarily used to set the analog common-mode voltage
COMMON for battery operation or in systems where the input signal is
referenced to the power supply. It also acts as a reference voltage
source. See paragraph on ANALOG COMMON for more details.
33 (8) C –REF See pin 34.
8
TELCOM SEMICONDUCTOR, INC. 3-187
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
∫
FIXED VARIABLE
TSI SIGNAL
INTEGRATE
REFERENCE
INTEGRATE
1 VRTRI TIME TIME
RC 0 V IN(t)dt = RC
Figure 2A. Basic Dual Slope Converter
The dual slope converter accuracy is unrelated to the Signal Integrate Cycle
integrating resistor and capacitor values as long as they are
stable during a measurement cycle. An inherent benefit is
noise immunity. Noise spikes are integrated or averaged to
When the auto-zero loop is opened, the internal differ-
+
ential inputs connect to V IN –
and VIN. The differential input
signal is integrated for a fixed time period. The signal
2
zero during the integration periods. Integrating ADCs are integration period is 1000 counts. The externally set clock
immune to the large conversion errors that plague succes- frequency is divided by four before clocking the internal
sive approximation converters in high-noise environments. counters. The integration time period is:
Interfering signals with frequency components at multiples
of the averaging period will be attenuated. Integrating ADCs 4
TSI = x 1000
commonly operate with the signal integration period set to a fOSC
multiple of the 50/60 Hz power line period. (Figure 2B) where: 3
fOSC = External Clock Frequency
30
The differential input voltage must be within the device
NORMAL MODE REJECTION (dB)
–
VIN
The final phase is reference integrate or de-integrate.
is internally connected to analog common and V IN +
is
5
Figure 2B. Normal-Mode Rejection of Dual Slope Converter
connected across the previously charged reference capaci-
ANALOG SECTION tor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator
In addition to the basic signal integrate and deintegrate output to return to zero. The time required for the output to
cycles discussed, the circuit incorporates an auto-zero return to zero is proportional to the input signal and is
cycle. This cycle removes buffer amplifier, integrator, and
comparator offset voltage error terms from the conversion.
A true digital zero reading results without adjusting external
between 0 and 2000 counts. The digital reading displayed is:
1000 x
VIN 6
potentiometers. A complete conversion consists of three VREF
cycles: an auto-zero, signal-integrate and reference-inte-
grate cycle. DIGITAL SECTION (TC7106A)
The TC7106A (Figure 3) contains all the segment driv-
Auto-Zero Cycle
ers necessary to directly drive a 3 -1/2 digit liquid crystal
During the auto-zero cycle the differential input signal is
disconnected from the circuit by opening internal analog
gates. The internal nodes are shorted to analog common
display (LCD). An LCD backplane driver is included. The
backplane frequency is the external clock frequency divided
by 800. For three conversions/second the backplane fre-
7
(ground) to establish a zero-input condition. Additional ana- quency is 60Hz with a 5V nominal amplitude. When a
log gates close a feedback loop around the integrator and segment driver is in phase with the backplane signal the
comparator. This loop permits comparator offset voltage segment is “OFF.” An out of phase segment drive signal
error compensation. The voltage level established on CAZ causes the segment to be “ON” or visible. This AC drive
compensates for device offset voltages. The offset error configuration results in negligible DC voltage across each
referred to the input is less than 10µV.
The auto-zero cycle length is 1000 to 3000 counts.
LCD segment. This insures long LCD display life. The
polarity segment driver is “ON” for negative analog inputs. If
+
V IN –
and VIN are reversed, this indicator will reverse.
8
TELCOM SEMICONDUCTOR, INC. 3-189
TC7107A
TC7107
TC7106A
TC7106
3-190
0.5mA
SEGMENT
OUTPUT
LCD DISPLAY
2mA
CAZ CINT
CREF RINT
Figure 3. TC7106A Block Diagram
34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT
TO
7 SEGMENT 7 SEGMENT
DECODE
÷ 200
DECODE DECODE
– – DIGITAL
10 A/Z A/Z + SECTION
µA + + DATA LATCH
–
A/Z
+ 31
V IN COMPARATOR
DE DE THOUSANDS HUNDREDS TENS UNITS
INT (–) (+)
LOW
A/Z – TEMPCO TO SWITCH DRIVERS
VREF FROM COMPARATOR OUTPUT
+ 1
V+
ROSC
COSC
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A
When the TEST pin on the TC7106A is pulled to V+, all • Signal Integrate: 1000 Counts
segments are turned “ON.” The display reads –1888. During
this mode the LCD segments have a constant DC voltage
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE
(4000 Clock Pulses)
This time period is fixed. The integration period is: 2
FOR MORE THAN SEVERAL MINUTES! LCD displays
may be destroyed if operated with DC levels for extended
TSI = 4000 [ ]1
fOSC
periods.
The display font and the segment drive assignment are Where fOSC is the externally set clock frequency.
shown in Figure 4. • Reference Integrate: 0 to 2000 Counts
DISPLAY FONT
(0 to 8000 Clock Pulses)
The TC7106A/7107A are drop-in replacements for the 3
7106/7107 parts. External component value changes are
not required to benefit from the low drift internal reference.
1000's 100's 10's 1's
Clock Circuit
Three clocking methods may be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
4
Figure 4. Display Font and Segment Assignment
÷4 TO
In the TC7106A, an internal digital ground is generated COUNTER
from a 6 volt zener diode and a large P channel source
follower. This supply is made stiff to absorb the large
40 39 38
capacitive currents when the backplane voltage is switched.
0.5mA
SEGMENT
OUTPUT
LED DISPLAY
8mA
CAZ
Figure 5. TC7107A Block Diagram
CINT
CREF RINT
+ + – – + LCD SEGMENT DRIVERS
C REF VREF VREF C REF V BUFF V VINT
34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT 7 SEGMENT 7 SEGMENT
TO DECODE DECODE DECODE
– – DIGITAL
10 A/Z A/Z + SECTION
µA + + DATA LATCH
–
A/Z
+ 31
V IN COMPARATOR
DE DE THOUSANDS HUNDREDS TENS UNITS
INT (–) (+)
LOW
A/Z – TEMPCO TO SWITCH DRIVERS
VREF
INT 26 DIGITAL
DIGITAL GOUND GROUND
– 500Ω
V
40 39 38 37
OSC 1 OSC 2 OSC 3 TEST
ROSC
COSC
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A
Where:
ings/second) will reject both 50Hz and 60Hz.
8
TELCOM SEMICONDUCTOR, INC. 3-193
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
V+ CI
V+ INPUT
V+ BUFFER
+ + RI
+ V+ –
VREF 6.8V – VI
ZENER 6.8kΩ VIN +
–
VREF INTEGRATOR
TC7106A 20k Ω
TC7107A –
TI
TC7106A
IZ
+
VREF VCM
VI =
RI CI
[
V CM – VIN [
TC04 Where:
TC7107A 4000
– 1.2V T I = INTEGRATION TIME =
VREF f OSC
REF
C I = INTEGRATION CAPACITOR
COMMON R I = INTEGRATION RESISTOR
(a) (b)
SEGMENT
DRIVE LCD DISPLAY
7
VREF
500Ω resistor in the TC7106A. The TEST pin load should be
no more than 1mA . ANALOG 32
COMMON
If TEST is pulled to V+ all segments plus the minus sign
will be activated. Do not operate in this mode for more than SET VREF = 1/2 VFULL SCALE
several minutes with the TC7106A. With TEST = V+ the LCD
segments are impressed with a DC voltage which will
destroy the LCD.
The TEST pin will sink about 10mA when pulled to V+. Figure 11. Internal Voltage Reference Connection
8
TELCOM SEMICONDUCTOR, INC. 3-195
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
V– = –3.3V
+5 V
1
+ + 36
V VREF
– 35
VREF
LED
DRIVE 32 Figure 14. TC7107A Output Current vs Output Voltage
COM
TC7107A
+ 31
VIN
Reduced power dissipation is very easy to obtain.
VIN
Figure 15 shows two ways: either a 5.1 ohm, 1/4 watt resistor
– 30
VIN
or a 1 Amp diode placed in series with the display (but not in
21 series with the TC7107A). The resistor will reduce the
– GND
V
8
TC7107A output voltage, when all 24 segments are “ON,” to
26
+
2 point “C” of Figure 14. When segments turn off, the output
5 (–5 V)
10µF 4
TC7660
voltage will increase. The diode, on the other hand, will result
3 *3-1/2 DIGIT ADC in a relatively steady output voltage, around point “B.”
+ 10µF
In addition to limiting maximum power dissipation, the
resistor reduces the change in power dissipation as the
Figure 13. Negative Power Supply Generation with TC7660 display changes. This effect is caused by the fact that, as
3-196 TELCOM SEMICONDUCTOR, INC.
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
1
TC7107
TC7107A
fewer segments are “ON,” each “ON” output drops more APPLICATIONS INFORMATION
voltage and current. For the best case of six segments (a
“111” display) to worst case (a “1888” display) the resistor
will change about 230mW, while a circuit without the resistor Liquid Crystal Display Sources 2
will change about 470mW. Therefore, the resistor will re- Several LCD manufacturers supply standard LCD dis-
duce the effect of display dissipation on reference voltage plays to interface with the TC7106A 3-1/2 digit analog-to-
drift by about 50%. digital converter.
The change in LED brightness caused by the resistor is
almost unnoticeable as more segments turn off. If display
Manufacturer Address/Phone Part Numbers1
brightness remaining steady is very important to the de-
signer, a diode may be used instead of the resistor. Crystaloid
Electronics
5282 Hudson Dr.
Hudson, OH 44236
C5335, H5535,
T5135, SX440
3
Figure 15. Diode or Resistor Limits Package Power Dissipation 216/655-2429
AND 720 Palomar Ave. FE 0201,0701
APPLICATIONS INFORMATION Sunnyvale, CA 94086 FE 0203, 2201
408/523-8200 FE 0501
+5V IN –5V Epson 3415 Kashikawa St. LD-B709BZ
+ –
Torrance, CA 90505 LD-H7992AZ
24kΩ
1 MΩ
TP3
150Ω
Hamlin, Inc.
213/534-0360
612 E. Lake St. 3902, 3933, 3903
4
1kΩ
0.47
Lake Mills, WI 53551
µF 0.22 414/648-2361
100 0.01
pF µF µF Note: 1. Contact LCD manufacturer for full product listing/specifications.
TP5
TP2 0.1 DISPLAY
100 µF 47
kΩ TP1 kΩ Light Emitting Diode Display Sources
Several LED manufacturers supply seven segment
5
40 30 TP 21
4
TC7107A
digits with and without decimal point annunciators for the
TC7107A.
1 10 20
8
TELCOM SEMICONDUCTOR, INC. 3-197
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
V+ +
V IN
LCD DISPLAY
V+ BP RUNKNOWN TC7106A
–
V IN
DECIMAL TO LCD ANALOG
POINT DECIMAL COMMON
TC7106A SELECT POINTS
+ 9V
VIN
IN4148
200mV
10kΩ
1µF
+
–
1 14
1
V+ V–
26
27
2
9MΩ 24kΩ
2V 0.02 2 13
1MΩ
µF TC7106A 29
3 12
900kΩ 1MΩ 36
20 V 1kΩ V+
REF
4 AD636 11
47kΩ – 28
35
90kΩ 1W 6.8µF 5 10 V–
REF
200 V 10% +
32
10kΩ
20kW
6
7
9
8
1MΩ 10%
0.01
31
ANALOG
COMMON
V+
IN
40 3
2.2µF µF
10% 30 38
COM V–
IN
C1 = 3–10pF VARIABLE, 26 39
C2 = 132pF VARIABLE V–
SEG BP
DRIVE
4
LCD DISPLAY
+ 9V + 9V
6
R2 + R3 VREF
VREF PTC
50kΩ 20kΩ
– –
VREF VREF
COMMON COMMON
Figure 19. Temperature Sensor Figure 20. Positive Temperature Coefficient Resistor
Temperature Sensor
7
8
TELCOM SEMICONDUCTOR, INC. 3-199
3-1/2 DIGIT A/D CONVERTERS
TC7106
TC7106A
TC7107
TC7107A
9V
2 1
CONSTANT 5 V
V+ V+
V+REF
5 2 – VFS = 2.00V
ADJ NC 8
1
V–
IN
3 3 +
TEMP 4 VOUT =
1.86V @ V+
IN
TEMPERATURE 25°C
50kΩ
DEPENDENT 1.3k R1 COMMON
OUTPUT
GND V–
4 26
TO PIN 1 TO PIN 1
SET VREF = 100mV SET VREF = 100mV
40 40
100kΩ 100kΩ
39 39
38 38
37 100pF 37 100pF
36 36
35 35 +5V
34 1 kΩ 22kΩ 34 1kΩ 22kΩ
0.1µF 0.1µF
33 1MΩ + 33 1MΩ +
32 32
31 0.01µF IN 31 0.01µF IN
TC7106A TC7107A 30
30
0.47µF + – 0.47µF –
29 29
47kΩ 47kΩ
28 9V 28
27 – 27
0.22µF 0.22µF
26 26 –5V
25 25
24 24
TO DISPLAY 23 TO DISPLAY
23
22 22
21 TO BACKPLANE 21
Figure 22. TC7106A Using the Internal Reference: 200mV Full- Figure 23. TC7107A Internal Reference (200mV Full-Scale,
Scale, 3 Readings-per-second (RPS). –
3RPS, VIN Tied to GND for Single Ended Inputs).
V+
1 40 TO PIN 1
SET VREF = 1V
2
40
TO 100kΩ
LOGIC 39
VCC TO 38
LOGIC 37 100pF
GND 24kΩ
36
35 V+
TC7106A 34 25k Ω
0.1µF
TC7106A
33
32
31 0.01µF
1MΩ +
IN
3
V– 30
O/R TC7107A 0.047µF –
29
470k Ω
28
27 0.22µF
U/R 26 V–
20 21 25
24
CD4023 TO DISPLAY
23
4
OR 74C10
CD4077 O/R = OVERRANGE 22
U/R = UNDERRANGE 21
Figure 24. Circuit for Developing Underrange and Overrange Figure 25. TC7106A/TC7107A: Recommended Component
Signals from TC7106A Outputs. Values for 2.00V Full-Scale
TO PIN 1 TO PIN 1 5
40 40
100k Ω 100kΩ
39 SET VREF = 100mV 39 SET VREF = 100mV
38 38
37 100pF 37 100pF
36 10k Ω 10kΩ 36 10k Ω 10kΩ
+ +
35 V 35 V
34 1kΩ TC04 34 1 kΩ TC04
0.1µF 0.1µF
33
32
31
30
1.2V
0.01µF 1M Ω
+
IN
TC7107A
33
32
31
30
0.01µF
1.2V
1MΩ
+
IN
6
TC7107A 0.47µF 0.47µF –
29 – 29
47kΩ 47kΩ
28 28
27 27
0.22µF – 0.22µF
26 V 26
25 25
24 24
TO DISPLAY TO DISPLAY
23 23
22
21
22
21
7
Figure 26. TC7107A With a 1.2V External Band-Gap Reference. Figure 27. TC7107A Operated from Single +5V Supply. An
–
(VIN Tied to Common.) External Reference Must Be Used in This Application.
8
TELCOM SEMICONDUCTOR, INC. 3-201
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