Ease VHDL Tutorial

Ease VHDL Tutorial

HDL Works BV Maxwellstraat 19 P.O. Box 620 6710 BP Ede The Netherlands Phone: +31 (318) 642 022 Fax: +31 (318) 636 482 Customer support: License requests: Web site: support@hdlworks.com license@hdlworks.com www.hdlworks.com

Even though HDL Works BV has tested the software and reviewed the documentation, HDL Works BV makes no warranty or representation, either express or implied, with respect to this software and documentation, its quality, performance, merchantability, or fitness for a particular purpose. No parts of this document may be copied or reproduced in any form or by any means without the prior written consent of HDL Works BV. The information in this document is subject to change without notice and should not be construed as a commitment by HDL Works BV. HDL Works BV assumes no responsibility for any errors that may appear in this document. HDL Works BV makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. The software described in this document is copyrighted by HDL Works BV, Ede, the Netherlands. The software described in this document is furnished under a license and may be used or copied only in accordance with the terms of a software license agreement. HDL Works BV acknowledges trademarks or registered trademarks of other organizations for their respective products and services. Software version: Ease 7.4. Copyright 2011 HDL Works BV, Ede, the Netherlands. All rights reserved.

Contents

Table of Contents
1 Introduction 2 Starting the Application 3 Setting Up the Project 5 6 8

................................................................................................................................... 8 3.1 Setting HDL Mode 3.2 Create a................................................................................................................................... 9 New Project 3.3 Setting ................................................................................................................................... 10 Project Options 3.4 Setting ................................................................................................................................... 11 Project Packages

4 Adding a Component 5 Adding Ports 6 Navigating Through the Project

14 17 20

................................................................................................................................... 20 6.1 Using the Browser Window ................................................................................................................................... 20 6.2 Using the Editor Window

7 Setting Up the State Diagram 8 Adding Conditions to Transitions 9 Adding the Reset Transition 10 Adding the Actions 11 Setting the State Diagram Properties 12 Design Considerations

21 24 28 30 33 35

................................................................................................................................... 35 12.1 Processes versus Components ................................................................................................................................... 36 12.2 Diagrams versus VHDL Files

13 Adding the Remaining Block Diagram Objects

37

................................................................................................................................... 38 13.1 A Component, Process, Generic and Port ................................................................................................................................... 39 13.2 Connect-by-Name Labels ................................................................................................................................... 40 13.3 Copying Ports ................................................................................................................................... 41 13.4 Automatically Connect Ports

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Contents

14 Connecting the Block Diagram Objects

43

................................................................................................................................... 43 14.1 About Process Ports 14.2 Adding ................................................................................................................................... 44 More Ports ................................................................................................................................... 45 14.3 Drawing Nets ................................................................................................................................... 46 14.4 Completing the Diagram

15 Editing the Table Diagram 16 Writing a VHDL File Process 17 Creating the Toplevel 18 Generating VHDL Output 19 Configurations 20 Import VHDL

50 52 54 56 59 65

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Introduction

Introduction
This tutorial presents a demonstration of the design practice using Ease, the Graphical HDL Entry Tool by HDL Works BV. Using the design of a simple pump controller as an example, you will create a state machine, truth table, design block diagrams, elaborate architectures, and define a design hierarchy. After verifying the design for errors and inconsistencies, you will be able to generate VHDL output specifying the pump controller. Please keep in mind that we use this pump controller design only as a vehicle for our tutorial; in "real life" you might decide to solve things differently. We will give a short, informal specification of a pump controller. This controller will be the subject of our design example. The pump controller must maintain a certain level in a fluid tank. The level can rise due to an external source. In that case the controller must start the pump to decrease the fluid level until the reference level is attained again. The reference level is pre-loaded in a register of the controller. The controller has inputs level, load, reset and clk. It has one output pump_on. The input level is used for entering both the preloaded reference value (when the input signal load will be "high"), and the current fluid level (load is "low"). The width of the vector level is specified by the generic n "n downto 0". The output signal pump_on will put the pump to work. A synchronous reset signal reset and the clock signal clk complete the description of the entity declaration pump. We will use a state machine to actually control the pump and a truth table and a process statement to supply control signals for this state machine. If you follow the instructions as mentioned in this tutorial, you will familiarize yourself with the possibilities of Ease and its user interface. All user actions in this tutorial are preceded by the symbol. Working through this tutorial may take you about three hours. Take your time. If you have any question please phone us or send us an email message. We will be glad to help you!

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Starting the Application

Starting the Application

Start Ease and select Create a new (untitled) project in the Welcome to Ease dialog. Now the Main Window will appear:

Main Window

The following items are shown in the Main Window: the Title Bar shows the name of the program: Ease, and the name of the current project. the Menu Bar lists the available main menus. the Button Bars contain easy to use buttons. They are described in detail in the Ease Users Manual. the Browser Window lists the contents of the project in the several Views. the Editor Window is the window for designing block, state or table diagrams. The Editor Window displays an empty work sheet of a block diagram. A large rectangle represents the border of the work sheet. It is recommended not to draw objects outside this border. Some space in the lower right corner of the work sheet is intended for the identification of this sheet. the Status Bar is part of the Editor Window. It displays the hierarchical path of the currently active diagram, the HDL language in which you are working, and the coordinates of the mouse pointer. the Diagram Button Bar is part of the Editor Window. The contents of this bar depends on the diagram type opened in the Editor Window.

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Starting the Application

the Editor Window Message Bar is part of the Editor Window. It shows verification information (if applicable) and information on selected objects. the Console Window displays messages and results. the Message Bar displays information on menu commands and buttons. Each window contains its own title bar, menu bar and button bars. A new project in Ease always starts with a block diagram called "Toplevel", as indicated in the status bar of the Editor Window. Block diagrams are representations of architectures in VHDL, and the Toplevel architecture supplies t he context (i.e. the instantiating environment) for the entity that represents your system. Another level can always be introduced above the current Toplevel, giving the current Toplevel an entity name of its own. This is designing in a bottom up manner. It is common practice to do top down design, defining objects at a certain level and then descending into these objects to define their contents. In this tutorial we will combine the two design strategies.

Selecting Objects
In the Editor Window an object is selected by clicking on it. There are two ways to select one or more objects in the work sheet of the Editor Window: either click on a single object; this object will be selected. By holding down the CTRL key and clicking more objects, these can be added to the selection, or draw a rectangle by dragging from one position in the work sheet to another and then releasing the button; all objects entirely enclosed by the rectangle will be selected. Those objects not entirely enclosed by the rectangle will not be selected (e.g., nets consisting of several wires, where points of the net remain outside the rectangle). Besides selecting a net by drawing a rectangle around it, a net can be selected by holding down the SHIFT key when clicking a wire of the net. A net can be added to the selection by holding down the SHIFT and CTRL keys simultaneously, while clicking the net. The message in the message bar of the Editor Window will inform you about selected objects.

Canceling Actions
You can cancel the current action that needs user input at all times using the ESC key, including the actions move and copy.

Deleting Objects
You can delete one or more objects in the Editor Window by selecting the object(s) as explained above. After the selection press the DELETE key. You can also select an object and select Delete from its shortcut menu.

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Setting Up the Project

Setting Up the Project

Before we start to implement our design we will first set up our project in Ease.

3.1

Setting HDL Mode

Before we can start designing, we have to be sure that we will develop our design in the correct HDL mode. In this tutorial, we use the VHDL mode. First we will set the default language for new projects. Select Options >> User Options, and the HDL page from the dialog that appears. Set the option Default startup language to "VHDL".

Set default startup language to VHDL

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Setting Up the Project

3.2

Create a New Project

We will create a new Ease project using the settings made in the previous section. Create the project by selecting File >> New. Check that the settings have been used by selecting the Options >> Project properties menu item. The Project Properties dialog shown below will appear. On the HDL page the option Default language for new entities/modules is set to "VHDL".

Project Properties dialog

Before starting to fill the project, we will save it. Click the Save button (or select the File >> Save command). The Save As dialog appears.

Now go to the directory where you want to store your project, and enter "my_pump" in the File name field. Then click Save. The new project is now saved as my_pump.ews, and this name is shown in the Ease title bar. You can always save the project by selecting the Save button.

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Setting Up the Project

3.3

Setting Project Options

The signals defined in this tutorial will all be of type 'std_logic' and 'std_logic_vector'. Ease offers the possibility to add a default signal and vector type for ports and signals. By using this you do not need to specify the type of a signal for each port or signal (net). Right-click the project node in the Browser Window and select Properties from the project shortcut menu as shown below.

Select properties

The Project Properties dialog appears. Go to the VHDL page of the Project Properties dialog. Make sure that the default Signal type is set to "std_logic" and the default Vector type to "std_logic_vector" as shown below.

Default VHDL signal/vector type

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Setting Up the Project

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Click OK to close the dialog. You will see the default signal name appear in dialog entries as <std_logic> and <std_logic_vector> to denote the project default type. These defaults types changed globally.

3.4

Setting Project Packages

The signal types std_logic and std_logic_vector have been defined in the standard package "std_logic_1164". As this is a common used package this package is added to the project by default. The next part of this section shows how you can add standard packages to your project by including the standard package "numeric_std". This package is not really needed in this project. In the Browser Window, right-click the project node and select New >> Standard Package from the project shortcut menu. The Standard Packages dialog appears. Select the ieee.numeric_std check box as shown below.

Select the "ieee.numeric_std" package

Click OK to close the dialog. In the Browser Window, the package "numeric_std" has been added to the project, but at this moment the package is not in the package use list. In the Browser Window, select New >> Package Use from the project shortcut menu. The Package uses for project my_pump dialog appears. Select ieee.numeric_std in the Package list and click button Insert.

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Setting Up the Project

Click the button to change the Package use list order. Usually the use statement of the std_logic_1164 package is declared before other packages.

Package Use dialog

Click OK to close the dialog. The package has been added to the package use list. Now, the Database View tab page of the Browser Window has the contents as shown below.

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Setting Up the Project

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Browser Window after adding package

Now you are all set to start your first design.

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Adding a Component

Adding a Component
We will start designing the state machine that controls the pump. New entities are created by adding a new component to the current block diagram. Click the Add Component of new Entity Component of new Entity" in the tooltip. button. Note the button description: "Add

Now point to a position in the sheet where you want one corner of the component boundary (see figure Component u0 in the block diagram below). Click and drag to the position of the opposite corner, then release the button. The dragging step defines the entity block size so that entities with lots of pins can be bigger than entities with a few pins. The dialog Create new Entity appears. In this dialog you must enter an entity name and you can change the component name, meaning the instantiation label in VHDL descriptions, architecture name and architecture implementation. Enter the name "control" in the Entity name field. This entity is to contain a state diagram architecture. Therefore the implementation must be changed from "Block Diagram" into "State Diagram" as shown below:

Create New Entity dialog

Click OK to close the dialog. The component appears on your screen, as in the figure below. The ports will be added later on.

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Adding a Component

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Component u0 in the block diagram

The component instantiation label u0:control:fsm(S) appears at the upper side of the component. This label consists of the component identifier (u0), the entity name (control), and the architecture name ( fsm) with an indication of the type of the architecture (S for state diagram). If you have added a too small entity you can resize it: Leave the Add Component of new Entity mode by right-clicking somewhere in the empty part of the worksheet, or by pressing the ESC key. Select the component you want to resize. The entity becomes yellow and has black squares on each corner as shown below. Point to the lower-right square, the mouse pointer changes into a small black two-directional arrow as shown below, left part. Click and drag the corner to the desired position as shown below, middle part. Release the button as shown below, right part.

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Adding a Component

Resize the component in three steps

You have now finished the creation of your first component. However, the component is still bare and has no interfaces. Our next step will be to add ports to the component.

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Adding Ports

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Adding Ports
The control component is a VHDL entity with four inputs (load, high, reset, and clk) and two outputs (wr and pump_on). We will first place the reset port. It is common design practice to place input ports at the left side of components and output ports at the right side. Clock and reset ports are often placed at the upper or lower side. After adding the ports the control component will look like this:

Ports of component u0

Click the Add Input Port shown below:

button and click a position on the lower side of the component as

Add port to entity

The Properties for new port dialog appears. In this dialog you can enter a name for this port, change its mode, set its type and enter a default value and comment. Substitute the presented default port name "p0" with the name "reset", and click OK.

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Adding Ports

Properties for New Port dialog

When you have added the port, it should be placed on the boundary of the component and its name should be placed inside the component. The figure below shows that the ports reset and load are input ports of the entity control. The ports reset_wrong and load_wrong are no input ports of the entity.

Port examples

You can delete wrong placed ports by selecting them and pressing the DELETE key. Select another position at the lower side of the component and add port clk. Select positions on the left side of the component and add the ports load and high. Note that a shortcut key has been assigned to most diagram buttons. For example to add an input port you can click the Add Input Port button, but you can also press the shortcut key I. Refer for a list of available shortcut keys to the Users Manual. These four ports are all input ports for the component, depicted by the port arrow pointing into the component.

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Adding Ports

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Now click the Add Output Port side of the component.

button. Add the output ports wr and pump_on at the right

You see that for output ports the port arrow points out of the instance (the port name is still inside the instance). While adding ports, the port symbol is attached to the mouse pointer, to indicate we are in a port adding mode. To switch off this mode right-click in the diagram, and see the mouse pointer change. The interface of the entity control is now defined. Point into the rectangle occupied by u0 and see how component information is shown in a tooltip box:

Tooltip information

Shown here are: the component name (u0), the entity name (control), the architecture name (fsm), with an indication of the type of the architecture (S for state diagram). The entity is not externally defined (shown by External = No), and it is contained in design library design.

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Navigating Through the Project

Navigating Through the Project

We have introduced the entity control (by adding a new component) and defined its interface (by adding ports). The next step is to define the architecture of this entity. To do this we move down one level in the design hierarchy and descend into the component. There are two ways to navigate through the project: you can use the Browser Window, or double-click in the diagram. We start by explaining the navigating using the Browser Window.

6.1

Using the Browser Window

All entities and their architectures are shown in the Database View tab page of the Browser Window. The contents of the architectures will be opened when you double-click on them in the Browser Window. If you double-click on a block diagram, state diagram, or table diagram body, its contents is shown in the Editor Window. If you double-click on an HDL text body, its contents is shown in the built-in editor, Scriptum. The current diagram icon in the Database View of the Browser Window marks the architecture that has been opened in the Editor Window.

6.2

Using the Editor Window

Another way of navigating through the hierarchy is by double-clicking in the diagrams in the Ease Editor Window. you go down one level by double-clicking inside the component you want to enter. you go up one level by double-clicking somewhere else in a block, state, or table diagram (not on a diagram object) or you can use the navigation button Go to parent diagram . Double-click in component u0, the instantiation of the entity control, and the empty state diagram of its architecture fsm appears. The screen should now display an empty state diagram. Note that the state diagram button bar now replaces the block diagram button bar. Note that the Editor Window title bar shows the name of the current contents: "State Diagram: design.control.fsm".

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Setting Up the State Diagram

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Setting Up the State Diagram

The state diagram editor of Ease enables you to enter state machines graphically. A state machine consists of states and transitions between these states. Conditions on the transitions control the internal state machine behavior (e.g. which state will be the next active state). Actions on the states and on the transitions control the external state machine behavior (e.g. what values need to be assigned to the outputs of the state machine). At the end of this section we will have a state diagram like this:

States and transitions of control

We need a relatively simple state machine for the entity control. When signal load is '1', the signal wr must become '1' for one clock cycle to store the reference value in the preload register. When the signal high is '1' (indicating that the measured level is higher than the preloaded value), the signal pump_on must be '1' to turn on the pump. This signal must remain '1' until the measured level drops below the preloaded level (when high resets to '0'). The synchronous reset signal reset causes the state machine to return to its initial state. Looking at this description we can identify the need for three states. When adding a state, it will be positioned with the left-top corner at the pointer position. Click the Add State button and click in the diagram where you want to place the state Start.

Replace the default state name "S1" by "Start" in the State Properties dialog that appears, and click OK. Also add states Pumping and Preload and position them as shown in the figure above. The states will by default be numbered in drawing order; the numbering can be changed, though. Now we will add transitions between the states. You may use both straight and curved transitions. A corner can be added to a straight transition, by clicking while drawing it.

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Setting Up the State Diagram

Click the Add Straight Transition button. Click inside state Start near the right border. Drag to the left side of state Pumping, and click again. The figure below shows the added transition:

The first transition between state Start and Pumping

The transition starts in state Start when this point has a number with only a blue circle as shown above. The transition is not connected to state Start when there is also a square around the circle as the reset transition in the figure Reset transition in Adding the Reset Transition. The transition ends in the state Pumping when this point has only a small blue dot. A blue dot with a cross is not connected to a state. You can always delete a transition by selecting it and pressing the DELETE key. Let us add another transition now, but this time a curved one. Click the Add Curved Transition button. Click near the lower side inside state Start and drag downwards and to the right, to a position inside state Preload, and click again:

The transition between state Start and Preload

Next, use again the Add Straight Transition and add a transition between state Pumping and state Preload as shown below:

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Setting Up the State Diagram

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The transition between state Pumping and Preload

Add a transition between state Preload and state Start as shown below:

The transition between state Preload and Start

Finally add a transition between state Pumping and state Start. Click in the state Pumping, drag upwards and click again. Now drag to the left and click somewhere above state Start. Finally drag downwards and click in the state Start:

The last transition between state Pumping and Start

Now you have added all transitions to the state diagram. You can move each arrow along its transition if you want to adjust the position. Leave the Add Transition mode by right-clicking somewhere in the diagram. The state diagram should now look like the first figure States and transitions of control in this section .

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Adding Conditions to Transitions

Adding Conditions to Transitions

The next step in the state diagram design is to add conditions to the transitions. So far, no conditions were attached; the default is used, evaluating to "always true". Right-click anywhere on the transition from state Start to state Pumping. You can do this by right-clicking on the connecting line, or the arrow symbol. Select Properties from the transition shortcut menu. The Transition Properties dialog appears:

Transition Properties dialog

A condition in Ease consists of three items. Most important is the VHDL code, containing a Boolean expression. The second item of a condition is its label, which serves as an identifier of the condition. The third item is a toggle to indicate whether the actual VHDL code or the label of the condition should be shown in the diagram. The condition label allows you to use a condition more than once. Defining a condition label is optional. Conditions without a label can only be displayed directly (i.e. showing the VHDL code) and can not be referenced in case you want to use the condition more than once. When you copy an unlabeled condition the VHDL code is actually copied, such that this text can be changed independently of the original text. When you copy a condition with a label the condition is not copied, but the reference to the condition is

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Adding Conditions to Transitions

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copied, such that when you change the VHDL code, all uses of this condition refer to the new VHDL code. We will enter conditions to the state diagram as shown in this figure:

State diagram with conditions

Type the VHDL code "high = '1'" in the HDL code field as shown below:

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Adding Conditions to Transitions

Adding "high = '1'" to the HDL code field

Click the New button, enter the condition label name "High" in the Enter Label name field of the Question dialog, and click OK twice. The label High appears near the arrow symbol of the transition in the state diagram as shown below:

Added condition label 'High' to the transition

Note: the Interface area of the dialog shows all entity port names with their direction and type. Doubleclicking in this area inserts the name in the HDL Code area of this dialog. Next, edit the transition from state Start to state Preload: enter the VHDL code "load = '1'", click New, enter the condition label name "Loading", and click OK twice:

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Adding Conditions to Transitions

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Added condition label 'Loading' to the transition

Edit the transition from state Pumping to state Start; enter the VHDL code "high = '0'", click New, enter the condition label name "Done", and click OK twice:

Added condition label 'Done' to the transition

Finally, edit the transition from state Pumping to state Preload: click on the label name "Loading" in the Labels list and click OK:

Added condition label 'Loading' to the transition

The condition Loading is now being used by two transitions. Note that the transition between Preload and Start uses the default condition: always true, because storing the preload value takes only one clock cycle.

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Adding the Reset Transition

Adding the Reset Transition

Finally, the transition for the synchronous reset needs to be added. We will use a global transition for this transition to make sure that the state Start is activated when the reset condition is true, regardless of the current state. A global transition is an efficient means for that, instead of having to draw transitions from every other state to Start.

Reset transition

Click the Add Straight Transition

button.

Click at a position in the work sheet to the left of state Start, drag to the right, into state Start and click again. Now leave the Add Transition mode by right-clicking. Now edit this transition. Enter the VHDL code "reset = '1'" and click OK right away. We will not attach a label to the condition, as we are sure that the condition will be used only once and the condition text is not very long. Notice that priorities change when a synchronous transition is added. The Start state now has two exiting transitions. Of these the global reset transition has the highest priority (0). The priority of the transitions labeled High and Loading have been incremented (from 0 and 1 to 1 and 2). We have now defined all transitions with their conditions in the state diagram. An overview of all conditions can be displayed by selecting the Diagram >> List Conditions command from the Editor Window menu. The following list is shown:

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List of conditions

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Adding the Actions

10

Adding the Actions

The next step is to add the actions to the state machine. An action, like a condition, consists of three items: the VHDL code containing sequential statements, its label (which serves as an identifier of the action), and the toggle to indicate whether the actual VHDL code or the label of the action should be shown in the diagram. Action code generally describes assignments to outputs. An action can be added to a transition or to a state. In case all assignments to a specific output are done in (one or more) actions that are all associated only to states, we traditionally speak of a Moore output. On the other hand, if these actions are only associated to transitions, we speak of a Mealy output. Ease allows to have both Moore and Mealy outputs in the same state machine. In our design example however, we only have Moore outputs. We will add actions to the state diagram as shown in this figure:

Complete state diagram

Click the Add Action button and add an action to the state Start, by clicking in the state Start at the position where you want to place the state action (see figure Added action label Nop' below). The Action Properties dialog appears. Enter the following VHDL code in the HDL code field as shown in the figure below: wr <= '0'; pump_on <= '0';

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Adding the Actions

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Adding the action code to the HDL code field

Click the New button, enter the action label name "Nop", and click OK. Click OK again to close the dialog. An action symbol labeled Nop appears in the state Start:

Added action label 'Nop'

Likewise, add the action labeled Pump to the state Pumping with this VHDL code: wr <= '0'; pump_on <= '1';

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Adding the Actions

Added action label 'Pump'

Next, add the action labeled Load to the state Preload with this VHDL code: wr <= '1'; pump_on <= '0';

Added action label 'Load'

All actions have been added now. Leave the Add Action mode by right-clicking somewhere in the diagram.

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11

Setting the State Diagram Properties

The last step in the design of the state machine is to set the state diagram properties. Open the State Diagram Properties dialog by selecting Diagram >> FSM Properties, or by right-clicking somewhere in the diagram and selecting FSM Properties from the shortcut menu. Go to the Clock Behaviour page of the State Diagram Properties dialog. Select clk from the Clock Edge Signal list as shown below.

Set the clock signal

Select Rising edge. The clock signal must be known to generate VHDL code for the state machine. We do not modify the other state diagram properties and keep the default settings. Click OK to close the State Diagram Properties dialog. The settings are shown in the state diagram:

State diagram properties

You can check the state diagram contents by verifying it.

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Setting the State Diagram Properties

Click the Verify the current diagram

button.

The Verification Results tab page of the Console Window should report: "0 errors, 0 warnings, 0 notes." If you have errors you can double-click on the error message in the Console Window. The object mentioned in the message is selected and you can fix the error. Move back to the Toplevel of the project by double-clicking in the white space of the state diagram.

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12

Design Considerations
Before we continue our design we have to consider a few questions.

12.1

Processes versus Components

The next step in this tutorial is to fill in the current block diagram. From our design specification (see Introduction) we conclude that we need two more design parts: one for the storage of the reference level in the preload register and one for the comparison of the current level with the preloaded level. The question is: should we use a process or a component instantiation? A process is a group of sequential statements representing the behavior of some portion of the design. A process is inseparable from its environment: its enclosing architecture. It can not be treated (e.g., simulated) separately from the architecture, nor can it be used in different places. A component, however, is an indication of the usage (the instantiation) of another design entity in the current architecture. This other design entity can be treated (e.g., designed, debugged, simulated, or synthesized) separately from the current entity. For that purpose the component statement declares how the other entity can be used in the current architecture. Two other advantages of using an entity are: that more than one architecture can be designed for the entity, allowing you to elaborate a design part in various ways; and secondly, that such an architecture could itself again instantiate components, thus allowing a hierarchical decomposition (this would be the case for block diagram architectures in Ease). The choice between a process or a component (instantiation of an entity) must therefore be based on the following question: Is the intended design part large or should it be a separate design unit for design, debugging, simulation, synthesis, or multiple usage purposes? If so, use a component (which is an instantiation of an entity). If not, use a process. It generally means a more compact VHDL description: better to survey (hence better to understand, and better to maintain) and a lesser load (in terms of memory and run-time usage) for the simulation and synthesis tools. We recommend that you consider the use of processes wherever possible.

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Design Considerations

12.2

Diagrams versus VHDL Files

A second question is this: Should we use a diagram or a VHDL file to determine the contents of the design part? Diagrams are easier to comprehend. One uses a block diagram for the hierarchical decomposition of a large design part, a state diagram to define the behavior of a state machine or a table diagram to define the output signals as a function of input conditions or expressions. Drawing block diagrams is the best way to capture structure. Using functional blocks to create hierarchy improves the ability to survey your project. And the easiest way to define interconnections between these functional blocks is to draw them. All tedious details about naming conventions and type and size compatibilities are left to the graphical design tool. The same holds for state diagrams. The relationships between the different states are best expressed graphically in a diagram containing states and transitions. You can immediately see all the states and how they are reached, more easily than you can by reading VHDL code. A table diagram shows the output signals as a function of the input signals to give a quick overview concerning the relation between the input and output signals. Sometimes, however, diagrams are not the adequate means to design. VHDL offers a power of expression that can not possibly be represented graphically. It would be a severe limitation when these constructs were not available to the users of Ease. And sometimes you need to describe a very small design part in just a few lines of VHDL code where a diagram may not be worth the effort. For these reasons VHDL files can be associated with architectures and processes, in addition to the block, state and table diagram architectures and state and table diagram processes. Such a VHDL code file is called an Architecture or Process Body File in Ease. They are easily accessed through Ease by going down one level into the proper component or process. We decide (mainly for illustrative purposes) that we will use an entity with a table diagram architecture for the preload storage design part, and a VHDL file process for the comparator design part.

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13

Adding the Remaining Block Diagram Objects

We will now add the remaining objects to the Toplevel block diagram: a component for the preload storage design part and a process for the comparator design part. The figure below shows an example of the resulting diagram after the design actions as described in this paragraph have taken place:

(Incomplete) block diagram

The interface objects as described in the design specification will be added to this block diagram: the diagram generic n (controlling the bus width of the input vector level) and the diagram ports level, load, clk, reset, and pump_on. Finally, the interconnections between these ports and the ports on the two components and the process will be defined. We will add ports, nets, and connect-by-name labels to the block diagram in a manner that shows the capabilities of Ease, but that might not look orderly and straightforward to novice Ease users.

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13.1

A Component, Process, Generic and Port

First, we will design the preload storage part. Click the Add Component of New Entity button. Now select the area where you want the component u1 to appear. Accept the component label "u1", enter "preload" for the entity name and change the implementation into "Table Diagram". End by clicking OK. Next, click the Add Process/Concurrent Statement process label "pr0" with "compare" and click OK. button. Place a process, replace the

Then click the Add Generic button and place a diagram generic in the sheet above component u1. Add "n" for the name of the generic. Set its Type to "natural". Set the default value of the generic to 5 by typing "5" in the field Def. value. Click OK to close the Generic Properties dialog. Note: you can change the Type of a generic or port by typing it in the Type field or by selecting it from the list, opened by clicking on the arrow behind the Type field. Now click the Add Input Port button. Place a diagram port in the sheet to the left of component u1. Enter the port name "level". Set its Type to "<std_logic_vector>" (to use the default vector type). Set Left range to "n" and Right range to "0". Click OK to close the Properties for new port dialog. The diagram should now look like:

The diagram after adding the diagram port 'level'

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13.2

Connect-by-Name Labels
We already defined component ports on component u0. We need some of these same ports as diagram ports, so copying them will save us having to specify their modes, and typing their names anew. However, more future work can be saved if we consider their interconnections now. There are two ways to establish connections between ports in Ease: through nets and through connect-by-name labels. Nets give an explicit view of the relationships between connected points. However, having many nets in a diagram may at times result in a confusing picture. Connect-by-name labels provide a powerful method for connecting ports that all use the same signal, such as clock and reset signals. The symbol used for connect-by-name labels is a tag. We will use both nets and tags in our block diagram. A handy feature of tags is that when you copy a port with such a tag, the tag is copied with the port too. So before we copy ports from component u0 we first attach tags to some of these ports. Click the Add Connect-by-Name Label button and click the port clk of component u0.

A tag appears, indicating that this port will be connected to all ports in the block diagram that have the same label name. Also place a tag on the port reset. Exit the Add Connect-by-Name Label mode by right-clicking. The diagram should now look like:

The diagram after adding the connect-by-name tags

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13.3

Copying Ports
Now we will copy the ports clk and reset from component u0. Select both ports like this: select port clk; next hold CTRL and select port reset; release the CTRL key. Click the Copy button.

Selected the ports 'clk' and 'reset'

Click the Paste button and move the mouse to a position at the lower side of component u1 (see figure below). Click when you point at the correct position.

Paste ports on preload

Two component ports appear on component u1. They have the same names as the ports you copied: clk and reset. Both ports also have a connect-by-name label tag. So, we did not only copy the port, we also took care of its interconnectivity in one and the same action. We want to create the diagram ports clk and reset also by copying the ports. Select port clk and copy this port by dragging the port, while holding the CTRL key, to a position below port level. When you point at the correct position release the mouse button and then the CTRL key (keep holding the CTRL key until the drop is completed). Do the same for port reset. You have used now two different copy functions. The first copy, with the Copy and Paste button, can be used to copy objects between several diagrams. The second copy, with the CTRL key, can be used

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to copy objects in the same diagram. As both ports points upwards like the component ports, we will rotate the ports 90 degrees. Select both diagram ports, right-click and select Rotate >> 90 from the port shortcut menu. The diagram should now look like:

The diagram after copying ports

You can move a port by selecting it and than drag it to the new position.

13.4

Automatically Connect Ports

Now we also copy the port load to a position above the diagram port level creating a diagram port load. After you copied this port, right-click on one of the ports load and select More >> Autoconnect from the port shortcut menu. Now select Tag and then OK.

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Autoconnect Ports dialog

All ports in this diagram that have the name load will now become connected. The diagram should now look like:

The diagram after connecting the ports 'load'

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14

Connecting the Block Diagram Objects

We will finish the design of the block diagram in this paragraph. At the end of this paragraph the block diagram should look like:

Complete block diagram

First, however, we will introduce the concept of the process port.

14.1

About Process Ports

As stated in Processes versus Components, a process is inseparable from its enclosing architecture: it simply addresses the signals present in the architecture and does not use things like ports for interfacing. In Ease, however, we like to be clear about the usage of signals to support the on-line connectivity checking. We therefore introduce the concept of process ports. A process port is placed on the process boundary and indicates that the signal attached to this symbol is used in the process. Process ports are similar to normal component ports, in that they indicate the direction of the data flow. a signal whose value is evaluated inside the process but that is not written by any assignment statement inside the process is indicated by a process input port; a signal whose value is not evaluated inside the process but that is written by an assignment

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statement inside the process is indicated by a process output port; a signal that is both evaluated and written both inside and outside the process is indicated by a process inout port; a signal that is both evaluated and written inside the process, but that is only evaluated outside the process (thus the values are written by the process, but not by a source outside the process), is indicated by a process buffer port. The process port has no proper name because it interfaces the signal in the architecture with the process: inside the process the signal has the same name as outside the process. Adding ports to a process is even easier than adding ports to a component: you simply select the proper port symbol, indicating the flow direction, without supplying a name. All other necessary features about the process port are gathered from the attached net or connect-by-name label. Knowing this about process ports, we can now continue the design.

14.2

Adding More Ports

We will now add some ports that will be connected through "regular" nets. The output signal wr of compononent u0 indicates when the input signal level has to be stored in the entity preload: Click the Add Input Port button. Add the input port to a position on the left side of component u1, and give it the name "write" and type "<std_logic>". The process compare needs an output port for passing the result of the comparison to the input port high of component u0: Click the Add Output Port button. Add the output port to a position on the right side of the process compare and leave the Add Output Port mode. Finally, select the output port pump_on of component u0 and copy it to a diagram port, positioned directly to its right. The diagram should now look like:

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The diagram after copying the port 'pump_on'

14.3

Drawing Nets
Drawing nets in block diagrams can be done in two ways: manually or by using the automatic net router. You can manually draw nets with wire segments. If you want to use the automatic router, point out the ports you want to connect and the automatic router will draw the nets for you. First click the Add Wire Segment button and select the connection point of port pump_on of component u0. Drag to the connection point of diagram port pump_on, and click again. Draw another net between port high of component u0 and the output port of the process compare. Now click the Add Net button and draw a straight line from the connection point of port wr of component u0 to the connection point of port write of component u1. Ease will route the net around the existing objects. Leave the Add Net mode. The diagram should now look like:

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The diagram after adding the net between 'wr' and 'write'

A net that is not connected to another net or port has a small cross at the unconnected end point. An unconnected port has a small cross at its connection point like the diagram port level in the figure above.

14.4

Completing the Diagram

In the previous section we drew the nets between existing ports. However Ease has an option to add a port automatically when drawing nets. Using this option, it is not necessary to add the ports before drawing the nets. We will complete the diagram by drawing the other nets using this option: Select the Options >> User Options menu item. In the dialog that appears select the page Diagram Editors >> Block Diagram. Check that the option Auto add ports when wiring has been set. Click OK to close the dialog. The input vector level is used for entering both the preloaded reference value and the current fluid level (see Introduction). Therefore, this diagram input port has to be connected to component u1 and the process compare. Click the Add Net button and select the connection point of diagram port level. Now click to a position on the left side of component u1 where you want the input port to appear. Now click to a position on the left side of process compare and then right-click to finish the drawing of this net. With this action Ease has added an input port automatically to component u1. This port has the same

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name and range as the diagram input port. And Ease has routed the net around the existing objects as shown below:

The diagram after adding the net 'level'

The stored reference value must be passed from component u1 to process compare. Click the Add Wire Segment button and click to a position on the right side of component u1 where you want the output port to appear. The dialog Properties for new port appears as Ease will automatically create a port for this net. Replace the default name "p0" into "pre" and change the Type into "<std_logic_vector>" with Left range set to "n" and Right range set to "0". And close the dialog by clicking OK. Note that the Type list contains already "<std_logic_vector>(n downto 0)". Selecting this type from the list fills in the range fields automatically. Now click to a position on the left side of process compare to complete the drawing of this net. Leave the Add Wire Segment mode. Note that the net automatically copies the bus width "(n downto 0)" from the port pre. The diagram port level uses the diagram generic n in its range specification (as can be seen in the label level(n:0)). Consequently the component ports level and pre of component u1 also need a generic n. Copy the diagram generic n to a position inside the boundary of component u1. The default value 5 of the diagram generic n is copied to this new component generic n. To maintain a flexible design (and prevent elaboration problems) we set the actual value of the component generic to "n", thus copying whatever is transferred by the diagram generic.

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Right-click the component generic n and select Properties from the generic shortcut menu. Select the Values page and set the actual value of the generic to "n". Note that it is not necessary to copy the generic to process compare, because diagram generics are always visible inside processes.

Set actual value for component generic

The block diagram is now ready and looks like:

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Complete block diagram

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Editing the Table Diagram

We will now define the contents of the architecture rtl of the entity preload. We decided to use a table diagram for this architecture. A table diagram shows the output actions as a function of input conditions or expressions. You can create a sequential (clocked) or combinatorial table diagram. As we are developing a synchronous design we will create a sequential table diagram. Move down into component u1, which is an instantiation of the entity preload, by double-clicking in the component u1. The empty table diagram appears. First we will initialize the table by creating a column for each input and output port and setting the table diagram properties. Click the Initial empty table with all columns button.

Now the table contains 5 columns: four input ports and one output port. As we create a sequential table diagram, we must specify the clock signal: Select Diagram >> Table properties from the editor menu. The Truth Table Properties dialog appears. Go to the Clock Behaviour page of the Truth Table Properties dialog. Select clk from the Clock Edge Signal list. Select Rising edge and click OK to close the dialog. We do not modify the other table diagram properties and keep the default settings. The figure below shows the empty table diagram after specifying the columns and clock signal.

The empty table diagram

We are now ready to fill in the table cells. The first row, called R/S, specifies the asynchronous reset/ set condition. As our design has a synchronous reset we leave this row empty. The row called 1 starts the first if statement inside the clock statement. On this row we will define our synchronous reset. Select the cell identified by row called 1 and column reset, and click the Insert 1 Select the cell identified by row called 1 and column pre, and click the Insert zeros button. button.

We have now specified that when the reset is high, the output signal pre will be low. Now we define the storage of the level value as an elsif in the same if statement as the reset. See the Users Manual for more information about table diagrams. We must insert a new row. Right-click in the empty space below the row names (grey color) and select Insert from the row shortcut menu. The Insert row(s) dialog appears. Click OK to insert

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one row. Select the cell identified by row called 2 and column write, and enter " 1 ". Select the cell identified by row called 2 and column pre, and enter "level". We have now specified all relations between the input signals and output signal. To clean up the table we remove the empty columns. Select the column clk; right-click and select Delete from the column shortcut menu. Do the same for the column level. Finally we use the Auto Layout button to increase the column width of column pre.

The figure below shows the final table diagram.

Complete table diagram

Move back to the Toplevel of the project by double-clicking in the white space of the table diagram.

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Writing a VHDL File Process

We will now define the contents of the VHDL file for the process compare. As stated in About Process Ports, a process addresses the signals present in the architecture. Therefore, for Ease to write a process skeleton, it first has to determine the names of the signals interfacing with this process. Before generating (or updating) a process skeleton, a quick verification of the block diagram architecture is performed. Ease always creates internal net names for signals that do not have a name. Process ports take over a number of properties from the net they are connected to among which is its name. The process compare, as we see, has three process ports. To make sure that you will not have to use internal net names in the VHDL code, we have to name these nets. We do not need to name the first net coming from diagram port level(n:0). This is because the signal is already defined in the diagram, being a diagram port. The other nets however are connected to other entities and therefore do not have a signal name within this architecture. Right-click the net between port pre of component u1 and the process input port and select Properties from the port shortcut menu. Change the net name from "pre" to "loaded" and click OK. The net label loaded(n:0) appears next to the net. The net between the process output port and the port high of component u0 has the name "high", we will not change this name. Now move down a level into process compare. The built-in editor will appear with the process body file for process compare:

Process skeleton 'compare'

At the start of this process body file you see a comment block which is a copy of the process interface. This copy is automatically updated when something changes. For that purpose, two meta-comment strings "-- EASE/HDL begin" and "-- EASE/HDL end" are put before and after the copy, allowing Ease to recognize what part of the body file can be updated, without the risk of modifying

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user-defined code. Enter this if-statement between the phrases "begin" and "end process compare ;" (at the location of the hand symbol in the figure above) of the process statement part: if (loaded < level) then high <= '1'; else high <= '0'; end if; Save the file and exit Scriptum. The design of the process compare is now ready.

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Creating the Toplevel

We started our tutorial project with the current block diagram. Now is the time to move up one level from the current block diagram. Because, as you may have noticed, we only defined a (block diagram) architecture as our current Toplevel. We did not explicitly define the entity pump yet. One of the strong points of Ease is the ability to work bottom up as well as top down. The entities control and preload were in fact created in a top down manner: first we defined the interfaces of these design parts, then we defined their contents, using, among other things, the architecture and process skeletons. But we can work bottom up as well. The entity pump is implicitly (partly) defined by the definition of the diagram ports and diagram generic in the current Toplevel architecture. We now create the entity pump by going up one level. Right-click in the white area of the Toplevel diagram and select Create new Toplevel from the shortcut menu. The dialog Name for current top level object appears. This dialog looks the same as the dialog for a new entity except that you can not change the contents of the architecture as you created this already. Change the component identifier to "u0" and enter the entity name "pump" for the entity of which the current level is a block diagram architecture. You now see a new Toplevel, containing one component instantiation of the entity pump as shown below:

The pump controller

The boundary of the component has default dimensions; you may resize the component by selecting the block and using the resize handles at the corners of the block. The input ports level(n:0), load, clk, and reset have default positions at the left side of the component boundary, while the output port pump_on appears at the right side. The generic n appears on the body of the component. You can change these default positions by moving the ports along the side of the component and the generic inside the component. Note: You will not find the component identifier u0 in the final VHDL output, because the Toplevel block diagram architecture is only used for supplying a context for the design entity pump representing your system (see also Starting the Application). Any actual value of the component generic n will be

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ignored. A new level of hierarchy has been added to your project.

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Generating VHDL Output

The project is now ready for generating VHDL output. First we will set the toplevel marker and check the project for errors. Right-click the component u0 of entity pump in the Editor Window and select Entity >> Mark as Toplevel Output from the component shortcut menu. In the Browser Window an orange triangle appears before entity pump. Select the button Verify from HDL Output Marker to check the project for errors. .

There should not be any errors or warnings. Check that the entries in the Browser Window (entities, and architectures) have an error-free status indicated by green "OK" markers If you have errors or warnings you can double-click on it in the Verification Results tab of the Console Window. The object mentioned in the message is selected and you can fix the error or warning. Now we will generate VHDL output for this example project. But first we will setup the output settings for the project. These settings will be used each time we generate output for it. Select Properties from the project shortcut menu, and go to the HDL >> Files page:

Set output file organization

For the HDL Files organization option select: "Entities/Modules with Architectures". We will specify the output location for the VHDL files to be generated. In the Browser Window, right-click the design library design and choose Properties from its

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shortcut menu, select the HDL Settings page:

Specify output directory for library 'design'

You can enter a directory in the Output Directory field or use the browse button. A relative directory will be relative from the project directory <project>.ews. In the figure above, the directory design. hdl will be created, if not exist, in the directory my_pump.ews. Type any directory you like in the Output Directory field, or keep the default. We are now ready to generate VHDL output for the project that you just created. Use the Generate all HDL Output (starting from marker) files for all entities in the hierarchical tree of entity pump. The report window in the Scriptum editor will look like this: button to generate VHDL output

Report of output generation

Double-click one of the lines with a blue square HDL file.

in this output window to open the associated

Another way of viewing the generated output, is selecting HDL >> View Generated HDL from

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the entity or architecture shortcut menu in the Database View of the Browser Window. Now the file that is generated for the selected entity is displayed in the built-in editor Scriptum: you do not have to leave Ease. Note that the File View tab page of the Browser Window shows all generated HDL files. Doubleclicking a file in this view opens also the HDL file.

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19

Configurations
A configuration is a collective description of the bindings of architectures to component instantiations in the project. Ease supports multiple architectures. For each component instantiation, the architecture that is to be bound (from a set of multiple architectures for an entity), must be specified. When a particular binding is defined for all component instantiations (i.e. a configuration is composed), you can give this configuration a proper name and info string, so that you are able to recall this configuration later. Let us try to clarify this with an example. In order to define different configurations, you need to know how to define different architectures for one entity, and how to change the bindings of a component. Let us start defining different architectures for an entity. We will elaborate the design you have created in the former chapters. Please open the project my_pump again if it is not open yet. Make sure you are in the Structure diagram of entity pump.

Browser Window

In the Database View tab page of the Browser Window, you can see that all entities in the project have one architecture (i.e. the entity pump has only the architecture structure). Right-click either the component u1 of entity preload in the Structure diagram and select Entity >> New >> Architecture from the component shortcut menu, or right-click the leaf of entity preload in the Browser Window and select New >> Architecture from the entity shortcut menu.

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Give the new architecture the name a0 and set its Contents to "HDL File":

Add architecture 'a0' to entity 'preload'

We still need to add the VHDL source code for the new architecture. Double-click the a0 of the preload leaf in the Browser Window. The editor Scriptum appears, with this skeleton for the architecture:

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Architecture skeleton

Enter this process statement between the phrases "begin" and "end architecture a0 ; " (at the location of the hand symbol in the figure above): process (clk) is begin if rising_edge(clk) then if (reset = '1') then pre <= (others => '0'); elsif (write = '1') then pre <= level; end if; end if; end process; Save the file and exit Scriptum. You have now finished adding a second architecture to entity preload. Now we will define certain configurations for this project. One configuration for the table diagram architecture rtl, and one for the VHDL file architecture a0. Right-click the rtl of the preload leaf in the Database View tab page of the Browser Window and select New >> Configuration from the shortcut menu. The Configuration Properties dialog will appear. Fill in the Name and Comment fields for the configuration as shown below. Click OK .

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Create configuration 'Table_source'

Create another configuration for the a0 architecture. Right-click the a0 of the preload leaf in the Database View tab page of the Browser Window and select New >> Configuration from the shortcut menu. The Configuration Properties dialog now appears. Enter the text "Hdl_source" in the Name field, and the text "Configuration for the VHDL source code" in the Comment field of this dialog and click OK. Create also a configuration for the structure architecture of entity pump. Right-click the structure of the pump leaf in the Database View tab page of the Browser Window and select New >> Configuration from the shortcut menu. In the Configuration Properties dialog that appears enter the text "Top_configuration" in the Name field, and the text "Configuration for pump" in the Comment field of this dialog and click OK. Right-click the Top_configuration of the pump leaf in the Database View tab page of the Browser Window and select Show Hierarchy from the configuration shortcut menu. This opens the Hierarchical View tab page and shows the hierarchy of this configuration. The figure

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below shows the Database View and Hierarchical View after creating the configurations.

Browser Window after creating the configurations

The Hierarchical View shows that the configuration Table_source with its associated architecture rtl is used for the entity preload. Expanding the Alternative bindings leaf shows the other configuration Hdl_source for the entity preload. Click on the plus sign of the Alternative bindings leaf in the Hierarchical View to expand this leaf. Right-click the u1:preload:a0(Hdl_source) leaf and select the Bind menu item. Note: the configuration Hdl_source is now bound to the entity preload as shown in the Hierarchical View. Have also a look in the structure block diagram of the entity pump. This diagram shows also that the configuration Hdl_source has been bound to the entity preload. We finalize this part of the tutorial by verifying the design, to make sure no errors have been introduced.

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Configurations

Right-click the Library: design leaf in the Database View and select the Verify menu item. The Verification Results tab page of the Console Window should not report errors. This ends our tutorial on creating configurations for your project. You can now create different configurations for your project where you can account for system and/or chip dependencies.

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Import VHDL
Using Ease you can create hierarchical block diagrams from existing VHDL. This means that you do not need to redo all the work! You simply import the source code, and the port layout of the blocks will be created, the blocks are placed in the diagram and connected by nets. Ease does it all for you. As an example, we will use output from the round-robin project from the examples that are supplied with Ease. We will import the generated output for the entity arbiter and its sub-tree into a blank project. Ease will then re-create a functional copy of the original arbiter implementation. Create an empty project, by selecting File >> New. Make sure the project is in VHDL mode (the status bar in the Editor Window indicates: "Language: VHDL"). See Setting HDL Mode how to set the HDL mode. Now select File >> Import >> HDL Files, or use the Import HDL Files button.

The HDL Import wizard appears, as shown in the figure HDL Import wizard, page 1 below. Make sure that the language to be imported is set to "VHDL". Click the button . Go to the Ease examples directory. In this directory you will find a directory tutorial. Select this directory and click OK. In the File System list you will see all files in the selected directory, that have the selected File extension. Select the file arbiter.vhd in the File System list and click the button.

The file arbiter.vhd is now added to the Selected Objects list. All files in the Selected Objects list will be imported.

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Import VHDL

HDL Import wizard, page 1

Make sure only the file "arbiter.vhd" is in the Selected Objects list. Click button Next, to go to the second page of the import wizard. All files of the Selected Objects list are processed to determine dependencies (file order) and targeted design library. The processing result is shown in the second page. Click button Next, to go to the third page of the import wizard. On the third page you can control the import type. Change the Import Style into "Block Diagram" for both entities as shown below and click button Next.

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HDL Import wizard, page 3

On the fourth page a number of options controlling the import process, can be set. Check that the Concurrent stat. box is set to "Group all". All concurrent signal assignments within one entity will now be grouped into one concurrent statement block. Check that Port and Generic distance has been set to "2" and the same applies to Corner distance. Click Finish to start the import process. The Database View tab page of the Browser Window shows that the entities that you have just imported are put in the design library design.

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Import VHDL

Browser Window after HDL import

You can now instantiate the sub-tree wherever you want in the project. In this case we simply instantiate it in the Toplevel diagram that is still empty. Drag the entity called arbiter from the Browser Window to the work sheet of the Editor Window. In the work sheet release the mouse button and move the rubber image of the component to a convenient spot in the Toplevel diagram and click to place it. Use the default component label u0. You can also use the Instantiate existing Entity or Module button to instantiate a component. The Instantiate dialog appears in which you can select the entity to instantiate: In the Database View tab page of the Browser Window, right-click the entity arbiter leaf and select Show Hierarchy from its shortcut menu. The Hierarchical View tab page of the Browser Window shows the hierarchy that is created from the VHDL source code by Ease as shown below.

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Hierarchical View of entity 'arbiter'

Now go down one level into the arbiter block (see Navigating Through the Project how to navigate through a project). The automatic placer routine of Ease has placed the blocks of the arbiter diagram automatically and the automatic router routed the whole diagram, as you can see in the figure below.

Automatic placement and routing of the 'arbiter'

This concludes the description of importing VHDL source code in Ease, using automatic place and route facilities. This ends our Ease VHDL Tutorial. We hope you enjoyed reading through it. More information can be found in the Ease User's Manual and on our web-site: www.hdlworks.com. On our web-site you will also find a few white papers describing some topics not covered in this

2011 HDL Works

Ease VHDL Tutorial

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Import VHDL

tutorial.

Ease VHDL Tutorial

2011 HDL Works