Creating a BRAM-based Entity Using Xilinx CORE Generator

by Ambarish Vyas and Kris Gaj ver. 1.0 Dec. 15, 2010

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Core-Generator Tutorial

In this tutorial, we will show how to create a simple entity based on an embedded block memory (BRAM) using Xilinx tool called CORE Generator. Our entity implements function of an AES S-box. AES S-box is a 256 x 8 bit look-up table, which can be implemented using 256x8 bit ROM. Such ROM has an 8-bit address and an 8-bit output. Since BRAM can only have synchronous outputs, our entity will have an extra clock input, clk. In order to generate files required to instantiate this component in our circuit for the purpose of simulation, synthesis, and implementation, you need to perform the following tasks. Step 1: Generating a Coefficient File Prepare a coefficient file (with extension .coe) containing the required contents of the 256 x 8 bit ROM. This file is provided together with this tutorial. As you can see it contains two parameters: memory_initialization_radix and memory_initialization_matrix. memory_initialization_radix is set to 16, which means that all memory locations will be specified in the hexadecimal representation. memory_initialization_matrix is a comma separated list of values at all 256 memory locations. In case of AES S-box, these values come from the specification of the AES algorithm. In case of implementing other components of SHA-3 candidates, these values can be taken from the: specification of the respective hash function, reference C implementation of the given hash function, or VHDL code of the basic architecture (in which a given entity is implemented using Xilinx distributed memory). Step 2: Choosing FPGA Device For a given Xilinx family, you may check how many BRAMs are available in each FPGA device belonging to the given family. In order to do that, please see your installation of ATHENa, and browse to device_lib/xilinx_device_lib.txt For each family, this file contains the list of devices supported by your version of Xilinx ISE, as well as the amount of resources (including the number of BRAMs) per each device. Alternatively, you can use specification of a given FPGA family at the Xilinx web site. For example if you need to use 16 S-boxes in your hash function, than you need at least 8 dual-port BRAMs, or 16 single-port BRAMs. Thus, the smallest Spartan 3 device, with only 4 BRAMs will be insufficient.

ECE-545 Step 3: Starting CORE Generator

Core-Generator Tutorial

You can open CORE generator from the Start->All Programs menu of Windows (typically under Xilinx ISE->ISE->Accessories->CORE Generator), and then create a new project, or you can open an existing project in Xilinx ISE and then click on Tools-> Core Generator. You should see the following window:

Expand the Memories & Storage Elements tab on the left hand side, and you can see Block Memory Generator, double click on it.

Step 4: Defining the Width and Depth of Memory

After choosing Block Memory Generator, a window will pop up and you should be able to see a symbol of BRAM on your left, with input/output ports and clock.

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Core-Generator Tutorial

You can give your component a name (e.g., sbox). Then, select a memory type: i.e. ROM/RAM, Single Port/Dual Port. We have selected Single Port ROM, and left the rest of the parameters at their default values. You can do the same, or change Single Port to Dual Port. Click Next. The next window allows you to enter the memory width and depth. Width specifies the output size, or the size of the data stored at each location of ROM. Depth specifies the number of elements in the ROM. We will choose Read Width = 8 and Read Depth = 256 (These are standard sizes for an AES Sbox). You can choose these parameters according to your specific needs.

In the figure above you can see the ADDRA is 8 bit and DOUTA is 8 bits. We have left enable as Always Enabled, if you need one for your design you can select to use ENA port and you will have one more input port in your entity. Click Next.

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Core-Generator Tutorial

Step 5: Initializing Memory

If you are using the BRAM as a ROM, you need to initialize it with values. In the window leave everything as it is and click on load INIT file under memory initialization. It needs a .coe file. A simple sbox.coe file is provided together with this tutorial. Please browse to the location of this file and choose it from the list of files stored in the same folder. Click Next. Step 6: Generating a Component If you need a reset pin, select use RSTA pin, and click next. We will leave it as it is and then click on Next. Then, click on Generate in the next window leaving all other parameters at their default values.

You can see an instance called sbox is created on the bottom left side. Now you can safely close the core generator.

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Core-Generator Tutorial

Step 7: Simulation
There will be a directory called ipcore_dir created in your project folder. This directory will have all the CORE generator files. Now, go to Project->Add source->browse to ipcore_dir->select sbox.vhd (or your file name). The file with extension .vho should contain component declaration, and example of component instantiation. Use these templates to instantiate a newly created component in an appropriate location of your VHDL code. You will need to change your previous memory instantiation, as you now have at least clock, and possibly also enable/reset ports too. You can test your module by writing a small testbench generating several addresses.

Step 8: Synthesis
Before you synthesize, right click on Synthesize and choose Process Properties. Chose HDL options under Category. You will see a window as shown below.

Choose RAM/ROM style as Block instead of Auto. Now select Advanced as property display level. Check the option Automatic BRAM packing. This will instruct the tool to pack two Single-Port memories with the same content into one Dual Port memory. Click OK. You are ready to synthesize your circuit. In order to use ATHENa for synthesis and implementation, please read Chapter 5.2 of the ATHENa tutorial. 7