MIMO TRANSMISSION USING PARASITIC ARRAY ANTENNA

by

Chamath Divarathne
chamath@cmu.edu B. Sc. Eng, University of Peradeniya, 2007

A THESIS submitted in partial fulfillment of the requirements for the degree

MASTER OF SCIENCE IN INFORMATION NETWORKING (MSIN)

Information Networking Institute (INI) The College of Engineering CARNEGIE MELLON UNIVERSITY 2010

Co-supervised by: Prof. Constantinos Papadias

papadias@ait.edu.gr

Prof. Antonis Kalis

akal@ait.edu.gr

DECLARATION
I Chamath Divarathne, declare that the work presented in this thesis is original and no part of it (including the document, the implementation code, etc.) has been copied from other sources. Work related to this one is cited appropriately.

Chamath Divarathne 30.04.2010

The work contained in this thesis MIMO Transmission using Parasitic Antenna Arrays by Chamath Divarathne has been carried out under my supervision.

Constantinos Papadias 30.04.2010 Athens Information Technology

Antonis Kalis 30.04.2010 Athens Information Technology ii

ABSTRACT
Multiple-Input-Multiple-Output (MIMO) transmission is one of the promising antenna technologies used for wireless communication. When the transceiver uses more than one antenna, the antennas must be placed at least half of the carrier wavelength apart, in order to transmit/receive uncorrelated signals. As a result size and cost sensitive devices like mobile terminals cannot facilitate MIMO transmission. Parasitic antenna on the other hand, uses only one active RF front end along with two or more parasitic elements which can be placed much closer resulting in a compact design. The parasitic elements can be electronically switched to form different antenna beams for the active RF feed, in each symbol period. Both theory and computer simulations have shown that, these different beams can be used to have MIMO transmission with traditional uniform linear array (ULA) antennas placed at the receiver. This work involves configuring and customizing a classical MIMO testbed to use a 3-element electronically steerable parasitic array radiator (ESPAR) at the transmitter and traditional two ULA of antennas at the receiver, using BPSK modulation. Vertical Bell labs Layered Space Time (V-BLAST) architecture was used together with zero forcing equalizer at the receiver, to verify over-the-air MIMO transmission using the parasitic antenna.

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ACKNOWLEDGEMENT
Take this opportunity with the great pleasure in repressing the appreciation and profound personal regards for my co-supervisors Prof. Constantinos Papadias and Antonis Kalis. I would like to pay a special gratitude to Stanford University for donating the MIMO testbed to the B-WiSE laboratory of Athens Information Technology. Finally the assistance and guidance from Mr. Frank McCarthy, Mr. Osama Al Rabadi, Mr. Philippos Tragas and Mr. Keshav Singh throughout the work are highly appreciated.

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TABLE OF CONTENT
ABSTRACT........................................................................................................... III ACKNOWLEDGEMENT..................................................................................... IV TABLE OF CONTENT ..........................................................................................V TABLE OF FIGURES .......................................................................................... VI 1 2 INTRODUCTION ........................................................................................... 1 LITERATURE SURVEY................................................................................ 3 2.1 2.2 3 MIMO TRANSMISSION ................................................................................ 3 PARASITIC ANTENNA ARRAYS .................................................................... 5

MIMO TESTBED OVERVIEW................................................................... 10 3.1 TRANSMITTER HARDWARE UNIT ............................................................... 12 3.1.1 DSPTX chip main board....................................................................... 13 3.1.2 DAC40 daughter card. ......................................................................... 14 3.1.3 I/O Board............................................................................................. 16 3.1.4 MMDS RF modules. ............................................................................. 18 3.1.5 Thunderbolt GPS synchronization unit. ................................................ 21 3.1.6 RF Filters............................................................................................. 22 3.1.7 Power units. ......................................................................................... 22 3.1.8 IP Engine. ............................................................................................ 22 3.2 RECEIVER HARDWARE UNIT ..................................................................... 23 3.2.1 MMDS RF modules. ............................................................................. 24 3.2.2 ADC daughter card.............................................................................. 25 3.2.3 IP Engine. ............................................................................................ 26 3.2.4 Time and Sync Card (TAS). .................................................................. 29

MIMO TRANSMISSION EXPERIMENT................................................... 30 4.1 4.2 4.3 4.4 4.5 4.6 HARDWARE CONNECTIONS ....................................................................... 30 TRANSMITTER UNIT CONFIGURATION ......................................................... 32 EXPERIMENT SPECIFICATIONS ................................................................... 35 DOWNLOADING A CODE TO THE DSP ......................................................... 35 TRANSMITTER SIDE INTERFACE ................................................................. 36 RECEIVER SIDE INTERFACE........................................................................ 38

5 6

RESULTS ...................................................................................................... 41 CONCLUSION AND FUTURE WORK ...................................................... 45

REFERENCES ...................................................................................................... 46 APPENDIX A ........................................................................................................ 47 APPENDIX B ........................................................................................................ 50

TABLE OF FIGURES
FIGURE 1: MAJOR COMMUNICATION BLOCKS USED IN MIMO TRANSMISSION ............... 1 FIGURE 4: NORMALIZED 3-ELEMENT ESPAR ANTENNA BASIS FUNCTIONS .................. 6 FIGURE 5: MIMO TESTBED SETUP............................................................................ 10 FIGURE 6: TRANSMITTER UNIT BLOCK DIAGRAM........................................................ 12 FIGURE 7: SNAPSHOT OF THE TRANSMITTER UNIT ..................................................... 13 FIGURE 8: DSP MAINBOARD BLOCK DIAGRAM ......................................................... 13 FIGURE 10: SNAPSHOT OF THE IO BOARD.................................................................. 16 FIGURE 11: CABLE CONNECTION OF THE IO BOARD................................................... 17 FIGURE 12: TRANSMITTER RF MODULES .................................................................. 18 FIGURE 13: GPS SYNCHRONIZATION UNIT ................................................................ 21 FIGURE 15: RECEIVER UNIT BLOCK DIAGRAM ............................................................ 23 FIGURE 16: SNAPSHOT OF THE RECEIVER UNIT ........................................................... 24 FIGURE 17: ADC BLOCK DIAGRAM .......................................................................... 25 FIGURE 18: SNAPSHOT OF THE IP ENGINE.................................................................. 26 FIGURE 19: CABLE CONNECTION BETWEEN DSP & IP ENGINE ................................... 27 FIGURE 20: BLOCK DIAGRAM OF IP ENGINE .............................................................. 27 FIGURE 21: HIGH LEVEL SYSTEM DIAGRAM OF THE MIMO TESTBED ........................ 30 FIGURE 22: LO CONNECTIONS .................................................................................. 31 FIGURE 23: TRANSMITTER SIDE PROCESSING ............................................................. 32 FIGURE 24: SCHEMATIC DIAGRAM OF THE COMPARATOR CIRCUIT USED...................... 33 FIGURE 26: COMPARATOR INPUT AND OUTPUT SIGNAL .............................................. 34 FIGURE 27: SNAPSHOT OF THE OSCILLOSCOPE SCREEN FOR COMPARATOR INPUT AND OUTPUT ............................................................................................................ 34 FIGURE 28: DSP MAINBOARD................................................................................... 35 FIGURE 29: TRANSMITTER SIDE INTERFACE ............................................................... 36 FIGURE 30: INPUT PARAMETERS FOR BASEBAND SIGNAL GENERATION........................ 37 FIGURE 31: RECEIVER SIDE INTERFACE SNAPSHOT ..................................................... 38 FIGURE 32: ADC POWER MEASUREMENT UTILITY INTERFACE.................................... 39 FIGURE 33: IN-PHASE AND QUAD-PHASE SIGNALS OF ONE OF THE RECEIVING ANTENNA ........................................................................................................................ 40 FIGURE 35: RECEIVED CONSTELLATIONS AT THE TWO ANTENNAS .............................. 42 FIGURE 36CONSTELLATION DIAGRAM FOR THE TWO SUB STREAMS............................ 43 FIGURE 37: BER COMPARISON FOR THE THREE SCENARIOS ....................................... 44

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1 Introduction
Mobile communication is well popular among the world in day to day life. With the ever increasing sophisticated mobile applications, the requirement of having high data rate communication is a challenge. There are several technologies which caters this requirement such as W-CDMA, and WiMax.

Multiple-input-multiple-output (MIMO) transmission is one of the promising antenna technologies used for wireless communications. Through spatial multiplexing, MIMO achieves high capacities. The only limitation is that, the transmitting and receiving antennas should be placed at least half the wave length of the carrier signal in order to transmit or receive uncorrelated signals. Apart from that, each of transmit or receive antenna requires a separate circuit which means, higher the no of antennas used higher the cost.

Modulation

Up Conversion

Down Conversion

Demodulation

Modulation Up Conversion Transmitter

Down Conversion

Demodulation

Receiver

Figure 1: Major communication blocks used in MIMO transmission

Due to these reasons, implementation of traditional MIMO transmission with multielement (MEA) arrays on cost and size sensitive devices like mobile terminals is not feasible. A novel approach to MIMO transmission using a single RF front end was introduced in [1] and [2]. In [1], a novel methodology for using electronically

steerable parasitc array radiator (ESPAR) antennas as a compact, cheap and less power-hungry MEA, for spatial multiplexing BPSK symbols. The simulated results have shown that this methodology still provides comparable spectral efficiency and performance as traditional MEA.

This work involves verifying over-the-air MIMO transmission using a 3-element ESPAR at the transmitter and a traditional 2 MEA using at the receiver. A traditional MIMO testbed was used and customized to facilitate the ESPAR at the transmitter. The received data is analyzed using Matlab to evaluate performaces.

2 Literature Survey
2.1 MIMO Transmission
In the never-ending quest for capacity increment in wireless communication, MIMO system architecture has shown the possibility of increasing the capacity substantially. Fading is considered as a challenge in wireless communication. But in MIMO channels it uses the fading to obtain high spectral efficiency.

Spectral efficiency is the capacity of the channel per unit bandwidth, which is measured in bits per second per Hertz (bps/Hz). MIMO transmission achieves high spectral efficiency using the spatial multiplexing. In spatial multiplexing different signals are transmitted from different antennas at the same time, so that receiving antenna array receives a superposition of all the transmitted signals. The receiver solves a linear equation system to demodulate the message. This provides an additional degree of freedom, which increases the spectral efficiency. Figure 2 illustrates the idea behind spatial multiplexing.

Tx 1 Tx Data Stream Tx 2

Rx 1 Rx Rx 2 Data Stream

Figure 2: Spatial Multiplexing

One of the common receiver

processing schemes used for solving these linear

equation system is called Vertical Bell lab LAyered Space Time (V-BLAST) [3]. VBLAST together with zero forcing equalizer is briefly explained in terms of linear equations.

Assume,

NR NT L H H# X X^ W Z

= No. of receiving antennas = No. of transmitting antennas = Burst size = Channel matrix = Pseudo inverse of H = Transmitted BPSK matrix = Decomposed BPSK matrix = Decomposing matrix = Received signal matrix with dimensions (NRxNT) (NRxNT) (NTxL) (NTxL) (NTxNR) (NRxL)

The received signal mixed by the channel is given by, Z =H.X

Zero forcing equalizer yields, W = H#

Finally, the decomposed BPSK symbols were given by, X^ = W.Z

There are other receiver processing schemes such as Maximum Ration Combining (MRC), MRC with Successive Interference Cancellation (MRC-SIC) and Maximum Likelihood decoder.

2.2 Parasitic Antenna Arrays

ESPAR is a smart antenna system which is able to control the beam patterns dynamically while being implemented using a single active antenna and number of parasitic elements placed around the active element. The parasitic elements are short circuited and loaded with variable reactors (varactors), to control the input impedance. By adjusting the varactors response beams can be formed in certain directions either in an adaptive or predefined fashion. [4]

Figure 3: 3-element ESPAR Antenna

When the ESPAR antenna is used for the uplink transmission scenario, where the receiver is equipped with traditional ULA, the system is physically a single input single output (SIMO) system as there is only one active element at the transmitter. However instead of sending symbols using uncorrelated antennas like in the traditional approach, they are mapped onto uncorrelated set of patterns as follows.

si is the ith symbol to be spatially multiplexed and bi is the ith basis function composing the ESPAR pattern

The far field pattern of a three-element ESPAR antenna with an inter-element spacing of d can be written as,

B1 and B2 are orthogonal to each other theoretically; they can be simplified as follows. B1 = 1 B2 = cos() Following figure shows two basis functions B1 and B2 with normalized power, when the inter-element spacing d = /16. (omni directional)

Figure 4: Normalized 3-element ESPAR Antenna Basis functions

By estimating response from each receiving antenna to each basis function symbols are de-multiplexed and later demodulated. For a system with 2 receiving antennas and 2 basis functions at the ESPAR antenna, then the radiation pattern would look like G = [g0 g1 gL-1]T

where gl is the sample of the array pattern. The patter is decomposed into a linear combination of two basis functions such that they are orthogonal to each other. b1 = [b1,0 b1,1 b 1,l-1] b2 = [b2,0 b2,1 b 2,l-1] let hl be the complex gain of the path l. Then the responses of the two receive antennas to the basis function b1 + b2 (corresponding to the symbol pair [1 1]T) will be,

Equivalently,

which yields to,

hij is the response from ith receiving antenna to the jth basis function. It is evident that linear combination of field patterns gives a linear combination of antenna responses.

Now the receiver can simply decompose the vector of the receiving antenna responses,

that denotes the SIMO channel, into a MIMO channel as follows.

Possible radiation patterns B [1 1] B [1 -1] B [-1 1] B [-1 -1] = = = = b1 + b2 b1 b2 (b1 b2) (b1 + b2)

These four combinations can be generalized as,

s

s1 (b1+(-1) b2)

s = b1xorb2
Thats why the active element of the parasitic antenna is always fed with the first symbol stream and the depending on the xored result of the two streams, the parasitic elements are switched using pin diodes.

A training sequence can be used to train the receiver as follows. Sending BPSK symbol pairs [1 1]T and [1 -1]T by transmitting (b1+b2) and (b 1-b2) respectively, gives the response first receiving antenna to the two beams as follows,

So that, the response from the first receiving antenna to the basis function b1 and b2 can be obtained as follows.

The same procedure applies to the second antenna as well. Finally the coefficients of H are fed to the V-BLAST algorithm as discussed in the previous section to demultiplex and demodulate the original symbols.

3 MIMO Testbed Overview

MIMO Test bed at a glance,

No. of MMDS Transmitter RF modules No. of MMDS Receiver RF modules

up to 2 up to 2

Carrier Frequency Signal Bandwidth

2.5 to 2.7 GHz (MMDS Band) up to 1 MHz

GPS synchronization feature. Stores gathered data into a computer, connected via 10BaseT Ethernet. Interfaces for tapping the Intermediate Frequency (IF) signal from the RF modules (only at receiver RF modules).

Tx Unit Host Computer Rx Unit

Rx Antennas Tx Antennas

Figure 5: MIMO Testbed Setup

Above figure shows the overall setup of the MIMO testbed including transmitter and receiver units, transmitting and receiving antennas together with the host computer.

The MIMO test bed consists of two major prototype units. 1. 2. Transmitter Unit. Receiver Unit.

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Transmitter Unit
This unit consists of following major sub-units. DSPTX chip main board. DAC daughter board (attached to DSP main board). I/O board. MMDS RF modules. (2 Nos) Thunderbolt GPS synchronization unit. RF Filters. Power units (2 Nos) IP Engine.

Receiver Unit
This unit consists of following major sub-units. DSPRX chip main board. ADC daughter card (attached to DSP main board). I/O board. Thunderbolt GPS synchronization unit. MMDS RF modules. (3 Nos) RF Filters. Power units (2 Nos) IP Engine. Time and Sync Card (TAS)

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3.1 Transmitter Hardware Unit

The transmitter hardware unit is responsible for converting bits to modulated baseband signals and then finally to transmit with a RF carrier using the available antennas. The control signal path and the data signal path is illustrated in figure ??.

ipEngine

Power Unit

IO Board DSP Mainboard

Reference Signal

DAC Master Control signal path Data signal path Slave RF Modules

GPS Unit

Front-end Filters

Figure 6: Transmitter unit block diagram

First the code writing for the Digital Signal Processor (DSP) is downloaded to the DSP using RS232 serial cable from the host computer. Then the DSP cofigures the two RF modules via the IO Board. The master RF module takes a 10 MHz reference signal from the GPS unit, which is used to generate the internal local oscillator frequencies.

Once the RF module initialization is completed successfully, DSP sends Digital to Analog Converter (DAC) with the digitized data generated for the baseband signal depending on the modulation scheme. Each RF module has to be fed with in-phase and quadrature-phase baseband signals. So DAC uses 4 independent channels to generate these baseband signals for the two RF modules namely, master and slave. Finally the output RF signals produced by RF modules are passed through the frontend RF filter before transmitting using the transmitting antenna.

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Power Unit ipEngine IO Board

DSP Mainboard

GPS Unit

RF Filters RF Modules

Figure 7: Snapshot of the Transmitter Unit

Description of each sub module found in the transmitter unit is given below.

3.1.1

DSPTX chip main board.

Figure 8: DSP Mainboard Block Diagram

DSP chip

Innovative DSP 320C6201. (Clock to 200 MHz)

Digital I/O port a 40-pin connector with 32 data pins. (JP1) JTAG Port Serial Port connect via JTAG debugger to the host. (JP 8) communicate with the RS232 port of a PC

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Omnibus DAC40 daughter card is connected using this. (JP12 & JP17)

There are two possible ways to download code from the PC host to the target (DSPTX). First method is using JTAG debugger. The C program is written in Code Composer Studio and downloaded to the DSP using the JTAG debugger. The second method is to RS232 Serial port to connect the PC to the relevant port in the DSPTX. For that the software program called Uniterminal is used. The COFF file is generated using the Code Composer Studio (ex. Hello.out) and downloaded to the DSP.

First of all generation of the analog baseband signal is described. The C code generates the baseband signal and uses OMNIBUS to transfer those data to the Digital to Analog converter (DAC40).

More details can be found in the CH11 of [11].

3.1.2

DAC40 daughter card. DAC40 OMNIBUS module provides 4-channel, high-speed (40MHz) 14bit resolution analog-to-digital conversion facility. Used to generate two (2) In-phase and two (2) Quad-phase signals for the two MMDS RF modules. (Master and slave)

The DAC40 OMNIBUS module gives the target processor card four channels of very high speed 40 MHZ, 14-bit resolution digital input to analog output conversion (D/A). This makes the DAC40 module well suitable for use in high-speed signal and arbitrary waveform generation, communications, and control systems. The DAC40 module uses four Analog Devices AD9764 D/As (one for each channel) along with the necessary output buffering, allowing for independent channel control. The AD9464 features 72 dB total harmonic distortion and a spurious free dynamic range of 75 dB, which is ideal for communications applications. The output is +/- 2V (max) into a 50-ohm load, which is DC accurate and can be calibrated.

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Figure 9: DAC40 Black Diagram

The DAC40 module has special memories (SARAM) placed between the DSP and the D/As. This allows the module to load waveform tables into memory for uninterrupted repeated playback independent of the DSP. This relieves the DSP from servicing the D/A at the high rates generally required for waveform generation. The DSP simply loads and playback table into RAM after which it may be played back continuously at full rate. The DSP may update the contents of the SARAM while playback is occurring without interrupting the current playback. Additionally, the DSP may bypass the SARAM and communicate directly with the DAC when necessary.

These four DAC channels are used to generate In-phase and Quadrate-phase baseband inputs to the each RF modules. So with one DAC40 module two RF modules can be fed with corresponding baseband signals.

After the baseband signal is generated successfully with the help of DAC40, RF module configuration is described. DSP uses 32 bit Digital port to communicate with RF module. First control and data signals are transferred from DSP main board to the I/O board.

More details on DAC40 can be found in CH8 of [9]

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3.1.3

I/O Board. Acts as a facilitator to configure and check the status of the MMDS RF modules. Communicate with DSP, using the W7A cable, connecting JP 1 of DSP main board and J-15 of IO board. Communicate with RF modules, using W2A and W1B cables.

Figure 10: Snapshot of the IO Board

The I/O Board for the Gigabit Wireless Prototype is a custom PCB that is meant to provide power and signal interconnects between internal components. A toplevel block diagram of the I/O Board is shown below.

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Figure 11: Cable connection of the IO Board

So I/O board receives control and data signals from the DSP main board and forward them to the corresponding RF module which has been already configured as a master or slave.

More details on I/O Board can be found in [10]

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3.1.4

MMDS RF modules. MMDS RF moduels operates in the MMDS frequency bands which is from

2.5 GHz to 2.7 GHz.

Figure 12: Transmitter RF Modules

Currently there are two RF modules namely master and slave. Each module takes in in-phase and quad-phase from the DAC40. Master RF module takes a 10MHz carrier signal from GPS synchronization unit (using W18B cable) and according to the LO configuration given in the following reference, master shares LO1 and LO2 output carrier signals with the slave RF module.

Finally the modulated RF signals are produced and they are connected to the RF filters using W14D and W14E RF cables.

Following table describes the connections and different interfaces of RF modules.

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19

Apart from that each RF module contains a 25-pin control connector. One analog input signal provides for control of the transmitter output level (by controlling the IF gain). The remaining signals are digital and provide for radio configuration, control, and status monitoring. The pin numbers, signal names, and functions for the DE25P connector are described in the following table.

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More details on MMDS RF modules can be found in [11] and Cable configuration for MMDS RF modules can be found in [12]

3.1.5

Thunderbolt GPS synchronization unit.

Figure 13: GPS Synchronization Unit

Takes in the output of the GPS antenna and produces a 10MHz carrier signal.

That signal is connected to the MMDS RF master module. The status of the GPS unit is transferred to the front panel LED using the RS 232 cable shown.

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3.1.6

RF Filters.

Figure 14: Front-end RF Filters

Located between MMDS RF modules and antennas. A19 and A18 are the RF filters for master and slave MMDS RF modules respectively.

3.1.7

Power units. These power units provide +5 VDC, +9 VDC, +24VDC and +/- 15VDC to I/O

board. Then I/O board is responsible for distributing power among each module. More details can be found at Figure 1: in [10]

3.1.8

IP Engine. Provides an interface with a 10BaseT Ethernet to store the data collected from DSP into a Secondary device like hard disk. More important at the receiver end than the transmitter end.

Detailed description for IP Engine is provided under the Receiver Unit section.

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3.2 Receiver Hardware Unit

Receiver unit is responsible for demodulating the original baseband signal and sending the digitized version of the received baseband signal for further signal processing. The control signal path and the data signal path of the receiver unit is illustrated in figure ??.

ipEngine

Power Unit

IO Board DSP Mainboard

Reference Signal

ADC Master Control signal path Data signal path Slave RF Modules

GPS Unit

Front-end Filters

Figure 15: Receiver unit block diagram

Like in the transmitter unit, the code written for the DSP should be downloaded using the RS232 serial cable. Then the DSP configures the two RF modules namely master and slave, via the IO Board. Again the master RF module expects a synchronized reference signal of 10 MHz from the GPS unit.

Once the configuration is successful, the received signals which already passed through the frond-end filters are fed to the RF modules. Using the internal local oscillators, they are down-converted to IF stage and then to baseband. Each module produces the two baseband signals like in the transmitter unit, and those are fed to a Analog to Digital Converter (ADC). DSP can read those digitized baseband signals and can be used for further signal processing. If the signal processing has to be taken at the host computer, they can be transferred to the host using the RS232 cable.

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Power Unit ipEngine IO Board

DSP Mainboard

GPS Unit

RF Modules

Figure 16: Snapshot of the receiver unit

Receiver unit is almost similar to the transmitter except for few hardware modules. Those will be discussed in detail here. First the received RF signal is passed through a RF filter and then fed to each RF module. 3.2.1 MMDS RF modules. There are two RF modules namely master (M) and slave (S). Each module takes a RF signal from the receiving antenna. Master RF module takes a 10MHz carrier signal from GPS synchronization unit (using W18B cable) and according to the LO configuration given in the following reference, master shares this carrier signal with the slave RF module. Each MMDS RF module provides an interface to access IF signal. Finally, it produces the appropriate In-phase (I-OUT) and Quad-phase (QOUT) signals (in baseband) for RF signals in each MMDS RF modules. This same signal can be accessed with two different interfaces. (I-OUT 1, I-OUT 2, Q-OUT 1, Q-OUT 2). These demodulated analog baseband signals are then connected to the Analog-toDigital Converter (ADC).

More details on MMDS RF modules can be found in [13] and cable configuration for MMDS RF modules can be found in [14] 24

3.2.2

ADC daughter card.

A4D1 OMNIBUS module provides 4-channel, high-speed (10MHz) 14-bit resolution analog-to-digital conversion facility. Plus a channel for high-speed (10MHz) 14-bit resolution digital-to-analog conversion. Used to digitize In-phase and Quad-phase analog signals from the three MMDS RF modules.

Figure 17: ADC Block Diagram

The A4D1 OMNIBUS module provides the target card processor with four channels of very high speed 10 MHz, 14-bit resolution analog input to digital output conversion (A/D). In addition to a single channel of very high speed 10 MHz, 14- bit resolution digital input to analog output conversion (D/A). This makes it well suited for highspeed data acquisition applications, transient capture, data processing, and control systems. The A4D1 module uses two pairs of Analog Devices AD9240 A/Ds and one AD9774 D/A to provide for excellent dynamic range over a wide input bandwidth.

The A/Ds use a novel four stage pipelined architecture as well as a wideband sampleand-hold amplifier making them well suited for direct IF down conversion extended to 45 MHz. The A/D delivers 10 MHz data from a pipeline, which is only four samples deep, resulting in low data latency. In addition, each A/D channel has gain/offset error adjustment for accurate measurements.

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A one (1) kword FIFO on each channel separates the A/Ds and D/A from the data bus allowing the DSP time for other tasks while the FIFOs are filling or emptying. The FIFOs allow the DSP to collect and transport the data from the A/Ds as single points or as a data set of up to 1K sample size. This reduces the interrupt rate to the host DSP allowing for highly efficient data connection. More details on A4D1 can be found in CH2 of [9]

3.2.3

IP Engine.

Provides an interface with a 10BaseT Ethernet to store the data collected from DSP into a Secondary device like hard disk. The DSP has to be programmed so that it will construct the required Protocol Data Unit (PDU) with the gathered data.

Figure 18: Snapshot of the IP Engine

Control Signals are sent from the DSP to the IP Engine with the help of the cable shown in the following figure. IP Engine is at the left side of the picture.

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Figure 19: Cable connection between DSP & IP Engine

The following diagram shows the functional block of IP Engine. In fact this unit is mounted on the IP Engine Motherboard. So these interfaces are accessible via the connectors available in the motherboard.

Figure 20: Block Diagram of IP Engine

Bright Star Engineerings ipEngine credit-card sized processor module provides an ideal core for a network enabled product. The ipEngine utilizes the Motorola PowerPC MPC823 processor with an array of on-chip peripherals including Ethernet, USB, LCD/Video, I2C and serial controllers. The on-board flash memory file system

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provides storage for the operating system as well as OEM application software and data. The ipEngine has the following significant features: 66 MIPS Power PC CPU 16 MB DRAM 2 MB FLASH 10Base-T Ethernet On-board 16- Watt Power Supply 16,000 Gate FPGA Virtual I/O Interface USB Host/Slave Controller LCD/Video Controller Dual RS-232

The external interface to the ipEngine hardware is via an FPGA-based "virtual interface" which can be configured on the fly to adapt to the OEM's needs. The FPGA can be configured to emulate a variety of bus architectures as well as to implement peripheral functions like UARTs, PWM control, memory emulation, data capture and synthesis, and interfaces to a variety of input devices. The ipEngine provides a firmware boot loader programmed into the flash memory "bootblock" at the factory. The bootloader is used to initialize the ipEngine and load the primary operating system from flash memory, from the network or from the serial console. The ipEngine includes a run-time license for BSE's pKernel real-time network operating system. The ipEngine can also be readily used with other operating systems like VxWorks, Windows CE, PSOS, QNX, eCos or Linux.

When combined with BSEs pKernel software environment, the ipEngine can significantly reduce the time, cost and complexity required to "network enable" a product by providing a vertically integrated "network engine" complete with the required hardware, software, and development environment. By employing POSIX and ANSI C standards, the ipEngine's pKernel software environment leverages a familiar programming environment and facilitates migration of software from UNIX and Windows 95/NT platforms. The pKernel SDK provides an integrated development environment based upon the industry standard GNU tool chain. The

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software developers toolkit includes the gcc cross-compiler, a linker, archive librarian and other utilities. Source level over-the-network debugging of code running on the target system is accomplished via a thread aware version of the GNU GDB debugger.

Using the IP Engine the received data samples are saved in the host PC. Then with the help of a Matlab code, receiver processing is done in order to extract the transmitted digital data.

3.2.4

Time and Sync Card (TAS). Responsible for synchronization at the receiver. TAS card provides signals from two time bases, either 10MHz reference signals time base or sample clock reference signals time base.

Mounted on top of the RF filters at the receiver unit. Currently this card is not used.

More details on TAS card can be found in, C:\Chamath\Documents\Selected Docs\Time_Sync\ Design_Reqs_TAS_2.doc

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4 MIMO Transmission Experiment

In this experiment the MIMO testbed was configured to facilitate the 3-element ESPAR antenna array at the transmitter and the traditional 2-element array of antennas at the receiver.

4.1 Hardware Connections

Following figure illustrates the high level system diagram of the MIMO testbed.

TX

RX

Upload a snapshot

GPS Sync Unit

10 MHz Ref. Signal

PC
Download the code to DSP

Figure 21: High Level System Diagram of the MIMO Testbed

Internal cable connections of TX and RX units are described in [12] and [14]

Both transmitter and receiver units should be supplied with a 10 MHz reference signal with an amplitude of 0-10 dBm. Each Tx and Rx unit has a Trimble Thunderbolt GPS synchronization module which provides this 10 MHz reference signal.

At the moment instead of using the GPS synchronization, two replicas of a 10 MHz tone was generated with the help of the frequency synthesizer available at the transmitter side GPS synchronization module. This was possible as both transmitter

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and the receiver modules are placed physically nearby. Those two synchronized signal outputs are connected to the 10 MHz Ref In channel of the Master RF Module of each transmitter and receiver units.

Master RF Module is responsible for transferring the LO output signal to the slave RF modules. Following figure illustrates the cable connection at the transmitter side RF modules.

Figure 22: LO connections

The MIMO testbed configuration at the receiver is the same as the traditional 2x2 MIMO case. So the transmitter unit configuration is discussed in detail first.

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4.2 Transmitter unit configuration

Just like in the traditional 2x2 MIMO transmission, the BPSK modulated first bit stream is fed to the master RF module in the transmitter unit and its output is transferred to the RF feed in the 3-element ESPAR antenna array. The major modification is that, the second bit stream is not modulated like in traditional 2x2 MIMO transmissions. Instead the bits in the two streams are XORed in each symbol duration and depending on the result, a switching signal is generated at one of the available DAC channels. This procedure is illustrated in figure 23.

Bit Stream

BPSK Modulation XOR

RF Feed

Comparator

Switching Signal

Figure 23: Transmitter side processing

With the DAC specifications, the maximum levels that can be produced are, +2 Volts and -2 Volts. There has to be at least 6 Volts in order to drive the pin diodes in the ESPAR antenna array. So an additional comparator circuit is used at transmitter side to amplify this switching signal produced by the DAC channels to a level which is large enough to drive the pin diodes. The function used for DSP programming can be found at Appendix A.

A schematic diagram of the comparator circuit is shown in figure 24.

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Figure 24: Schematic diagram of the comparator circuit used.

A snapshot of the actual switching circuit setup is shown in figure 25.

Figure 25: Snapshot of the switching circuit setup

The simulated performances of the comparator circuit is shown in figure 26.

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Figure 26: Comparator input and output signal

After implementing the comparator circuit, the DAC output and the comparator output was compared using a oscilloscope. The figure 27 shows that the switching signal conforms to the design specification.

1 S

Comparator Output

DAC Output 5V

Figure 27: Snapshot of the oscilloscope screen for comparator input and output

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4.3 Experiment Specifications

Following are the specification used for the MIMO transmission experiment used for 3-element ESPAR antenna array.

BPSK Modulation Baseband Frequency Baseband signal Training sequence Burst size Switching signal level - 500 kHz - Raised cosine - 8 symbols - 410x2 symbols -8V

V-BLAST with Zero Forcing Equalizer at the receiver

4.4

Downloading a code to the DSP

The C code is written with the help of the Code Composer Studio IDE, and the

output file (xxx.out) is generated. Then Uniterminal application developed by TI is used to download the COFF (xxx.out) file to the DSP using the RS232 serial interface. The Ribbon serial cable is connected to the DSP motherboard as shown in the following figure.

Figure 28: DSP Mainboard

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The code used can be found at [9]. The same code has to be compiled and build with debug variables DSPTX and DSPRX for the transmitter and receiver unit respectively. Setting up the Code Composer Studio, project is explained in [10].

4.5 Transmitter side Interface

Once the transmitter side .out file (readpow.out) is dumped successfully using uniterminal, the screen of the uniterminal should be as follows.

Figure 29: Transmitter side interface

Center frequency can be configured with the option 2. It is configured to be at 2.6 GHz by default. Then option 8 is selected in order to generate a baseband signal at the transmitter.

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Figure 30: Input parameters for baseband signal generation

Parameter C is the baseband frequency in kHz s. N is the no of samples per symbol. A and B are the amplitudes of the baseband symbol for Master and Slave RF modules respectively. Currently in the code the baseband signal level is made to be fixed and as long as the amplitude is not zero and within the range, it generates a baseband signal for that channel with fixed amplitude hard-coded at the vfun.c file. For this experiment, amplitude for both channel A and B has to be given a non zero value. Channel A is used to feed the master RF module and one DAC channel from channel B is used to generate the switching signal. Thats why amplitude for both channels has to be given a non zero value. Otherwise the free DAC channels used for channel B will not be able to use.

RF output power is given at last. If the antennas are much closer, its better to use a less power (with the currently used antennas its about 5 dB) if not received signal should be connected to the receiver unit via an attenuator. Once the input parameters are provided, the summary page would look as figure 30.

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4.6 Receiver side Interface

At the receiver side, after the code downloading completed successfully the uniterminal screen should look as follows.

Figure 31: Receiver side interface snapshot

In order to run the ADC Power Measurement Utility option 5 has to be selected. All the features of the utility are illustrated in the following figure.

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Figure 32: ADC Power measurement utility interface

By pressing S followed by U a snapshot of the received baseband signals can be uploaded to the computer.

A snapshot of the in-phase and quad-phase signals from one of the receiving antenna is shown in figure 33.

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5 S

500 mV

Figure 33: In-phase and quad-phase signals of one of the receiving antenna

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5 Results
The experiment was carried out as described in the chapter 4. The received baseband signals for each antenna is sampled and digitized from the ADC. Those digitized data samples are then transferred to the host computer. Those received data samples are then analyzed using a Matlab code for decomposing. The used matlab code is available at Appendix B.

First the peak of the raised cosine function is detected from the received baseband data.

Figure 34: Peak Detection for further signal processing

The received constellation for each antenna is shown in the following figure.

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Figure 35: Received Constellations at the two antennas

Then the channel is estimated using the 8 training symbols. Once the channel is estimated, the receiver side processing is carried out to decompose the original symbols. The transmitted and estimated symbols are shown in figure 36.

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Figure 36Constellation Diagram for the two sub streams

Finally the Bit Error Rate (BER) is calculated by comparing the bit streams. BER performances are evaluated with different SNR levels. Figure 37 shows a comparison of BER performances with SNR for three scenarios.

Beam Space (BS) MIMO Simulation Traditional MIMO Transmission OTA MIMO Transmission with 3-Element ESPAR

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Figure 37: BER Comparison for the three scenarios

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6 Conclusion and Future Work

Firstly the traditional 2x2 MIMO transmission was verified using the MIMO testbed. Thereafter, 2x2 MIMO transmission with antenna switching was tested and verified with two omni directional antennas placed at the transmitter. Finally a threeelement ESPAR antenna is used at the transmitter and the 2x2 MIMO transmission was validated. The BER performance of over-the-air MIMO transmission using the three-element ESPAR antenna is similar to the traditional 2x2 MIMO and Beam Space MIMO simulation results. So that it can be concluded that, MIMO transmission with three-element ESPAR antenna placed at the transmitter and traditional two elements ULA placed at the receiver is possible. This can make a good impact on the future mobile transmission.

The immediate next step would be to make the testbed work for real-time data processing. So that the received constellation, BER, and other characteristics can be observed dynamically. The testbed can even be used to verify other phenomenon such as transmitter diversity and aerial modulation. Due to the high capacity available for each channel, the testbed can be used for experiments with multimedia communication as well.

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REFERENCES
1. A Novel Approach to MIMO Transmission Using a Single RF Front End , Antonis Kalis, Athanasios G Kanatas and Constantinos B Papadias, IEEE Journal on Selected Areas in Communications, Vol 26, Issue. 6, August 2008, Digital Object Identifier 10.1109/JSAC.2008.080813 2. MIMO Transmission and Reception Techniques Using Three-Element ESPAR Antennas Osama N. Alrabadi, Constantinos B. Papadias, Antonis Kalis, Nicola Marchetti, and Ramjee Prasad. IEEE COMMUNICATIONS LETTERS, VOL. 13, NO. 4, APRIL 2009. Digital Object Identifier 10.1109/LCOMM.2009.082190 3. Foschini, G.J Layered space-time architecture for wireless communication in a fading environment when using multiple antennas, Bell Lab. Tech. J.,vol. 1,N. 2, pp. 4159, 1996 4. Spatial multiplexing by decomposing the far-field of a compact ESPAR antenna, Osama N Alrabadi, Antonis Kalis, Constantinos B Papadias and Athanasios G Kanatas, 19th IEEE International symposium on Personal, Indoor and Mobile Radio Communications, 2008, 1-5 pg, Digital Object Identifier 10.1109/PIMRC.2008.4699495
5. The OMNIBUS Users Manual was prepared by the technical staff of Innovative Integration on October 30, 2002. 6. I/O Board Interface Control Document, Gigabit Wireless September 29, 1999 7. The SBC6x Development Package Manual was prepared by the technical staff of Innovative Integration, April 3, 2002 8. IP Engine Hardware Reference Manual, Bright Star Engineering November 1998 9. Readpow Code composer studio C:\Windows\Desktop\work_ait\work_deliver_tx\readpow\ 10. Build_Option_for_Code_Composer_Studio.pdf C:\chamath\documents\selected documents\ project, at

found

at

11. Transmitter Interface Doc 1.pdf found at C:\Chamath\Documents\Selected Docs\MMDS_radios\ MMDS\Transmitter\ 12. DSO_Tx_Unit_interconnect_2006_10_14.pdf found C:\Chamath\Documents\Selected Docs\MMDS_radios\ MMDS\Transmitter\ 13. Receiver Interface Doc 1.pdf found at C:\Chamath\Documents\Selected Docs\MMDS_radios\ MMDS\Receiver\ 14. DSO_Rx_Unit_interconnect_2006_10_14.pdf found at C:\Chamath\Documents\Selected Docs\MMDS_radios\ MMDS\Receiver\ at

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APPENDIX A
The function used at the transmitter DSP to generate the required baseband and the switching signals.
/* func: uFsOverN * * This utility function will fill an SCOMPLEX buffer with a * sinusoid that has a specified amplitude and period. The * sinusoid will have c periods in n samples (ie, a c/n f-sub-s * sinusoid). * * The value c/n is constrained in the following ways: * c must be < n, and n must be >= 4. * * Also, siglen is required to be an even multiple of n. * * use: * flag=uFsOverN(c,n,sigamp,sigbuf,siglen); * args: * input: c = number of periods in n samples * n = number of samples for an exact number of periods * sigamp = maximum amplitude to apply * sigbuf = buffer to place result * siglen = length of sigbuf // Chamath: ( = PROCSIZE = 2048) * output: sigbuf = this buffer is filled to siglen length. * flag = true if aok, false if error encountered. * */ int uFsOverN (int c, int n, int sigamp, SCOMPLEX* restrict sigbuf, int siglen) { register double angle; register double delta; register int i, b, training, trainingBy2, sampsPERsymb, flag; register SCOMPLEX *sigp; int rcosin[253] = {0,0,0,0,0,1,1,2,2,3,3,4,5,6,7,8,10,11,12,13,15,16,17,18,19,20,21,22, 23,23,23,23,23,22,22,21,19,17,15,13,10,7,4,0,-4,-9,-13,-19,-24,-30,36,-42,-48,-54,-61,-67,-74,-81,-87,-93,-99,-105,-110,-116,-120,-124,127,-130,-132,-133,-134,-133,-131,-129,-125,-120,-114,-106,-98,-88,77,-64,-50,-35,18,0,19,40,62,85,110,135,162,189,218,247,278,309,340,372,405,437,470, 503,536,568,600,632,663,694,723,752,779,806,831,855,877,897,916,933,9 49,962,974,983,990,996,999,1000,999,996,990,983,974,962,949,933,916,8 97,877,855,831,806,779,752,723,694,663,632,600,568,536,503,470,437,40 5,372,340,309,278,247,218,189,162,135,110,85,62,40,19,0,-18,-35,-50,64,-77,-88,-98,-106,-114,-120,-125,-129,-131,-133,-134,-133,-132,130,-127,-124,-120,-116,-110,-105,-99,-93,-87,-81,-74,-67,-61,-54,48,-42,-36,-30,-24,-19,-13,-9,4,0,4,7,10,13,15,17,19,21,22,22,23,23,23,23,23,22,21,20,19,18,17,16,1 5,13,12,11,10,8,7,6,5,4,3,3,2,2,1,1,0,0,0}; int bits[180] = {1,1,0,1,0,0,0,0,0,0,0,0,1,1,0,0,0,1,0,0,1,0,0,0,0,0,1,1,1,0,0,0,1,0, 0,0,1,1,1,0,1,0,1,0,1,0,0,1,1,0,1,1,0,0,0,0,1,1,1,1,1,0,1,1,0,1,1,1,1 ,1,0,0,0,0,1,0,0,0,0,0,0,1,0,0,1,1,0,0,0,0,1,0,1,1,0,0,0,0,0,1,0,0,1, 0,1,1,0,1,0,0,1,1,1,0,0,1,1,0,0,1,0,1,1,1,0,0,0,1,0,1,0,1,0,1,1,1,1,0

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,1,0,0,1,1,0,1,1,1,1,1,1,0,0,1,0,0,0,1,1,1,0,0,1,0,0,1,0,1,1,1,0,1,1, 1,1,1,0,0,1,0,0}; if ((c >= n) || (n < 4) || (n > siglen)) return(false);

sigp=sigbuf; i = siglen / n; if ((i * n) != siglen) return(false); sampsPERsymb = (double)n / (double)c; delta = 253/sampsPERsymb; trainingBy2 = sampsPERsymb*4; training = trainingBy2*2; angle = 0.0; b = 0; flag = 0; for (i=0; i<siglen; i++) { if (sigamp==1) { J1 and J2) // training sequence if (i<training) { sigp->re = 8*rcosin[shortRound(angle)]; sigp->im = 0; } else { // transmit the first bits stream always (from the only available antenna) if (bits[b]==1) { sigp->re = 6*rcosin[shortRound(angle)]; sigp->im = 0; } else { sigp->re = 6*rcosin[shortRound(angle)]; sigp->im = 0;//6*rcosin[shortRound(angle)]; } } } else { J4) if (i<trainingBy2) { sigp->re = 7500; sigp->im = 0; } else if (i<training) { sigp->re = -1*7500; sigp->im = 0; } // for antenna two (for DAC channels, J3 and // for antenna one (for DAC channels,

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// beam switching starts for actual data bits else { if ((bits[179-b]^bits[b])==0) { sigp->re = 7500; sigp->im = 0; } else { sigp->re = -1*7500; sigp->im = 0; } } } angle += delta; if (angle > 255) { angle = 0.0; b++; flag ^= 1; } if (b>179) b=0; sigp++; } return(true); } /*end*/

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APPENDIX B
MATLAB Code used for receiver side processing.
close all A = 1700; % Amplitude of the tx raised cosine T = 2048; % No of samples in a snapshot at the receiver C = 410; % No of symbols in the snapshot, (the freq of the baseband rcosine signal in 500 kHz) L = 8; % L training symbols, so actual no of data symbols is C-L B = 283; % The index of the breaking point. (1-410) check for boundary conditions near 410. (if it is < 400 safe anyway) % Txed random bits pool bits = [1,1,0,1,0,0,0,0,0,0,0,0,1,1,0,0,0,1,0,0,1,0,0,0,0,0,1,1,1,0,0,0,1,0, 0,0,1,1,1,0,1,0,1,0,1,0,0,1,1,0,1,1,0,0,0,0,1,1,1,1,1,0,1,1,0,1,1,1,1 ,1,0,0,0,0,1,0,0,0,0,0,0,1,0,0,1,1,0,0,0,0,1,0,1,1,0,0,0,0,0,1,0,0,1, 0,1,1,0,1,0,0,1,1,1,0,0,1,1,0,0,1,0,1,1,1,0,0,0,1,0,1,0,1,0,1,1,1,1,0 ,1,0,0,1,1,0,1,1,1,1,1,1,0,0,1,0,0,0,1,1,1,0,0,1,0,0,1,0,1,1,1,0,1,1, 1,1,1,0,0,1,0,0]; sample1 = zeros(1,T); sample2 = zeros(1,T); rxSymbol1 = zeros(1,C); rxSymbol2 = zeros(1,C); % Sampling the received signals for k=1:C q = k*5-4; if (q>1410) q=q-2; end sample1(q) = snap11(q); sample2(q) = snap22(q); rxSymbol1(k) = snap11(q); rxSymbol2(k) = snap22(q); end figure(1) subplot(2,1,1) plot(real(snap11)) hold on, stem(real(sample1),'r') title('Real Part of Rx Signal 1 and the Sampled Point for 500kHz') subplot(2,1,2) plot(imag(snap11)) hold on, stem(imag(sample1),'r') title('Imag Part of Rx Signal 1 and the Sampled Point for 500kHz')

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figure(2) subplot(2,1,1) plot(real(snap22)) hold on, stem(real(sample2),'r') title('Real Part of Rx Signal 1 and the Sampled Point for 500kHz') subplot(2,1,2) plot(imag(snap22)) hold on, stem(imag(sample2),'r') title('Imag Part of Rx Signal 1 and the Sampled Point for 500kHz') figure(3) subplot(2,1,1) stem(abs(rxSymbol1)) title('Received Signal 1 Strengh') subplot(2,1,2) stem(abs(rxSymbol2)) title('Received Signal 2 Strengh') %% Channel Estimation % H = Y.X#((X.X#)^-1) % Constructing the training vector X = zeros(2,L); for ii=1:L/2 X(1,ii) = A;%+sqrt(-1)*A; X(2,ii) = 0; end for ii=(L/2+1):L X(1,ii) = 0; X(2,ii) = A;%+sqrt(-1)*A; end Xhash = (X'); % Constructing the received vector for training sequence Y = zeros(2,L); % Rx Antenna 1 Y(1,1:L) = rxSymbol1(B:B+L-1); % Rx Antenna 2 Y(2,1:L) = rxSymbol2(B:B+L-1); H = zeros(2,2); H = Y*Xhash*inv(X*Xhash); % Construct the received data matrix rxData = zeros(2,C-L); rxData(1,1:B-1) = rxSymbol1(1:B-1); rxData(1,B:C-L) = rxSymbol1(B+L:C); rxData(2,1:B-1) = rxSymbol2(1:B-1); rxData(2,B:C-L) = rxSymbol2(B+L:C);

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figure(4) subplot(2,1,1), plot(real(rxData(1,:)), imag(rxData(1,:)),'*'), hold on, plot(A,0,'r*'), hold on, plot(-A, 0, 'r*') axis([-2*A, 2*A, -2*A, 2*A]) title('Constellation Diagram for Rxed signal at Rx1') subplot(2,1,2), plot(real(rxData(2,:)), imag(rxData(2,:)),'*'), hold on, plot(A,0,'r*'), hold on, plot(-A, 0, 'r*') axis([-2*A, 2*A, -2*A, 2*A]) title('Constellation Diagram for Rxed signal at Rx2') % Received SNR Calculation nn=1; oo=1; for mm=1:C-L, if (imag(rxData(1,mm))>100 && real(rxData(1,mm)>90)) snrDATA(1,nn) = rxData(1,mm); nn = nn+1; elseif (imag(rxData(1,mm))<100 && real(rxData(1,mm)<150)) snrDATA(2,oo) = rxData(1,mm); oo = oo+1; end end snr = zeros(1,4); S(1) = abs(mean(snrDATA(1,:)))^2; V(1) = var(snrDATA(1,:)); snr(1) = 10*log10(S(1)/V(1)); S(2) = abs(mean(snrDATA(2,:)))^2; V(2) = var(snrDATA(2,:)); snr(2) = 10*log10(S(2)/V(2)); % snr nn=1; oo=1; for mm=1:C-L, if (rxData(2,mm)>-225) snrDATA(1,nn) = rxData(2,mm); nn = nn+1; else snrDATA(2,oo) = rxData(2,mm); oo = oo+1; end end S(1) = abs(mean(snrDATA(2,:)))^2; V(1) = var(snrDATA(2,:)); snr(3) = 10*log10(S(1)/V(1)); S(2) = abs(mean(snrDATA(2,:)))^2; V(2) = var(snrDATA(2,:)); snr(4) = 10*log10(S(2)/V(2)); snr

%% Decoding the two sub streams % Calculating W

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% W = inv(H$) where, Hnote = (1/sqrt(2))*[H(1,1)+H(1,2) H(1,1)H(1,2); H(2,1)+H(2,2) H(2,1)-H(2,2)] Hnote = (1/sqrt(2))*[H(1,1)+H(1,2) H(1,1)-H(1,2); H(2,1)+H(2,2) H(2,1)-H(2,2)]; W = inv(Hnote); Yhat = zeros(2,C-L); Yhat = W*rxData; figure(5) subplot(2,1,1), plot(real(Yhat(1,:)), imag(Yhat(1,:)),'*'), hold on, plot(A,0,'r*'), hold on, plot(-A, 0, 'r*') axis([-2*A, 2*A, -2*A, 2*A]) title('Constellation Diagram for Substream 1') subplot(2,1,2), plot(real(Yhat(2,:)), imag(Yhat(2,:)),'*'), hold on, plot(A,0,'r*'), hold on, plot(-A, 0, 'r*') axis([-2*A, 2*A, -2*A, 2*A]) title('Constellation Diagram for Substream 2') % Detection decSymb1 decSymb2 decBits1 decBits2 = = = = zeros(1,C-L); zeros(1,C-L); zeros(1,C-L); zeros(1,C-L);

% for Substream 1 for k=1:C-L if (real(Yhat(1,k))>0) decSymb1(k) = A; decBits1(k) = 1; else decSymb1(k) = -A; decBits1(k) = 0; end end % for Substream 2 for k=1:C-L if (real(Yhat(2,k))>0) decSymb2(k) = A; decBits2(k) = 1; else decSymb2(k) = -A; decBits2(k) = 0; end end

%% Compare with the original tx bits % Constructing the Tx Bits vector for BER Calculation txBits = zeros(2,C-L); % for Substream 1 txBits(1,1:52) = bits(129:180); txBits(1,53:232) = bits(1:180);

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txBits(1,233:282) = bits(1:50); txBits(1,283:404) = bits(7:128); % for Substream 2 txBits(2,1:52) = flipud(bits(1:52)')'; txBits(2,53:232) = flipud(bits(1:180)')'; txBits(2,233:282) = flipud(bits(131:180)')'; txBits(2,283:404) = flipud(bits(53:174)')'; modTxBits = (txBits*2-1)*A; figure(6), subplot(2,1,1), stem(modTxBits(1,:)), hold on, stem(decSymb1,'r*') title('Zero Forcing 2x2 MIMO - Txed and Decoded symbols for sub streams 1') subplot(2,1,2), stem(modTxBits(2,:)), hold on, stem(decSymb2,'*r') title('Zero Forcing 2x2 MIMO - Txed and Decoded symbols for sub streams 2') % BER Calculation BER1 = sum(abs(txBits(1,:)-decBits1))/C BER2 = sum(abs(txBits(2,:)-decBits2))/C BER_Tot = (BER1+BER2)/2 SNR = mean(snr)

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