8086 Final Project

Table of Contents
8086 Microprocessor ................................................................................................................................. 3 256KB of CMOS flash memory ................................................................................................................ 3 128KB of SRAM ......................................................................................................................................... 4 8284A Clock Generator ............................................................................................................................. 4 8255 Programmable Peripheral Interface Chips ................................................................................... 4 8259 Programmable Interrupt Controller ................................................................................................ 5 8254 Programmable Interval Timer ......................................................................................................... 5 8279 Programmable Keyboard/Display Interface ................................................................................. 5 16550 UART ............................................................................................................................................... 6 20 Character x 4 Line LCD Display ......................................................................................................... 6 2 Common-Anode 7-Segment LEDs....................................................................................................... 6 8 DIP Switches ........................................................................................................................................... 7 Power Terminal Block ................................................................................................................................ 7 Appendix A: Diagrams ............................................................................................................................... 8 Appendix B: Bill of Materials ................................................................................................................... 25 Appendix C: Verilog Coding of 16L8 Decoders ................................................................................... 27 Appendix D: Group Involvement ............................................................................................................ 30

8086 Microprocessor

The 8086 microprocessor is the central processing unit used to implement this board design. The 8086 is a 16-bit microprocessor that addresses up to 1M-byte of memory. The 8086 operates in minimum mode, thus an input voltage is applied to the MIN/MAX pin on the processor. The CLK, READY, and RESET inputs are received from the 8284A clock device. Last, a push-button switch (with appropriate timing logic) is connected to the NMI input pin. Buffering the 8086: In order to implement the 8086 so that it functions properly with the other memory and/or IO devices on this board, it is necessary to fully buffer the microprocessors shared address and data buses. To obtain the address bus, three 74LS373 (373 for short) transparent latches are used. Since each latch is limited to 8 input pins and 20 address pins are required, three is the minimum number of latches required. The ALE pin enables these three latches. Also, two 8-input 74LS245 octal bidirectional bus buffers are used to obtain the 8086 data bus. The DEN and DT/R output pins control these latches. Last, the M/IO, RD, and WR output signals are allocated off-page connectors where they are passed through a 74LS244 buffer to form the boards control bus. 256KB of CMOS flash memory The CMOS flash is composed of high speed 128K x 8-bit 28F010 CMOS Flash Memory chips, which are decoded into two separate banks from addresses C0000H to FFFFFH. In order to select the proper bank, a 16L8 decoder is used in which the output enables the proper chip. For the 16L8s inputs, the highest 3 address inputs (A17, A18, A19), BHE, and control bus signals are used. If the BHE signal is high (and A17 is logic level 1), the high bank is enabled; otherwise, if A17 is logic level low, the low bank is enabled. Data bits D0-D7 from the data bus are connected to the DQ pins. Additionally, the inputs for the /OE and /WE pins on the 28F010 come directly from the control bus.

128KB of SRAM Four 32K x 8 CY7C199 Static SRAM modules were used to meet this specification. Three 74LS138 decoders are used to control each RAM module and ensure that they are enabled at the correct addresses. When the three most significant address bits are held low and the control bus signals for a memory operation to occur, the memory bank that is enabled depends on BHE (enables the high bank) and A0 (enables the low bank). Two of the four modules connect to high data bus pins (D8:D15) and two of the four modules connect to low data bus pins (D0:D7), thus forming high and low banks. 8284A Clock Generator The 8284A clock generator is an ancillary component to the 8086 microprocessor that provides the basic functions of synchronizing the RESET and READY signals and generating the clock signal with use of a 15 MHz crystal. The RESET subcircuit consists of a push button to operate. Numerous pins are connected to ground, including the RDY1, RDY2, AEN1, AEN2, and CSYNC pins. Since no external clock signal is used, F/C pin is also grounded. The EFI pin is unused and is therefore not connected. 8255 Programmable Peripheral Interface Chips Three 8255 Programmable Peripheral Interface chips are general purpose programmable I/O devices for use with Intel processor. All port connections are pulled to headers for external access. There are a total of nine 8-pin headers, three headers for each chip, accounting for ports A, B, and C. Address pins A1 and A2 are connected pins A0 and A1 on the 8255 chips to select one of the three ports, or the control register. The port connections are as followed: PPI 1: Port addresses FFFF (control register), FFFD, FFFB, FFF9 PPI 2: Port addresses FFFE (control register), FFFC, FFFA, FFF8 PPI 3: Port addresses FFF7 (control register), FFF5, FFF3, FFF1 This circuit includes a 16L8 decoder to select the proper 8255 chip. The equations are as followed: /01 = A0 * /A3 * A4 * A5 * A6 * A7 * * A15 * M/ /IO /02 = /A0 * A3 * A4 * A5 * A6 * A7 * * A15 * M/ /IO /03 = A0 * A3 * A4 * A5 * A6 * A7 * * A15 * M/ /IO For all possible programming modes of the 8255, please refer to the appropriate data sheet for more information. Example code: To set up the ports of the first PPI chip in mode 2 (Bi-Directional Bus) with all ports as input, send the control word 11111111B. MOV AL, 11111111B MOV DX, FFFFH ; set DX to the control register address OUT DX, AL ; send control word to CR address
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8259 Programmable Interrupt Controller The 8259A programmable interrupt controller provides eight (expandable to 64) priority-encoded interrupts to the microprocessor. The interrupt signal IR0 is connected to a push button switch containing all necessary circuits, and IR1, IR2, and IR3 are connected to the 8254 counter 2 output, 8279 IRQ output, and the 16550 INTR output, respectively. 8254 Programmable Interval Timer The 8284 Programmable Interval Timer is a counter/timer device used to solve the common timing control problems found in the 8086 microprocessor. It consists of three independent 16-bit programmable counters in which each counter is capable of counting in either binary or binary-coded decimal (BCD). This device has proven to be useful wherever the microprocessor must control real-time events. In this circuit, the 8254 is decoded at FFDE for the command register, FFDC, FFDA, and FFD8. The OUT0 (counter 1) and OUT2 (counter 3) pins are connected to headers. The OUT1 (counter 2) is connected to IR1 of the 8259 PIC chip. In addition, the gate (G0-G2) and clock (CLK0-CLK2) pins are connected to headers. To select the 8254 chip, a 16l8 decoder is used. The 8245s /RD and /WR pins are directly connected to the appropriate control bus signals. Address bits A1 and A2 are connected to pins A0 and A1, respectively. The equation to select the 8254 chip is as followed: /01 = /A0 * A3 * A4 * /A5 * A6 * A7 * A8 * A9 Example code: To program the 8254 in BCD mode, in mode 0, counter 2, and reading or writing with the least-significant byte only: MOV AL, 10010001b MOV DX, FFDE ; command register address to register DX OUT DX, AL 8279 Programmable Keyboard/Display Interface The 8279 is a general purpose programmable keyboard and display I/O interface device designed for use with the 8086 microprocessor. The 8279 is decoded with a 16L8 decoder at FFF2 for command and FFF0 for data. The chip will be operated in the decoded mode. Twenty push button switches are connected as four rows and five columns. Two switches are connected to the control and shift inputs. Additionally, three extra push buttons are used for reset, the switch that connects to the IR0 input on the 8259, and an NMI key to form the 5x5 keyboard matrix layout. The CLK input to the 8279 is the PCLK signal from the 8284A clock generator. The equation to select the 8279 chip is as followed: /01 = /A0 * /A2 * /A3 * A4 * A5 * A6 * A7 * M/ /IO

16550 UART For serial communication, the system will be using the 16550 UART in combination with the MAX 235 and a DSUB 9 connector. To decode the UART so that it is enabled when within the address range of FFE1 to FFEF, CS1 is connected to VCC, CS2 is connected to A0, and a programmable logic device is used where one of the fixed outputs is activated with the combination A15 * A14 * A13 * A12 *A11 * A10 * A9 * A8 * A7 * A6 * A5 * /A4. The output signals of the UART (/DTR, /RTS, and /TXRDY) get connected to the first three TINs of the MAX 235, which in turn get connected to the DSUB 9 pins respectively. Resort to the DSUB 9 pin layout for the proper matching. The inputs of the DSUB 9 are connected to the RINs of the MAX 235, which then has the ROUTs connect to the respective UART pins (/CTS, /DCD, /DSR, and /RXRDY), again result to DSUB 9 pin layout for proper matching. To address the interrupts from the UART, connect the INT to IR3 of the 8259 interrupt chip. Since we have a clock generator in the system we can use its PCLK signal for the UARTs CLK and not waste space for a crystal. The 8 data pins of the UART are connected to D0- D7 of the microprocessor and /ADS, RD, and WR are grounded. 20 Character x 4 Line LCD Display LCD (liquid crystal displays) with 4 lines by 20 characters per line display that accepts ASCII code as input data. The integrated LCD controller decoded at addresses FFD6, FFD4, FFD2 and FFD0 by connecting the register select at the address bus 1 and 2. In addition, pins 7 through 14 are connected to the data bus 0 through 7. The enable input is used to select a read or write operation and in our design, it is connected to the power. 2 Common-Anode 7-Segment LEDs Two 7-Segment LED displays with decimal points are connected to a 74LS374 latch in which 8 data bits are used to light up each segment and the decimal point on the 7-Segment LED. To enable either LED, a 16L8 decoder is used to decode at addressed FFCE and FFCF, respectively. In addition, the same 16L8, in combination with a 74LS373 latch, causes 8 light-emitting diodes to turn on at address FFCC. The 16L8 decoding addresses are as followed: /O1 = A9 * A8 * A7 * A6 * /A5 * /A4 * A3 * A2 * A1 * /A0 /O2 = A9 * A8 * A7 * A6 * /A5 * /A4 * A3 * A2 * A1 * A0 /O3 = A9 * A8 * A7 * A6 * /A5 * /A4 * A3 * A2 * /A1 * /A0 Example code: To code the 7-segment LEDs to show the number 77: MOV OUT MOV OUT AL, 00000111b FFCE, AL AL, 00000111b FFCF, AL

To turn on the light-emitting diodes: MOV AL, DATA ; DATA is the 8-bit value chosen OUT FFCCH, AL 8 DIP Switches The eight DIP switches control various components of the board. Essentially, when DIP switch is selected, the connected voltage is supplied to that switch (the switch is held high), and when a DIP switch is not selected, the switch is grounded (the switch is held low). As required, the DIP switches are connected to a 74244 that is decoded at the address FFCAH. Decoding of the 74244 is handled externally using a 16L8 decoder with the following logic: /01 = /A0 x A1 x /A2 x A3 x/A4 x /A5 x /A6 x x /A15 Power Terminal Block The power terminal block provides power to the board.

Appendix A: Diagrams

8086 in Minimum mode

256KB of CMOS flash

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128KB SRAM

11

8284A Clock Generator

12

8255

13

8259

14

8254

15

8279

16

16550 UART

17

20 Character x 4 Line LCD Display

18

7-Segment LEDs

19

8 DIP Switches

20

PPI Headers

21

Control/Bus Headers

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Power Terminal

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Schematic of full board

Power Block
Header Header Header Header

8255 PPI

8255 PPI

8255 PPI

16550 UART Conn. D89 LCD

MAX235

16L8 16L8 Control/Bus Headers D C S S A 6 6 S 6 74245 x 2

16L8

74138

CY7C199 SRAM x 4

8086 74373 x 3

16L8

28F010 CMOS x 2

16L8

8254 16L8 Crystal 8284 Clk Generator 74244 8279 Header Keyboard 74138 8 LEDs 74374 16L8 74374
Header Header Header

16L8

8259

Header

74244

7 Segment LED x 2 8 DIP Switches

16L8 x 2

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Appendix B: Bill of Materials

Revised: Wednesday, November 24, 2010 Revision: Bill Of Materials November 24,2010 15:00:14 Page1

Item Quantity Reference Part ______________________________________________ 1 42 CTRL1,C4,C5,C6,C7,C8,C9, C C10,C11,C12,C13,C14,C15, C16,C17,C18,C19,C20,C21, C22,C23,C24,C25,C26,C27, C28,C29,C30,C31,C32,C33, C34,C35,C36,C37,C38,C39, C40,C41,C42,C43,C44 C1,R3,R7,R9,R10,R13,R14, 10k R16 C2,1.0u1 CAPACITOR SW2,D2,SW3,C3,SW4,SW7, SW PUSHBUTTON SW8,SW9,SW10,SW11,SW12, SW13,SW14,SW15,SW16,SW17, SW18,SW19,SW20,SW21,SW22, SW23,SW24,SW25,SW26,SW27, SW28 D1,D3,D9,U38 74LS373 D4 DIODE D5,D7 74LS245 J1,J2,D6,D8,D10,D11,D12, LED D13 J7,J9,J12,J14,J15,J17, HEADER 10 J20,J21,J23 J10 IRQ HEADER J11,J26,J27 HEADER 3 J13 HEADER 2 J16 ADDRESS LOW J18 ADDRESS HIGH J19 DATA LOW J22 DATA HIGH J24,J25 HEADER 1 R1 POT R5 RESISTOR SIP 9 SW1,R6,R8,R11,R12,R15, R R17,R18,R19,R20,R21 R22 CONNECTOR DB9 SW5 Push Button SW6 SW DIP-8 U1 8284A U2 LCD U7 8255 [PP1] U8 8259A U9 8255 [PP2] U11 8255 [PP3] U12,U17,U18,U23,U25,U27, 16L8

2 3 4

8 2 27

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

4 1 2 8 9 1 3 1 1 1 1 1 2 1 1 11 1 1 1 1 1 1 1 1 1 10

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31 32 33 34 35 36 37 38 39 40 41 42

1 2 2 2 1 4 1 4 1 1 1 1

U29,U36,U37,U39 U14 74LS244 U15,U16 28F010 U19,U20 7 Segment LCD U21,U22 74LS374 U24 8279 U26,U33,U34,U35 74LS138 U28 8254 Y2,U30,U31,U32 CY7C199 U40 DM74LS244 U41 PC16550D U42 MAX235 Y5 15 MHz CRYSTAL

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Appendix C: Verilog Coding of 16L8 Decoders 8279: module 8279A16L8(o1, a0, a2, a3, a4, a5, a6, a7, cb0); input = a0, a2, a3, a4, a5, a6, a7, cb0; output = o1; assign o1 = ~(~a0 & ~a2 & ~a3 & a4 & a5 & a6 & a7 & cb0); endmodule 128KB RAM: module 128KBRAM16L7(o1, o2, o3, a17, a18, a19); input a17, a18, a19; output o1, o2, o3; assign o1 = ~a17; assign o2 = ~a18; assign o3 = ~19; endmodule 16550 UART: module 16550UART16L8(o1, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15); input a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15; output o1; assign ~(~a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11 & a12 & a13 & a14 & a15); endmodule LED: module LED16L8(o1, o2, o3, a0, a1, a2, a3, a4, a5, a6, a7, a8, a9); input a0, a1, a2, a3, a4, a5, a6, a7, a8, a9; output o1, o2, o3; o1 = a9 & a8 & a7 & a6 & ~a5 & ~a4 & a3 & a2 & a1 & ~a0; o2 = a9 & a8 & a7 & a6 & ~a5 & ~a4 & a3 & a2 & a1 & a0; o3 = a9 & a8 & a7 & a6 & ~a5 & ~a4 & a3 & a2 & ~a1 & a0; endmodule

CMOS:

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module 28F01016L8(o1, o2, a17, a18, a19, cb0, cb1, cb2, bhe); input a17, a18, a19, cb0, cb1, cb2, bhe; output o1, o2; assign o1 = a19 & a18 & ~a17; assign o2 = a19 & a18 & bhe; endmodule 8284: module 825416L8(o1, a0, a3, a4, a5, a6, a7); input a0, a3, a4, a5, a6, a7; output o1; assign o1 = ~a0 & a3 & a4 & ~a5 & a6 & a7 & a8 & a9; endmodule 8255: module 825516L8(o1, o2, o3, a0, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15); input a0, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15; output o1, o2, o3; assign o1 = a0 & ~a3 & a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11 & a12 & a13 & a14 & a15; assign o2 = ~a0 & a3 & a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11 & a12 & a13 & a14 & a15; assign o3 = a0 & a3 & a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11 & a12 & a13 & a14 & a15; endmodule 8259A: module 8259A16L8(o1, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15); input a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15; output o1; assign o1 = ~(a1 & a2 & a3 & a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11 & a12 & a13 & a14 & a15); endmodule
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DIP Switches: module 8279A16L8(o8, a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15); input a0, a1, a2, a3, a4, a5, a6, a7, a8, a9, a10, a11, a12, a13, a14, a15; output o8; assign 08 = ~(a0 & a1 & a2 & a3 & a4 & a5 & a6 & a7 & a8 & a9 & a10 & a11 & a12 & a13 & a14 & a15); endmodule

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Appendix D: Group Involvement Phase one of the 8086 Final Project was split into separate parts between the four teammates: Patrick Macatangga 8284a CLK 3 8255 chips CMOS 2 common-anode 7-seg LEDs Dominic Gasaway 8279 16550 UART DIP Switches Blanche Mendi LCD display Stuart Reynard 8086 SRAM 8259 8254 Power block Verilog code Each member contributed to the writing of the report and helping each other in creating the schematics of each component of the 8086 microprocessor board.

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