Winter 2011 Debabrata Guchhait.

Roll NoBachelor of Computer Application (BCA) Semester 1 BC0036 Digital Systems 4 Credits (Book ID: B0680)
Assignment Set 1 (60 Marks)

1. Convert the following octal number to decimal

A) 64.24(8) = 6*81+4*80+2*8-1+4*8-2 = 48+4+2*0.125+4*0.015625 = 32+0.25+0.0625 = 32.3125(10) B) 2456(8) = 2*83+4*82+5*81+6*80 = 2*512+4*64+5*8+6*1 = 1024+256+40+6 = 1326(10) C) 0.5675(8) =5*8-1 +6*8-2 +7*8-3 + 5*8-4 =5*0.125+6*0.015625+7*0.001953125+5*0.00024414062 =0.625+0.09375+0.013671875+0.0012207031 =0.71875+0.013916015625 =0.7336425781(10) D) 5624.87(8) = 5*83 +6*82 +2*81 +4*80 +8*8-1 +7*8-2 = 5*512+6*64+4+8*0.125+7*0.015625 =2560+384+1+0.109375 =2945.109375(10)

2. Use Boolean algebra to simplify the logic function and realize the given function and minimized function using discrete gates.

3. Prove that a) a + bc = (a+b) . (a+c) a+bc =a*1+bc =a(1+b)+bc =a*1+ab+bc =a*(1+c)+a*b+b*c =a*1+a*c+a*b+b*c =a*a+a*c+a*b+b*c =a(a+c)+b(a+c) a+b*c=(a+c)(a+b) Alternatively P .T.O

Winter 2011 Debabrata Guchhait. Roll NoBachelor of Computer Application (BCA) Semester 1 BC0036 Digital Systems 4 Credits (Book ID: B0680)
Assignment Set 1 (60 Marks)

(a+c)(a+b) =aa+ab+ac+bc =a+ab+ac+bc =a(1+b)+ac+bc =a*1+ac+bc =a(1+c)+bc =a+bc

b)

5. Describe the operations performed by the following arithmetic circuits. a) Half adder:There are four rules with Binary Addition.

0(2)+0(2)=0(2) 0(2)+1(2)=1(2) 1(2)+0(2)=1(2) 1(2)+1(2)=10(2)

These operation carried by a logical circuit called half adder which accepted two binary digits as its input and produces two binary digits on its output terminals known as sum bit and carry bit. The multiple output function block diagram is shown in trough table to realize the combinational logic is shown in the table. The half adder outputs are given by

Input A 0 0 1 1
P .T.O

B 0 1 0 1

Output Sum 0 1 1 0

Carry 0 0 0 1

Winter 2011 Debabrata Guchhait. Roll NoBachelor of Computer Application (BCA) Semester 1 BC0036 Digital Systems 4 Credits (Book ID: B0680)
Assignment Set 1 (60 Marks)

From these two expression implementation required for a half adder function requires one Ex.OR gate for sum generation and AND gate for carry generation. This logic circuit is shown below

b) Full adder:The full adder three one bit inputs and generates a Sum and a Carry output. Full adder thus accepts one more input for handling carry bits generated during multiple bit addition. Full adder outputs are given by Inputs a b 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Cin 0 1 0 1 0 1 0 1 Outputs Sum Carry 0 0 1 0 1 0 0 1 1 0 0 1 0 1 1 1

P .T.O

Winter 2011 Debabrata Guchhait. Roll NoBachelor of Computer Application (BCA) Semester 1 BC0036 Digital Systems 4 Credits (Book ID: B0680)
Assignment Set 1 (60 Marks)

c) Half Subtractor:Ans:- There are four rules associated while carrying Beanery Subtraction

0(2) -0(2) =0(2) 1(2) -1(2) =0(2) 1(2) -0(2) =1(2) 0(2) -1(2) = invalid there fpre obtain a borrow 1 from MSB and perfom
binary subtraction.

10(2) -1(2) =1(2)

Inputs A B 0 0 0 1 1 0 1 1

Outputs Diff Borrow 0 0 1 1 1 0 0 0

d) Full Subtractor:Ans:- Half subtractor can be used only for single bit subtraction. If there is borrow during the subtraction of LSBs, it affects the subtraction in the next higher bit. A logic circuit which performs the subtraction of the two bits with borrow generated if any, during the previous LSB subtraction is known as full subtractor.

P .T.O

Winter 2011 Debabrata Guchhait. Roll NoBachelor of Computer Application (BCA) Semester 1 BC0036 Digital Systems 4 Credits (Book ID: B0680)
Assignment Set 1 (60 Marks)

Inputs A 0 0 0 0 1 1 1 1

B 0 0 1 1 0 0 1 1

Bin 0 1 0 1 0 1 0 1

Outputs Diff Borrow 0 0 1 1 1 1 0 1 1 0 0 0 0 0 1 1

6. Explain a basic three bit up/down synchronous counter.

Ans:- A synchronous up down counter is one that is capable of counting in either direction through a certain sequence. An up/down counter is also reffered as a bidirectional counter. For example, a three bit binary counter that advance upwards through its sequence 0,1,2,3,4,5,6,7 and then can be revised show that its goes through the sequence in the opposite direction i.e. 7,6,5,4,3,2,1,0. Clock For Up Counting For Down Counting Pulse Up/Down=1 Up/Down=0 QC QB QA QC QB QA 0 0 0 0 1 1 1 1 0 0 1 1 1 0 2 0 1 0 1 0 1 3 0 1 1 1 0 0 4 1 0 0 0 1 1 5 1 0 1 0 1 0 6 1 1 0 0 0 1 7 1 1 1 0 0 0

From the table a closed watch on the output QA indicates for both the UP DOWN sequence so that FFA toggles its state on every clock pluse. Thus J=K=1 for FFA. For the UP sequence, QB changes state on the next clock pluse when QA=1 where as for the DOWN sequence, QB changes state on the next clock pluse when QA=0. Thus the expression for J and K of FFB is J=K=QA, UP+QA.DOWN.

P .T.O

Winter 2011 Debabrata Guchhait. Roll NoBachelor of Computer Application (BCA) Semester 1 BC0036 Digital Systems 4 Credits (Book ID: B0680)
Assignment Set 1 (60 Marks)

For the UP sequence, QC changes state on the next clock pluse when QA=QB=1 where as for the DOWN sequence Qc Changes state on the next clock pluse QA=QB=0. Thus the expression for J and K of FFC is J=K=QA.QB.up+QA.QB.DOWN.

P .T.O