Assignment #4: Digital Controller Design

Date Assigned: April 27, 2009 Date Due: May 13, 2009

An exercise by:

Sven Fagerstrom
sfagerstrom@csufresno.edu

EE 231 Professor Nagy N. Bengiamin, PhD Spring 2009 California State University at Fresno

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design Solve problem 8-18 on page 332. Problem 8-18 as copied from book:

(a) Find the system phase margin with D(z)=1. Analysis begins with function (1.1) as derived from P8-18 where K=1.

GH = ZOH

200 1 0.14 0.07 = ZOH s ( 0.5s + 1) 100 0.5s2 + s

(1.1)

This equation is then digitized with the zero-order hold in the Matlab workspace with the following script (corresponding output follows):
%% Part a n=2*0.07;d=[0.5 1 0]; %define transfer function [nz,dz]=c2dm(n,d,0.1,'zoh'); %digitize transfer funciton with zero-order hold printsys(nz,dz,'z') %graphically print transfer function to workspace

num/den = 0.0013112 z + 0.0012266 -----------------------z^2 - 1.8187 z + 0.81873

(1.2)

The transfer function is then evaluated in the workspace with the bilinear transformation into the w-domain as shown with the following script (corresponding output follows):
[nw,dw]=d2cm(nz,dz,0.1,'tustin'); %bilinear transformation printsys(nw,dw,'w')

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

num/den = -2.324e-005 w^2 - 0.013489 w + 0.27907 -------------------------------------w^2 + 1.9934 w + 1.1065e-014

(1.3)

This function is now evaluated with a bode plot in Matlab with the following script and corresponding Figure 1.1 which follows:
bode(nw,dw);margin(nw,dw);grid %plot transfer function in 'w' showing margin & grid

Bode Diagram Gm = 43.4 dB (at 6.43 rad/sec) , Pm = 85.6 deg (at 0.14 rad/sec) 20 0 Magnitude (dB) Phase (deg) -20 -40 -60 -80 -100 270 225 180 135 90 10
-1

10

10

10

10

10

Frequency (rad/sec)

Fig. 1.1. Robot Arm Digital Frequency Response The phase margin can be seen to be 43.4 dB.

(b) Design a phase-lag controller with the dc gain of 10 that yields a system phase margin of 45o. To design a phase-lag controller in Matlab the transfer function of (1.3) is defined in the workspace as shown with the following script:
%% Part b Gw=tf(nw,dw); %define transfer function to workspace for rltool importation printsys(nw,dw,'w')

The RLTOOL compensator gain is set to 10 as shown in Figure 1.2 along with completed compensator.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

Fig. 1.2. RLTOOL Lag Compe nsator

Phase-lag response is shown in Figure 1.3.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

Open-Loop Bode Editor for Open Loop 1 ( OL1) 60 40 20 0 -20 -40 -60 -80 -100 270 G.M.: 35.1 dB Fr eq: 5.85 rad/sec Stable loop

Magnitude (dB) Phas e (deg)

225

180

135 P.M.: 45 deg Fr eq: 0.409 rad/sec 90 10

-3

10

-2

10

-1

10 10 Frequenc y (rad/sec)

10

10

10

Fig. 1.3. Phase-Lag Controller Response - Bode

It can be seen that the dominant pole is to the right of the zero resulting in a phase-lag configuration as seen in the root locus representation of Figure 1.4.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

x 10

-3

Root Locus Editor f or Open Loop 1 (OL1)

1 Imag Axis

-1

-2

-3

-4

-5

-2

-1.5

-1 Real Axis

-0.5

Fig. 1.4. Phase-Lag Controller Response Root Locus

(c) Design a phase lead controller with the dc gain of 10 that yields a system phase margin of 45o. The added zero of Figure 1.3 is dragged to the left of the pole as shown in Figure 1.5.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

Open-Loop Bode Editor f or Open Loop 1 (OL1) 60

40

20 Magnitude (dB)

-20

-40 G.M.: 19.1 dB Freq: 6.5 rad/sec Stable loop

-60

-80 315

270

Phase (deg)

225

180

135 P.M.: 45.1 deg Freq: 1.75 rad/sec 90 10

-3

10

-2

10

-1

10 10 Frequency (rad/sec)

10

10

10

Fig. 1.5. Phase-Lead Controller Response - Bode

The pole and zero are fine-tuned to provide the desired phase margin of 45 degrees.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

x 10 1.5

-5

Root Locus Editor f or Open Loop 1 (OL1)

0.5

Imag Axis

-0.5

-1

-1.5

-0.12

-0.1

-0.08

-0.06 Real Axis

-0.04

-0.02

Fig. 1.6. Phase-Lead Controller Response Root Locus

The root locus of Figure 1.6 further shows the lead configuration as the pole is to the left of the zero. The resulting compensator is shown in Figure 1.7.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

Fig. 1.7. RLTOOL Lead Compe nsator

(d) If simulation facilities are available, find the step response for the systems of parts (b) and (c), with c(t) = 0.07u(t). Compare the rise times and the percent overshoot for the two systems. The percent overshoot is defined as

Percent Overshoot =

maximum value - final value 100 final value

Lag-Compensator Simulation The lag-compensator simulation begins with defining the compensator function of Figure 1.2 as shown in (1.4.)

C=

10 (1 + 2.5s ) (1 + 11s )

(1.4)

(1.4) is then defined in the Matlab workspace and evaluated with bilinear transformation as shown (corresponding output follows):
nc=[25 10];dc=[11 1]; [ncz dcz]=c2dm(nc,dc,0.1,'tustin'); printsys(ncz,dcz,'z')

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design num/den = 2.3077 z - 2.2172 ----------------z - 0.99095 This transfer function is then implemented in Simulink for simulation as shown in Figure 1.8.
2.3077 z-2 .2172 z-0.99095 0.7 u(t) T=0.1 sec T=0.1 sec. 200 0 .5s2 +s

10

1 /100 Scope

0 .07

Fig. 1.8. Simulink Lag-Compe nsator Simulation Diagram

The response of the step simulation is shown in Figure 1.9.

1.4

X: 6.9 Y: 1.282

1.2

1
X: 3.4 Y: 0.9074

Theta(t)

0.8

0.6

0.4

0.2

10

15

20 t

25

30

35

40

Fig. 1.9. Step Response of Lag-Compensator System The overshoot of the system can be seen to be 28%, rise-time is seen to be 3.4 seconds.

Lead-Compensator Simulation The lead-compensator simulation begins with defining the compensator function of Figure 1.7 as shown in (1.5.)

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

11

C=

10 (1 + 17 s ) (1 + 10 s )

(1.5)

(1.5) is entered into the workspace and evaluated with bilinear transformation as shown in the following script (output follows):
%% Part d lead nc=[170 10];dc=[10 1]; [ncz dcz]=c2dm(nc,dc,0.1,'tustin'); printsys(ncz,dcz,'z')

num/den = 16.9652 z - 16.8657 ------------------z - 0.99005 This transfer function is then implemented in Simulink for simulation as shown in Figure 1.10.

16 .9652 z-16 .8657 z-0.99005 0.07 u(t) T=0.1 sec T=0.1 sec.

200 0.5s2 +s

1/100 Scope

0.07

Fig. 1.10. Simulink Lag-Compe nsator Simulation Diagram

The response of the step simulation is shown in Figure 1.11.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

12

1.4
X: 1.55 Y: 1.225

1.2

1
X: 0.908 Y : 0.9003

Theta(t)

0.8

0.6

0.4

0.2

10 t

15

20

25

Fig. 1.11. Step Response of Lead-Compensator System The overshoot of the system can be seen to be 23%, rise-time is seen to be 0.91 seconds. Both response curves are plotted for comparison in Figure 1.12.

1.4

1.2

0.8

y(t)
0.6 0.4 0.2 0 0

10

15

20 t

25

30

35

40

Fig. 1.12. Lead(Red)/Lag(Blue) Compensator Comparison

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design (e) Write the difference equations required to realize the controllers of (b) and (c). In order to write the difference equations for part (b) the controller of Figure 1.8 is used and converted to delay format as shown in (1.6.)

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C=

2.3077 z 2.2172 2.3077 2.2172 z 1 = z 0.99095 1 0.99095 z 1

(1.6)

(1.6) is then put into signal flow form as shown in Figure 1.13.

Fig. 1.13. Signal Flow Graph for Lag Controller Based on Figure 1.13 the difference equations of (1.7) are derived.

x ( k ) = R ( k 1) + 0.99095 x ( k 1) Y ( k ) = 2.3077 R ( k ) + 0.99095 x ( k ) 2.2172 x ( k )

(1.7)

In order to realize the difference equations for the lead controller, the transfer function of Figure 1.10 is used and developed into delay form as shown in (1.8.)

16.9652 z 16.8657 16.9652 16.8657 z 1 C= = z 0.99005 1 0.99005 z 1

(1.8) is then put into signal flow form as shown in Figure 1.14.

(1.8)

Fig. 1.14. Signal Flow Graph for Lead Controller

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design Based on Figure 1.14 the difference equations of (1.9) are derived.

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x ( k ) = R ( k 1) + 0.99005 x ( k 1) Y ( k ) = 16.9652 R ( k ) + 0.99005 x ( k ) 16.8657 x ( k )

(1.9)

2. For the system of problem 1 above, use the Root Locus method to design a controller such that the overshoot is 10% and the settling time is 1.5 sec. Use the following two methods: (a) Analog design then digitized. (b) Digital design from the beginning. (c) Compare the two designs and the produced controllers. (d) Use Matlab to sketch the Bode plot for the control system of part (b) in the previous problem to determine the phase margin. (a) Analog design then digitized. For analog design, then digitized, a continuous system is defined in the workspace and then imported into RLTOOL for design. If we consider the plant comprising the servo motor and gears, the following Matlab workspace code defines the transfer functions for import for G and H:
% analog then digital clear all; n=2;d=[0.5 1 0]; %define the plant G=tf(n,d); %define plant transfer function F=0.07; %feedback gain H=tf(F); %define feedback tf rltool

After importation of G and H into RLTOOL, a pole and a zero are added to bring the system into an acceptable response range as gain alone will not accomplish the design specifications. The pole is added far to the left so as to not affect system performance. Figure 2.1 shows the root locus editor and finished design.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

15

Root Locus Editor for Open Loop 1 (OL1) 15

10

Imag Axis

-5

-10

-15 -12

-10

-8

-6 Real Axis

-4

-2

Fig. 2.1. Analog Root Locus Plot

Figure 2.2 shows the finished controller step response.

Step Response 16 Sys tem: Closed Loop r to y I/O: r to y Peak amplitude: 15.6 Ov ershoot (%): 9.49 At time (sec): 0.792

14

Sys tem: Clos ed Loop r to y I/O: r to y Settling Time (sec): 1.36

12

10 Amplitude

0.2

0.4

0.6

0.8 Time (sec )

1.2

1.4

1.6

1.8

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design Fig. 2.2. Analog Step Response It is observed that the system operates within specifications with an overshoot of 9.5% and settling time of 1.4 seconds. The compensator is seen under the compensator editor as shown in Figure 2.3.

16

Fig. 2.3. Analog Controller The controller is realized for simulation as shown in the following Matlab script with corresponding transfer function following:
na=[12.6162 38.231];da=[0.083 1]; %analog controller [nz,dz]=c2dm(na,da,0.1,'tustin'); %bilinear transformation to digital printsys(nz,dz,'z')

num/den = 109.2312 z - 80.4861 -------------------z - 0.24812 For later comparison, the system is tested with Simulink with the system shown in Figure 2.4.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

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109 .2312 z-80 .4861 z-0.24812 0.07 u(t) T =0 .1 sec T =0.1 sec.

200 0 .5s2 +s 1/100 Scope

0.07

Fig. 2.4. Simulink Analog to Digital Simulation Diagram Figure 2.5 shows the simulated step response of the system.
1.4
X: 0.65 Y: 1.177

1.2

X: 1.15 Y: 1.03

0.8 y(t) 0.6 0.4 0.2 0 0

0.5

1 t

1.5

2.5

Fig. 2.5. Analog to Digital Controller Step Response Although the design of Figure 2.2 show adequate results, the realization of the system in Simulink as shown in Figure 2.5 are not acceptable with OS=18%. I checked sampling time with the closed-loop transfer function to make sure it was adequate and found the required Nyquist sampling time to be T=0.6, showing that T=0.1 is adequate. I checked the Simulink evaluation step and found it to not affect the response. Further evaluation is required.

(b) Digital design from the beginning. Digital design from the beginning required digitization of the controller as shown in the following Matlab script (corresponding output follows):
%% digital from start n=2;d=[0.5 1 0]; %define the plant Ga=tf(n,d); %define plant transfer function Gd=c2d(Ga,0.1,'zoh'); %convert plant to digital F=0.07; %feedback gain H=tf(F); %define feedback tf Gd rltool

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

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Transfer function: 0.01873 z + 0.01752 ---------------------z^2 - 1.819 z + 0.8187 Sampling time: 0.1 G and H are imported into RLTOOL. A pole and a zero are added as shown in Figure 2.6.
Root Locus Editor for Open Loop 1 (OL1) 1.5

0.5

Imag Axis

-0.5

-1

-1.5 -5

-4

-3

-2 Real A xis

-1

Fig. 2.6. Digital Controller Root Locus Pole, zero, and gain fine-tuned by hand to provide the desired response as shown in Figure 2.7.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

I/O: r to y Peak amplitude: 15.6 Overshoot (%): 9.22 At time (sec): 0.6 16

19

Step Response

14

System: Closed Loop r to y I/O: r to y Settling Time (sec): 1.12

12

10

Amplitude

0.5

1 Time (sec)

1.5

2.5

Fig. 2.7. Analog to Digital Controller Step Response Figure 2.7 reveals overshoot to be 9.2% and settling time to be 1.12 seconds. In order to simulate this controller, the compensator shown in Figure 2.8 is used.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

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Fig. 2.8. Digital Compe nsator Transfer Function

The compensator of Figure 2.8 is realized for simulation as shown in Figure 2.9.

218 .27 z-161 .52 z+0.23 0.07 u(t) T =0.1 sec T=0 .1 sec.

200 0.5s2 +s 1/100 Scope

0.07

Fig. 2.9. Simulink Digital Controller Simulation Diagram The corresponding output step response of the digital controller is shown in Figure 2.10.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

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1.4
X: 0.58 Y: 1.093

1.2

X: 1.04 Y: 1.028

0.8 y(t) 0.6 0.4 0.2 0 0

0.2

0.4

0.6

0.8

1 t

1.2

1.4

1.6

1.8

Fig. 2.10. Simulink Digital Controller Simulation Step Response The simulation reveals a 9.3% overshoot and a 1 second settling time, satisfying design requirements.

(c) Compare the two designs and the produced controllers. Controller comparison reveals the digital controller from the start to have better performance. This is not conclusive however, as the analog to digital controller of part a) did not meet the performance criteria during implementation.

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design

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1.4
X: 0.65 Y: 1.177

1.2

X: 0.58 Y: 1.093

0.8 y(t) 0.6 0.4 0.2 0 0

0.5

1 t

1.5

2.5

Fig. 2.11. Analog/Digital(Blue) & Digital From Start(Red) Comparison The digital controller is acceptable, but the analog overshoot exceeds the maximum of 10%. Further design required as described in section a.

(d) Use Matlab to sketch the Bode plot for the control system of part (b) in the previous problem to determine the phase margin. To create the bode plot in Matlab for the control system of part (b), the controller and plant have to be convoluted. The required transfer functions are defined and convoluted in the workspace as shown (corresponding output follows):
%% Problem 2 last part clear all; n=2*0.07;d=[0.5 1 0]; %GH [nz,dz]=c2dm(n,d,0.1,'zoh'); %digitize GH with ZOH [nw,dw]=d2cm(nz,dz,0.1,'tustin'); %bilinear transform to w domain for analog plot printsys(nw,dw,'w') %confirm w transfer function nc=[25 10];dc=[11 1]; %controller of part b [ncz dcz]=c2dm(nc,dc,0.1,'tustin'); %controller to digital [ncw,dcw]=d2cm(ncz,dcz,0.1,'tustin'); %controller to w domain printsys(ncw,dcw,'w') %confirm w transfer function nt=conv(nw,ncw);dt=conv(dw,dcw); %convolute the signals to combine bode(nt,dt);margin(nt,dt);grid %bode plot to show results

Sven Fagerstrom EE 231 Assignme nt #4 Digital Controller Design num/den = -2.324e-005 w^2 - 0.013489 w + 0.27907 -------------------------------------w^2 + 1.9934 w + 1.1065e-014 num/den = 2.2727 w + 0.90909 -----------------w + 0.090909 The corresponding bode plot is shown in Figure 2.12.

23

Bode Diagram Gm = 34.8 dB (at 5.86 rad/sec) , Pm = 45.6 deg (at 0.42 rad/sec) 100

Magnitude (dB) Phase (deg)

50

-50

-100 270 225 180 135 90 10

-3

10

-2

10

-1

10

10

10

10

10

Frequency (rad/sec)

Fig. 2.12. Frequency Response for Combined Part 1b Controller and Plant

Phase margin of the part (b) control system is 45.6 degrees.