IEEEJOURNAL SOLID-STATE OF CIRCUITS, OL.SC-8, NO.

4, AUGUST 1973 V divergence of the curves in the saturated region isprobably due to inexact modeling of the resistanceof the epitaxialregion between the active transistorand the buried,layer (li?Cl Fig. 1). The in limits of the circuit analysisprogram only permit a one-dimensional modeling of the region as shown in Fig. Z. The effect isnoticeable here since crowding has resulted in one eighth of the active transistorconducting half of the collector current.While thismodeling is not exact over the entire transistor operating range, it does yield useful information tlhat

275

sister Schottky-barrier-diode integrated logic circuit, IEEE J. SolidState Circuits, vol. SC-4, pp. 3-12, Feb. 1969.

[31 A. Y. G. Yu and C. A. Mead, Characteristics of sluminumsilicon Schottky barrier diode, Solid-State Electron., vol. 13,
pp. 97-104, Feb. 1970.

[41 L. Nagel and R. Rohre:,

Computer analysis of nonlinear circuits, excluding radiation ((3ANCER) , ZEEE Y. SotidState Circuits, vol. S(2-6, pp. 166-182,+Aug. 1971. [51 H. K. Gummel and H. C. Pocm, An integral charge control model of bi~olar transistors. Bell Svst. Tech. J.. vol. 49I.. rJD. .. 827-851, M~y/June 1970. Raymond A. Heald (S71) was born in Portland, Ore. He received the B.S. and M.S. degrees in electrical engineering from the University of California, Berkeley, in 1965 and 1972, respectively. He is currently working toward the Ph.D. degree in the area of integrated memories. From 1965 to 1970 he was involved in modeling energy generation and transfer in fission power reactors for the U.S. Navy. Mr. Heald is a member of Tau Beta Pi. David A. Hodges (S59M65) was born in New Jersey on August 25, 1937. He received the B.E.E. degree from Cornell University, Ithaca, N. Y., in 1960, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Berkeley, in 1961 and 1966, respectively. For the academic year 1965 to 1966 he was an Associate in the Electronics Laboratory, Technical University of Denmark. He ioined Bell Tele~hone Laboratories. Inc.. Murray Hill, N. J., in ~966, where he co~ducted exploratory studies on integrated-circuit memory and logic components and on device modeling for computer-aided design, serving finally as Head of the Systems Elements Research Department. Presently, he is Associate Professor of Electrical Engineering and Computer Sciences, University of California, Berkeley. His research interests are in the area of integrated circuits and semiconductor memories. Dr. Hodges is a member of Eta Kappa Nu and Sigma Xi. He was the recipient of Outstanding Paper Awards from the IEEE International Solid-State Circuits Conference in 1963 and 1969. He is currently the Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS.

is very

difficult

if not impossible

to measure

direct] y. IX. CONCLUSIONS This paper shows a method of modeling distributed resistive effects in integrated circuit transistors using arrays or grids of lumped components. From these manylump models, three-lump models are formed that are easily analyzed to determine approximate operating limits, In this way various layouts may be quickly analyzed and evaluated. With this approach, a minimumsize Schottky-clamped transistor layout was developed that has nearly twice the current-handling capacity of the most widely-used minimum-geometry device. The accuracy of the modeling technique was confirmed by comparing results of analysis and experiment for twoclamped integrated circuit transistors. ACKNOWLEDGMENT The authors and assistance. are grateful to L. W. Nagel for advice

REFERENCES
make IC Scene, Electronics, pp. 74-W, July 21, 1969. [2] Y. Tarni, Y. Hayashi, H. Teshima, and T. Sekigawa, [Tran-

[11 R. N. Noyce, R. E. Bohn, and H. T. Chua, Schottky diodes

Distortion BipolarTransistor in Variable-Gain Amplifiers

WILLY M. C. SANSEN AND ROBERT G. MEYER

Absfract-Wide-band variable-gain amplifiers consisting of bipolar junction transistors and exhibiting maximum gain larger than umitv are considered. The mechanisms of distortion are analManuscript received September 6, 1972; revised April 25, 1973. This research was supported by the U. S. Army Research Office, Durham, N. C., under Grant DA-ARO-D31-124-72-G52. W. M. C. Sansen was with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory, University of California,, Berkeley, Calif. 94720. He is now with the Laboratorium Fymca en Electronics van de Halfgelelders, Katholieke Universiteit, Leuven, Belgium. R. G. Meyer is, with the Department of Electrical Engineering and Computer Sciences and the Electronics Research Laboratory,

yzed at low and high frequencies. Approximate expressions for distortion are derived and give good agreement with computational results and measurements. The most common high-performance variable-gain circuit realizations are discussed and compared for distortion performance. 1. INTRODUCTION

ARIABLE-GAIN
grammable

automatic-gain-control

university

of California, Berkeley, Calif. 94720.

of a variable-gain

amplifiers are widely used in (AGC) circuits and proAn important parameter attenuators. circuit is its dynamic range. This is

276 the maximum range of input signal amplitudes that circuit can handle for given limits on noise for small nals ered plifiers able first ance sistor and at distortion of distortion both using low and for large high signals. frequencies. de-coupled Such In this paper subject in variable-gain circuits the sigthe

IEEEJOURNAL SOLID-ST.4TE OF CIRCUITS, UGUST A 1973

is considamsuit-

Considerations variable-gain circuits are form. pairs tranapis high-performfor distortion of the

The specification of one form of clistortion thus determines the other. IJnder low-distortion conditions the power series, given by (2), converges rapidly so that only the second- ancl third-order terms need to be considered. The distortion is then given by In!f2 = *(vBE,/ v,) and In/I, = *(vBED/ VT) in which ~B~~ is the peak value of ~B~. As an example, l-percent IM3 is reached for a peak input voltage of 5,2 mVr~S. Series base and emitter resistances in the transistor linearize the exponential Ic VBE relationship and thus reduce the distortion [5], [61, This corresponds however with a reduction in available gain variation. In the limit of very high series resistance, the transistor is current driven and gain variation is possible only as far as current gain /3 clepends on collector current la. The distortion given by (5) is then negligible with respect to distortion caused by this 10 dependence of ~. The large values of even-order distortion in the single transistor can be balanced out by applying the input signal vi between the bases of a matched pair [Fig. 1 (a)], Varying the common-emitter current IB changes the gain. Signal output current icz is given by
?& = IE

are restricted

to wide-band bipolar in single Using

transistors. in monolithic transistors these

(5)

for realization considered. integrated quads

integrated three

Distortion

and differential circuits incorporated selection optimization

results and

gain-control

are analyzed
This work for chosen

compared the the distortion

performance. propriate in any performance given

allows best and

configuration application of the

performance of the

circuit.

11. GAIN CONTROL IN A SINGLE TRANSISTOR AND A BASE-DRIVEN EAIR In a bipolar pends transistor the at-collector current i. de-

on the ac baseemitter tial relationship of the form

voltage

vB~ by an exponen-

IQ + ic = IC~ exp in which IQ I CS

(v;=)

(1)

the dc collector

current, and

the collector-saturation current,

v ,E
V,

the dc baseemitter voltage, = lcT/q * 26 mV at 302 K.

1 +

exp (v,/ VT) ~)

(6)

For small v,. the exponential can be expanded and after rearrangement (1) becomes

in v,.

if /3 >> 1. Under low-distortion panded in v{ and becomes ic2 = *g.vt[l

conditions

(6) can be ex-

+(vi/vT)2

. . .] term

(7) is zero. @)

c=g~,~[+itt)+it%)+ J 2)
The first-order coefficient g. is given by (3) 9rn = IQ/vT, where g,. is the small-signal transconductance of the transistor. Consequently, gain can be varied by changing IQ. The higher order terms in (2) are due to the exponential nonlinearity and give rise to signal distortion. Common measures of this distortion are intermodulation (IM) and harmonic distortion (HD). IM distortion is defined for two-sinusoidal input signals at frequencies 01 and oz applied to a circuit. Second-order intermodulation (IMZ) is defined as the ratio of the amplitude of the output distortion product at frequency 01 * Wzto the fundamental signal. This arises from the square term in the power series expansion. Third-order intermodulation (IM~) is similarly defined for distortion at 2~z * ~1 and 2til * w2 and arises from the cubic term in the power series. At low frequencies, IM2 and IMS are related to secondharmonic distortion (HDZ) and third-harmonic distortion (HD,) by [4] IM, IM, = 2.HD, = 3.HD8. (4)

in which gn = IE/Vy. The The third-order term yields IM,

second-order

= &(v,p/V,)2

in which v,, is the peak value of v,. In this case l-percent IM, is reached at 7.4-mV,~, input signal that is @ times higher than for a single transistor. In practice, small mismatches between transistors cause some second-order distortion. However, since collector currents ic, and icz have an opposite phase, a differential output [Fig. 1(a)] can be taken that significantly improves the rejection of even-order distortion. As for a single transistor, the presence of base and emitter resistance linearizes the transfer characteristic so that the available gain variation is exchanged for distortion reduction. The base-driven pair is thus able to suppress evenorder distortion but decreases the odd-order distortion by a factor of only 1,4 compared with a single transistor. A significant improvement in distortion performance can be obtained by applying the signal input as a current via the current source of the differential pair. III. THE EMITTER-DRIVEN PAIR

Interchanging the positions of input signal and gain control in the pair of Fig. 1 (a) results in the emitter-

SANSENAND MEYER: BIPOLAR TRANSISTOR MPLIFIERS A

277
drops across the base resistances are different.liminaE tion of 101 in (10) gives an expressionfor {C2.This nonlinearequation is solved point by point for a sinusoidal input and a Fourier analysisistaken of the output waveform. The ?M2 and IM3 products are plottedversus relative signal attenuation in Fig. 2. Note that the secondorder distortion again present due to the unbalancing is of the differentialair. Maximum p current gain (0-dB attenuation) is achieved for high negative VB. Almost

vcc

Vi f

J-vEE

(0)

-IEE
Fig. 1. (a) Base-driven

~ 4
IE(l+i)

11
(b)
variable-gain pair.

all the current then flows in transistor Q2 [Fig, 1 (b)], which thus acts as a current-driven common-base stage. As a result there is no distortion (it is assumed throughout that ~ is approximately independent of current). This is also seen from (10).lcl is then negligible the first in equation and thus Icz is linear in i. When both transistors carry the same current the exponential in (10] equals unity. Voltage VB is zero, Currents ICI and IOz, are equal and again linear in i. There is thus no distortion at an attenuation of 6 dB. For high attenuation nearly all the current flows in transistor Ql. Voltage l~ is both positive and large compared with Vr. Since current 10Z is small, elimination of ICI in (10) gives

Ic, = a,l~(l
in which

+ i) exp (b

+ Y,) exp (rIi)

(11)

and (b) emitter-driven

driven pair shown in Fig. 1 (b).Input currentZE(l + i), in which i represents the fractionalsignal level,feeds both transistors parallel. in DC voltage VB determines
l-

t-m

the fractionof the input current that flows in the second transistorand develops output voltage VO. At low frequencies the signal output current iG2 is readily found from (6) for B >>1 and no seriesemitter resistance and isgiven by t& = IX 1 +

The ac voltage drop across the base resistance of the current-carrying transistor represented by exp (~li) in (11), thus causes distortion in the attenuated output current. This distortion is found by expanding exp (~li) in a power series in (rli) and is given by 1 + ?,/2 IM2 = r,in l+r, 1 + rJ3 IM, = ~(?,i=) --(12a)

:Xp (b)

(9)

in which b = VB/V~. Since (9) is linear in i, no distortion clccurs so that the emitter-driven pair is far superior to the base-driven pair. However the input signal must be available as a current. The required voltage-current conversion implies a tradeoff between circuit gain and distortion as will be illustrated in the circuit realizations of Section IV. Thus the distortion actually present in io2 is never zero but can be made very low at the expense of circuit gain. Whereas the presence of base and emitter resistance imprcwes the distortion performance of the base-driven pair, it has a deteriorating effect for the emitter-driven pair. Inclusion of base resistances r~l and rB2 in the transistors of Fig. 1 (b) gives the circuit equations

(12b)

L(1 )+ I 4+2= +; lE(li)

*=

=P[++*-*)]

in which iP is the peak value of i. The values given by (12a) and (12b) constitute an upper limit for the distortion. They agree very well with the ones obtained by exact calculations (Fig. 2). Experiments have been performed on a matched pair of transistors (CA 3018). Base resistance was determined by means of the circle diagram and phase cancellation methods [7]. A single transistor with large emitter resistance was used as a current source. The distortion associated with the current source was thus negligible compared with the distortion generated in the pair itself. HD and IM distortion have been measured at low frequencies. Their ratio was in very close agreement with the relations given in (4) provided the distortion was low. The experimental results are given in Fig. 2. IV. PRACmCAL ~EALIzAT1ONs The excellent properties realized in two commonly of an emitter-driven pair are known transistor quads: t+e

in which lC1 and 1a2 represent total collectorcurrents. The second equation of (1(l)is nonlinear if the voltage

278
Distortion (dB)

IEEEJOURNAL SOLID-ST.4TE OF CIRCUITS, UGUST A 1973

-40
~

(1M3) -20 1

6
m u c ; 20

z w 5

40

4 h 6Q60 -40 -20

(IM2) o

i? -vEE
Fig. 3. Variable-gain quad based on signal summation amplifier). (AGC

Fig. 2. Low-frequency IM, and IM, distortion for the emitterdriven pair for C,A 3018 with r, = 0.385 and i. == 0.25 ;computed; --- approximated (12); o measured.

AGC amplifier [1] represented in Fig.3 and the multiplier [3] shown in Fig. 4. The use of a balanced quad arrangement results in cancellation of the second-order distortion of the emitter-driven differential pair discussed previously. Both circuitis employ a base-driven pair with emitter degeneration as a differential current source. Thedistortion of the input current with no feedbacks thus given by (8). At low-frequencies feedback caused by emitter resistance RE however reduces this to IA!I,, = a 1 + (.RJEJ2 (13)

kc

V,)

if the signal output current has the same amplitude as without feedback [8]. Arbitrarily increasing RE thus decreases the distortion but also the maximum current gain, which is given by

-tEE
(14) Consequentlyj a tradeoff has to be made in the choice of emitter resistance RE. The AGC quad shown in Fig. 3 is formed by balancing two emitter-driven pairs. Even-order distortion is thus absent for perfectly matched transistors. Odd-order components however add. The IM3 distortion versus attenuation is thus as given in Fig. 2 and the maximum value is given again by ( 12b). The AGC quad using the multiplier configuration is shown in Fig. 4. For zero input voltage VD, all collector currents are equal and the signal output V.. is zero. For negative VD the attenuated ac collector currents ic2 and ic3 become highly distorted but are negligible in magnitude with respect to the increasing ac collector currents icl and ic4. Thus the amount of third-order distortion at low frequencies is similar to that in Fig. 2 for attenuation between 6 and O dB, but now expanded over the whole attenuation range of the multiplier. However, as
Fig. 4. Variable-gain quad based on signal subtraction plier). (multi-

attenuation increases, the fractional third-order distortion approaches a constant value because the fundamental and the third-order component itself both decrease at the same rate. This is true only if the transistors are perfectly matched. The IM3 distortion is computed from (10) and plotted versus attenuation in Fig. 5. The constant amount of distortion at high attenuation is obtained by expanding (10) for very small b and is found to be about 10 dB lower than the maximum distortion of the AGC amplifier (Fig. 2) given by ( 12b). Even-order distortion is canceled if perfect matching is achieved. The multiplier has thus actually a better distortion performance than the so-called AGC amplifier itself. However, if the multiplier is not fully compensated [3] for mismatches, the third-order component cancels at a different value of VB than does the fundamental. This results in an infinite value for IM3 at an attenuation level

SANSENAND MEYER: BIPOLAR TR.4NSISTOR MPLIFIERS A IM3

Distortion (dB)

279

o .(CQ 0 .-

-80

-60

-40 *

-20

)
0

40I

1
o

VB

negotive

/ o

00

-1 1

~t
1

I I -vEE
Fig, 5. Low-frequency IM~ distortion for multiplier using CA 3045 with r, D 0.35 and ip n 0,5; computed for matched transistors; o measured. Fig. 6, Vo.riable-gain quad based quad). on prechstortion - (Gilberts

IM3 Distortion ( dB)

determined by the degree of mismatch. This isillustrated
~60

built with four-matched transistors (CA 3045). Base resistance is added to make distortion measurement easier. Mismatch is such that for positive VB the third-order component is zero but not the fundamental, The waveform is thus distortionless at an attenuation of about 30 dB (Fig. 5). For negative VB however, the fundamental cancels but nok the third-order component. The fractional distortion thus increases with a slope of 20 dB/decade. It can thus be concluded that a multiplier has superior distortion performance compared with the AGC amplifier provided full four-potentiometer compensation [3] is applied. V, VARIABLE-GAIN QUAD BASED ON PREDISTORmON The gain variation in the AGC amplifier and the multiplier are based on unbalancing a differential pair. Evenorder distortion is canceled by taking a differential output of two pairs. A different variable-gain quad is based on Gilberts wide-band amplifier technique [2]. In this case, a single-ended output ideally does not contain second-order distortion. The quad is shown in Fig. 6. The input signal is converted into a current and predisto~%ed by the transistors Q1 in order to cancel the distortion generated in the base-driven pair of transistors Q2. The same predistortion concept is applied in highperfo.rmance multipliers [3]. The gain is controlled by the ratio of pair currents I,w and 1E2. Howetier, distortion is absent only if [2] 71-? 2=0 (15)

in Fig. 5 for a multiplier

-40

-20

z -20 0 6 .= . : =
a

00 0 .

40

Fig. 7. IM, distortion versus attenuation for Gilbert?s quad (Fig. 6) using CA 3045; r,,, ~,.~ n 0.35 and i. D 0.5; computed; -- approximated at low (16) and high (25) frequencies; o measured at low frequencies; A measured at high frequencies for B~,~.,,. = 4; B = 4 corresponds to a frequency of 48 MHz.

pansion, by

the third-order

distortion

can be approximated

in which rl and Vz are defined as in (11) for the first and second pair, respectively. Condition (15) is fulfilled for only one gain value, and distortion occurs for lower and higher gains. At low frequencies this distortion is found from the nonlinear equation describing the quad [3] using the methods described in Section III, and is plotted versus attenuation in Fig. 7. Using-. a Dower series ex-

in which ~ is the fractional current swing in transistors Qz. Ideally, no second-order distortion is present, even from a single-ended output. Residual second-order distortion, due to device imbalances can be further reduced by taking a differential output (Fig. 6). The results given by (16) and the measured data are plotted also in Fig. 7. The null in distortion is measured at a lower gain than predicted. This is caused by some residual distortion present in the current source that adds on one side of the null and subtracts on the other side [4]. For a given operating current, the maximum amount of distortion given by (16) is larger than the maximum distortion in the AGC amplifier, which is given in ( 12b). The distortion null however, is less shar~ and thus Gilberts vari-

---

mu

IEEEJOURNAL SOLID-STATE OF cIRCUITS,AUGUST 1973

able-gain quad is quite attractive for a limited tion range around the null in distortion. VI. HIGH-FREQUENCY
ANALYSIS

attenuao 6 : 20 E z z . z 40
-80 -60

Dlstortlon

dB )

-40

(H03) -;

The previous analysis was restricted to low frequencies where charge storage is unimportant. Corisider now the situation at high frequencies. The distortion in the emitter-driven pair [Fig. 1 (b)] is analyzed first. Then a comparison is made of the distortion performance of the AGC amplifier (Fig. 3), the multiplier (Fig. 4), and Gilberts quad (Fig. 6). For the emitter-driven pair, initially, assume that the device ~~ is constant (i.e., 10 is not low) and that the frequencies are high enough that recombination current is negligible. Then
I. = r(dI./dt) eXp (V, E/V,),

H03

I 1 / I I I -30 I
(HDZ)

00

. I -50 I

(17a) (17b)

6Q70

~C = I..

where 13, lc, and V~E are total values for base current, collector current, and base-emitter voltage, respectively; 7 is the base transit time. The circuit equations are then given by

Fig. 8. High-frequency HD, and HD, distortion for the emitterdriven pair using CA 3018;, B = 4 (60 MHz) and i, = 0.25; computed; --- approximated (24; o measured.

&

[~E exp

( b)] I(BJo. i [II

&)oi2 +

+ II,(B,,

H,(B,,

B,B,)o.

i3 +

. . .]

(22)

in which lli (Bl, . Bt) are the ith order Volterra kernels operating on input signal i. They are found by substituting (21 ) and (22) in ( 18b) and they are given by Equation (18a) shows that off at their common base about both collector currents roll cutoff frequency, which is jB1l+~ (19)
H,(B,, BJ

f. = l/27rT.

= (1 + j7B,)(l

( )

+ iYBz)

Equation ( 18b) describes the nonlinearity. As for low frequencies, this is caused by the difference in voltage drop across the base resistances. These voltage drops are now time differentials so that the distortion is frequency dependent. Eliminating Icl in (18a) and ( 18b) gives a nonlinear differential equation of the first order, This equation has been solved directly by computer aids and a Fourier analysis has been taken of the output waveform, The amount of distortion at one specific frequency is plotted in Fig. 8. Frequency is normalized as given by

The HD components [which at high frequencies are not necessarily related to the IM products by a constant ratio as given by (4) ] are derived from (23) and given by

D ?~T2B2)2 = ------(ww 24a) +

HD, = ~. 8 , l+TB ~ (%92)2 24b)

HD as predicted by the previous equation is plotted versus frequency in Fig. 9 and as asymptotes in Fig. 8. Experimental results are also shown in Fig,s. 8 and 9. Agreement is satisfactory. However, at high-attenuation maximum value can be predicted by an analyticalexlevels, deviations occur as can be seen in Fig. 8. Also pressionderived as follows. available attenuation is limited. Both In (18a) and (18b) 1C2 isneglectedwith respectto 10I. the maximum effects are caused by direct signal feedthrough via the The ac part of lCI is then found from (18a) and given junction capacitances CjE1 and Cjcz of output transistor in the frequency domain by Q2 [Fig. 1 (b)]. For high attenuation, emitter voltage vi is determined entirely by the common-base input im(21) pedance of transistor Q1. This voltage is highly disin which y = V~/YBIIn and thus yB = COT1 or f/jT. The ac torted because of the exponential 10 V~E relationship. part of collector current Z& can then be represented by a Also the magnitude of v, increases with frequency due Volterra series of the form [9] to the presence of the base resistance [7]. The output As for low frequencies, distortion due to the presence of
base resistance zero at fullgain and at half that gain. is For high attenuation, distortion becomes maximum. This

SANSENANDMEYER: BIPOLAR TRANSISTOR MPLIFIERS A

Frequency B

281 has a better than at distortion direct AGC emitters in the the performance feedthrough amplifier. of transistors than The the AGC quad voltage (Fig. 6)

amplifier.
OOF-

However,

in Gilberts signal QI

is worse developed

is applied directly of transistors Qz. VII.

to the

junction

capacitances

Cjcz

THE INFLUENCE OF NONIDEAL CURRENT SOWRCES

Fig. 9. Maximum HD, and HD, distortion versus frequency for the emitte,r-driven pair; i, n 0.25 and ~ H 0.00; computed; --- approximated (24); O meamu-ed, cjE2

A current source is nonideal when it is shunted by a finite resistance or by capacitance. Presence of shunt resistance Rg at the commonemitter points of the AGC circuits in Figs. 3 and 4 or at the emitters of transistors QI in Gilberts quad in Fig. 6 introduces distortion that subtracts from the distortion obtained for high attenuation. At low frequencies and for high attenuation it is found by power series expansion and given by (26)

Cjc2

fi t ?

r-r--l

I
RL

+
V.

Fig. 10. Model of output transistor Q, with collector l~ad R. at high attenuation; v, is the emitter voltage and v, the collector voltage.

transistor with collector load RL is nearly cutoff and can thus be simulated by a second-order high-pass filter shown in Fig. 10. Output signal V. is thus even more distorted than v;. Also its amplitude increases with frequency. Although other parasitic capacitances such as collector substrate capacitance are present the model of Fig. 10 has yielded values of maximum available attenuation that are in good agreement with experimental data. As for low frequencies the HDa curve shown in Fig. 8 for the emitter-driven pair applies directly for the AGC amplifier (Fig. 4). The HDZ is reduced by taking a differential output and has usually become smaller than HDS. In the multiplier (Fig. 4) full compensation at high frequencies is not feasible and the attenuation range for a given distortion level is quite limited. The multiplier is thus not very attractive as an AGC circuit at high frequencies. The distortion at high frequencies in Gilberts variable-gain quad is obtained by means of a Volterra series expansion using the model described by (17). The distortion is given approximately by

(for Gilberts quad take X~E = 2 1~1). This amount of distortion is usually small enough to be neglected unless the current sources are replaced by resistors. At high frequencies, constant capacitances at the emitters of the quad, such as collector-substrate capacitance Cc~ and emitterbase junction capacitance cjE1 become important. They can be modeled by assuming a current dependent base-transit time , for the quad transistors. Expression (17a) becomes then

~. (~+g@c. )
B

IC

dt

(27) in

The ac component of base current i~ can be expanded ic, the ac part of Ic, as given by

with 2CC VT TO = ~+. I EE 4C, ov* TI = r

I EE 72 =

8CC . VT2
IEE

and Cc = 2~jB + Ccs for one pair. In a first-order analysis Cjn is voltage independent and thus the same for both transistors of the pair under any attenuation level. Base resistance is neglected also. The distortion is then (25) HD, = (iP2/8) (1?, B,) found in the collector current of one emitter-driven in which B1 and B2 are defined as in (20) for transistors transistor. Using a Volterra series approximation the QI and Q,, respectively. Computed, predicted, and meadistortion is given by sured results are represented in Fig. 7. Agreement is satisfactory. (29) The maximum distortion at high frequencies in Gilfor small Cc and frequencies below f~/3. As for low berts variable-gain quad increases only linearly with frequencies this distortion subtracts from the distortion frequency whereas in the AGC amplifier (Fig. 4) the level obtained for high attenuation. Omission of (26) maximum distortion, given by (24b) increases twice as and (29) leads thus to worst case analysis. fast. For high frequencies (Bl~z ~,x > 1) Gilberts quad

282 VIII. CONCLUSION

IEEE JOURNAL SOLID-STATE OF CIRCUITS, UGUST A 1973 transistors, IEEE J. Solid-State Circuits, vol. SC-7, pp. 492498, Dec. 1972, London: Pitman, [81 A. T. Starr, Radio and Radar Technique. 19.53, p. 416. [91 S. Narayanan, Transistor distortion analysis using Volterra series remesentation, Bell. Swst. Tech. J,, vol. 46, ,.. W. 9911024, M~y/June 1967.

Distortion in wide-band transistor variable-gain amplifiers has been analyzed at both low and high frelevels all circuits conquencies. At high-attenuation sidered here approach constant distortion values that are given by simple analytic expressions. Experimental results show good agreement with these calculations. Three high-performance variable-gain amplifier configurations are identified and compared. The AGC amplifier covers the widest attenuation range at both low and high frequencies. However, at high attenuation its distortion is relatively high. A multiplier used as a variable-gain amplifier exhibits less distortion but needs full compensation for offset in order to obtain the same attenuation range as in an AGC amplifier. This is not feasible however at high frequencies. Gilberts quad gives higher distortion than both the previous circuits at both high- and low-attenuation levels. At high frequencies the distortion is lower than in both other amplifiers but the attenuation level is severely limited by feedthrough. REFERENCES [11 W. R. Davis and J. E. Solomon, (A high-performance monolithic IF amplifier incorporating electronic gain control, {~6E~ J. Solid-State Circuits, vol. SC-3, pp. 408-416, Dec.
[21 B. Gilbert, [31 [41

Winy M. C. Sansen (S65M72) was born in Poperinge, Belgium, on May 16, 1943. He received the E1.-Mech. Eng. degree in electronics from the Katholieke Uuiversiteit, Leuven, Belgium, in 1967 and the Ph.D. degree from the University of California, Berkeley, in 1972. In 1968 he was employed as an Assistant at the Katholieke Universiteit. In 1971 he was employed as a Teaching Fellow at the University of California. In 1972 he was

appointed by the National Fund for Scientific Research in Belgium to conduct research at the Laboratorium van de Fysica en Elektronica van de Halfgeleiders, Katholieke Universiteit. His interests are in device modeling and in distortion and noise limitations in
integrated circuits. Mr. Sansen is a member of the Koninklijke Waamse Ingenieurs Vereniging (Belgium) and Sigma Xi. In September 1969 he received a CRB Fellowship from the Belgian American Educational Foundation and in 1970 a G.T.E. Fellowship.

[51

[61

[71

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Correspondence
Grounded Analysis Load Complementary FET Circuits: Sceptre
area might be achieved by employing grounded load devices in portions of a system employing large-scale integrated CMOS circuits. INTRODUCTION The performance characteristics of complementary MOS (CMOS) circuits [1], [2] with the gate of the load device grounded have been evaluated and compared with other type of AbstracfThe performance of grounded load complementary MOS circuits. The grounded load complementary MOS (GLCMOS) (CMOS) circuits has been evaluated. It has been found that a very inverter circuit is shown in Fig. 1 (a). The GLCMOS circuit significant improvement in performance and reduction in circuit has smaller propagation delay, requires only n + 1 devices per logic function rather than 2n devices as in CMOS circuits, Manuscript received February 2,1973. ~~ork supported This ~va,s inpart bythe and occupies much less area. At high frequencies, CMOS cirComputing Ce~ter the a,t University of Ark~~sa,s. of Electrical Engineering, U~i~~rsit~ cuits dissipate as much power as the GLCMOS circuits. of Theauthors with the Department ~~e Arkan~~~, Fayetteville, Ark. 72701. If large-scale integrated CMOS circuits are used in a system,

HIROO SAKAMOTO AND LEONARD

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