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Tng qut: ADXL: 13 bit, c th o dc gia tc trong phm vi +- 16g. D liu s u ra c nh dng 16bit v c th c truy cp thng qua giao din SPI( 3hoc 4 dy) hoc I2C. ADXL ng dng o gia tc trng trng tnh trong cc ng dng cm bin nghing cng nh o gia tc ng hc ca cc qu trnh chuyn ng, rung( phn gii cao: 3.9mg/LSB => c th o ngay c khi nging thay i t hn 1.) C nhiu khi chc nng cm bin: Cm bin s hot ng (hay khng hot ng): So snh gia tc trn 1 trc bt k vi gi tr ngng t ca ngi sdng. Cm bin s ri t do ca thit b. Dng cho 2 ngt ngoi.

Thng s c bn: nh mc: 23uA; 2.5 V phn gii: Mc nh: 10bit C th ti 13bit khi a=+-16g Ngun cung cp: 2-3.6V I/O: 1,7V Phm vi nhit : -48 n 85 c. ng dng: thit b y t chi game thit b cng nghip bo v cng(shock) thng s k thut: phi tuyn: +_ 0.5 % full scale Chn: Reserved: b ng hoc ni vi Vs. NC: khng kt ni ni b Nguyn l lm vic: s dng cc t in, mi t gm 1 tm c nh v 1 tm c gn vi 1 khi lng dch chuyn. gia tc s lm lch phn khi lng v lm mt cn bng cc t khc. Kt qu l xut hin 1 tn hiu ra c bin t l vi gia tc. nhy pha dng xc nh ln v du ca gia tc. Truyn thng ni tip: Chun I2C: chn CS treo cao vi V I/O 2 dy Chn Alt address ni vi VI/O hoc ni t. Chun SPI: chn CS c iu khin bi VXL ngoi 3 dy: ngc li chn.

 4 dy: xa bit SPI( bit d6- address: 0x31) Ngt: 2 chn int c tch cc cao. thay i (tch cc thp): set bit int_invert trong thanh ghi data_format (address: 0x31) Ngt c cho php khi setbit thch hp trong thanh ghi int_enable (0x2E) v truyn n int1 hoc int2 da vo ni dung ca thang ghi int_map(0x2F). C th theo di cc ngt trong thanh ghi int_source Cc loi ngt: Ngt hot ng: set bi thanh ghi ACT_INACT_CTL khi gia tc ln hn gi tr lu gi trong thanh ghi THRESH_ACT trn bt k trc tham gia no. Ngt khng hot ng: ngc li, vi gia tc nh hn nhng trong thi gian di hn thi gian quy nh trong thanh ghi TIME_INACT Ngt ri t do: tng t ngt k h, khc ch tt c cc trc u tham gia, chu k ngn hn Ngt single tap: khi 1 gia tc (c gi tr ln hn gi tr quy nh trong thanh ghi THRESH_TAP ) xy ra trong khong thi gian ngn hn thi gian quy nh trong thanh ghi DUR. Ngt double_tap: tng t trn, khi c 2 gia tc xy ra, trong tap th 2 bt u sau thi gian quy nh trong thanh ghi latent nhng vn nm trong khong thi gian quy nh trong thanh ghi window. Watermark: bit watermark c set khi s lng mu trong FIFO bng vi gi tr lu tr trong cc bit mu (thanh ghi FIFO_CTL). N s t ng c xa khi FIFO c c, v gi tr s quay tr li gi tr nh hn gi tr lu gi trong cc bit mu. S vt qu: bit overrun c set khi DL mi thay th DL cha c c. s hot ng chnh xc ca chc nng overrun ph thuc vo ch FIFO. ch bypass, bit overrun c set khi DL mi thay th DL cha c trong thanh ghi DATAX,DATAY,DATAZ. Cn tt c cc ch khc, set bit overrun khi FIFO y. bit overrun t ng xa khi ni dung ca FIFO c c. FIFO: l 1 b m c th gip ti thiu ha gnh nng x l ca my ch. C 4 ch c chn = cch set bit FIFO_MODE trong thanh ghi FIFO_CTL: Ch bypass: FIFO khng hot ng. tt c u trng(DL) Ch FIFO: DL o c t trc x,y,z c lu tr trong FIFO. Khi s lng mu trong FIFO = vi mc c nh trong bit mu ca thanh ghi FIFO, ngt watermark c set. FIFO tip tc tch ly mu cho n khi n y (32 mu) th dng vic thu thp DL. Sau khi FIFO dng thu thp DL, thit b vn tip tc lm vic, do pht hin tap c th c s dng khi FIFO y. ngt watermark tip tc xy ra n khi s lng mu trong FIFO nh hn gi tr lu gi trong bit mu ca thanh ghi FIFO_CTL. Ch Stream(dng, chy, lp): DL o t trc x,y,z c lu tr trong FIFO. Khi s lng mu trong FIFO = vi mc quy nh trong bit mu ca thanh ghi FIFO_CTL, ngt watermark c set. FIFO tip tc tch ly mu v gi 32 mu cui cng c o t trc x,y,z, loi b nhng DL c hn khi DL mi

n. Ngt watermark tip tc xy ra n khi s lng mu trong FIFO nh hn gi tr lu gi trong bit mu ca thanh ghi FIFO_CTL. Ch Trigger: FIFO tch ly mu v gi 32 mu cui cng c o t trc x,y,z. sau khi 1 s kin rt nhanh xy ra v 1 ngt c gi n chn INT1 hoc INT2 ( c quyt nh bi bit trigger trong thanh ghi FIFO_CTL), FIFO s gi n mu cui cng (n c nh sn bi bit mu trong thanh ghi FIFO_CTL) v sau lm vic ch FIFO, thu thp nhng mu mi ch khi FIFO cha y. nn c ti thiu 5us tr gia s kin trigger xy ra v vic bt u c DL t FIFO cho php FIFO loi b v gi li nhng mu cn thit. vic cng thm cc s kin trigger l khng th c cho n khi ch trigger c reset ( reset, ta a thit b v ch bypass sau quay tr li ch trigger) Ly DL t FIFO: DL FIFO c c bi cac thanh ghi DATAX,Y,Z. mi khi DL c FIFO c vo, nhng DL c nht s c a n cc thanh ghi trn. Kt thc ca vic c vo 1 DL thanh ghi c nh du bi vic chuyn thanh ghi 0x37 n 0x38 hoc CS ln mc cao. T kim tra: set bit SELF_TEST trong thanh ghi DATA_FORMAT Khi self-test enable, 1 tn hiu in s c a vo cm bin c, nh kiu 1 gia tc c cng vo thit b. kt qu l s thay i u ra trn cc trc x,y,z. v tn hiu in ny t l vi Vs nn s thay i u ra cng bin i theo Vs.(figure P22) Register map: Threshold: ngng Duration: thi gian tn ti Latency: chm nh ngha cc thanh ghi: Devid: cha m ID ca thit b Thresh_tap: 8bit, cha gi tr ngng cho ngt tap. Scale factor ( phn gii): 62.5mg/LSB (FF=16g) OFSX,Y,Z: