INT. J. NEW. INN.

, 2012, 1(1), 101-104

ISSN:2277-4459

REDUCTION OF SETTLING TIME IN FREQUENCY SYNTHESIZERS BY USING BANDPASS FILTERS

Govind Patel1, Arvind Pathak2, Sarita Bhan3

ABSTRACT
This paper demonstrates the design and performance of Band Pass Filter for reduction of settling time in high speed frequency synthesizers. These synthesizers find their wide applications in the field of communication. The introduction of Band Pass filter in these synthesizers provides a remarkable solution in various trendy tradeoffs in these high speed frequency synthesizers. In particular, it is possible to achieve a very high-frequency resolution together with fast settling and spectral purity. In different applications requirement of a clock signal to be synchronous, phase-locked, or derived from another signal, such as a data signal or another clock is mandatory. The proposed frequency synthesizer solution is superior in performance as compared to the conventional frequency synthesizer.

1. INTRODUCTION 2. ARCHITECTURE
The Frequency Synthesizer is nothing but a Phase Locked Loop which is a fundamental part of radio, wireless and telecommunication technology. PLL is a simple feedback architecture that allows economic multiplication of crystal frequencies by large variable numbers. By studying the loop components and their reaction to various noise sources, we will show that PLL is uniquely suited for generation of stable, low noise tunable RF signals for radio, timing and wireless applications [6]. The PLL has seen a number of challenges like economy in size, power and cost while maintaining good spectral purity. All PLL applications demand for achievement and maintenance of the phase-locked condition. In order to use frequency synthesizers for high speed applications, reduction of settling time has always been a challenge for PLL designers in different fields. In this paper, we will demonstrate about the phaselocked loop as a frequency synthesizer along with its block design. A PLL block is the core of our frequency synthesizer design. As it is a system with many analog sub-circuits, it can be used to test the designers analog expertise. Also, since it has many design constrains that will be shown in the following part of the chapter; we will use a full-custom design flow for the PLL block layout as a frequency synthesizer. 101

2.1. Phase Locked Loop as Frequency Synthesizer

The Frequency Synthesizer is nothing but a PLL (Phase Locked Loop) and it is mainly comprised of a Phase detector, A filter and a Voltage Controlled Oscillator as shown in Figure 1 below.

Figure 1.

In Figure 1 we have a normal PLL wherein a normal PLL operation can be seen i.e. a reference source is used to have a reference frequency fr and that reference frequency is fed to a phase detector for comparison between it and the Voltage controlled Oscillator (VCO) frequency which is divided by the fixed divider network International Journal of New Innovations