74HC4017; 74HCT4017

Johnson decade counter with 10 decoded outputs

Rev. 03 8 January 2008 Product data sheet

1. General description
The 74HC4017; 74HCT4017 is a high-speed Si-gate CMOS device and is pin compatible with the HEF4017. The 74HC4017; 74HCT4017 is a 5-stage Johnson decade counter with 10 decoded active HIGH outputs (Q0 to Q9), an active LOW output from the most signicant ip-op (Q5-9), active HIGH and active LOW clock inputs (CP0 and CP1) and an overriding asynchronous master reset input (MR). The counter is advanced by either a LOW-to-HIGH transition at CP0 while CP1 is LOW or a HIGH-to-LOW transition at CP1 while CP0 is HIGH (see Table 3). When cascading counters, the Q5-9 output, which is LOW while the counter is in states 5, 6, 7, 8 and 9, can be used to drive the CP0 input of the next counter. A HIGH on MR resets the counter to zero (Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW) independent of the clock inputs (CP0 and CP1). Automatic code correction of the counter is provided by an internal circuit: following any illegal code the counter returns to a proper counting mode within 11 clock pulses.

2. Features
s Multiple package options s Complies with JEDEC standard no. 7 A s ESD protection: x HBM JESD22-A114E exceeds 2000 V x MM JESD22-A115-A exceeds 200 V s Specied from 40 C to +85 C and from 40 C to +125 C

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

3. Ordering information
Table 1. Ordering information Package Temperature range Name 74HC4017 74HC4017N 74HC4017D 74HC4017DB 74HC4017PW 74HC4017BQ 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C 40 C to +125 C DIP16 SO16 SSOP16 TSSOP16 plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm plastic shrink small outline package; 16 leads; body width 5.3 mm SOT38-4 SOT109-1 SOT338-1 Description Version Type number

plastic thin shrink small outline package; 16 leads; SOT403-1 body width 4.4 mm

SOT763-1 DHVQFN16 plastic dual in-line compatible thermal-enhanced very thin quad at package; no leads; 16 terminals; body 2.5 3.5 0.85 mm DIP16 SO16 plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm SOT38-4 SOT109-1

74HCT4017 74HCT4017N 74HCT4017D 74HCT4017BQ 40 C to +125 C 40 C to +125 C 40 C to +125 C

DHVQFN16 plastic dual in-line compatible thermal-enhanced SOT763-1 very thin quad at package; no leads; 16 terminals; body 2.5 3.5 0.85 mm

4. Functional diagram

13 14 15

CP1 CP0 MR 5-STAGE JOHNSON COUNTER

DECODING AND OUTPUT CIRCUITRY Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 3 2 4 7 10 1 5 6 9 11

Q5-9

12

001aah242

Fig 1. Functional diagram

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

2 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

14 13 14 CP1 CP0 Q0 Q1 Q2 Q3 Q4 Q5 Q6 15 MR Q7 Q8 Q9 Q5-9

001aah239

CTRDIV10/DEC & CT = 0 0 1 2 3 4 5 6 7 8 9 CT5

001aah240

3 2 4 7 10 1 5 6 9 11 12

3 2 4 7 10 1 5 6 9 11 12

13 15

Fig 2. Logic symbol

Fig 3. IEC logic symbol

D CP1

CP0

Q FF 1 CP Q RD

Q FF 2 CP Q RD

Q FF 3 CP Q RD

Q FF 4 CP Q RD

Q FF 5 CP Q RD

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

Q5-9
001aah243

Fig 4. Logic diagram

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

3 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

CP0 INPUT

CP1 INPUT

MR INPUT

Q0 OUTPUT

Q1 OUTPUT

Q2 OUTPUT

Q3 OUTPUT

Q4 OUTPUT

Q5 OUTPUT

Q6 OUTPUT

Q7 OUTPUT

Q8 OUTPUT

Q9 OUTPUT

Q5-9 OUTPUT

001aah244

Fig 5. Timing diagram

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

4 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

5. Pinning information
5.1 Pinning
74HC4017 74HCT4017 74HC4017 74HCT4017
Q5 Q1 Q0 Q2 Q6 Q7 Q3 GND 1 2 3 4 5 6 7 8
001aah238

terminal 1 index area Q1 16 VCC 15 MR 14 CP0 13 CP1 12 Q5-9 11 Q9 10 Q4 9 Q8 Q6 Q7 Q3 5 6 7 Q0 Q2 2 3 4

16 VCC 15 MR 14 CP0 13 CP1 12 Q5-9 11 Q9 10 Q4 Q8 9

GND(1) 8 GND

Q5

001aah241

Transparent top view

Fig 6. Pin conguration DIP16, SO16 and (T)SSOP16

Fig 7. Pin conguration DHVQFN16

5.2 Pin description

Table 2. Symbol Q[0:9] GND Q5-9 CP1 CP0 MR VCC Pin description Pin 8 12 13 14 15 16 Description ground (0 V) carry output (active LOW) clock input (HIGH-to-LOW edge-triggered) clock input (LOW-to-HIGH edge-triggered) master reset input (active HIGH) supply voltage 3, 2, 4, 7, 10, 1, 5, 6, 9, 11 decoded output

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

5 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

6. Functional description
Table 3. MR H L L L L L L
[1] H = HIGH voltage level; L = LOW voltage level; X = dont care; = LOW-to-HIGH transition; = HIGH-to-LOW transition;

Function table[1] CP0 X H L X H CP1 X L X H L Operation Q0 = Q5-9 = HIGH; Q1 to Q9 = LOW counter advances counter advances no change no change no change no change

7. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC IIK IOK IO ICC IGND Tstg Ptot Parameter supply voltage input clamping current output clamping current output current supply current ground current storage temperature total power dissipation DIP16 package SO16 package (T)SSOP16 package DHVQFN16 package
[1] [2] [3] [4] [5]

Conditions VI < 0.5 V or VI > VCC + 0.5 V VO < 0.5 V or VO > VCC + 0.5 V 0.5 V < VO < VCC + 0.5 V
[1] [1]

Min 0.5 50 65

Max +7 20 20 25 50 +150 750 500 500 500

Unit V mA mA mA mA mA C mW mW mW mW

Tamb = 40 C to +125 C
[2] [3] [4] [5]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Ptot derates linearly with 12 mW/K above 70 C. Ptot derates linearly with 8 mW/K above 70 C. Ptot derates linearly with 5.5 mW/K above 60 C. Ptot derates linearly with 4.5 mW/K above 60 C.

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

6 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

8. Recommended operating conditions

Table 5. Symbol 74HC4017 VCC VI VO t/V supply voltage input voltage output voltage input transition rise and fall rate VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Tamb 74HCT4017 VCC VI VO t/V Tamb supply voltage input voltage output voltage input transition rise and fall rate VCC = 4.5 V ambient temperature 4.5 0 0 40 5.0 1.67 5.5 VCC VCC 139 +125 V V V ns/V C ambient temperature 2.0 0 0 40 5.0 1.67 6.0 VCC VCC 625 139 83 +125 V V V ns/V ns/V ns/V C Recommended operating conditions Parameter Conditions Min Typ Max Unit

9. Static characteristics
Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 74HC4017 VIH HIGH-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VIL LOW-level input voltage VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V VOH HIGH-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V 1.5 3.15 4.2 1.9 4.4 5.9 1.2 2.4 3.2 0.8 2.1 2.8 2.0 4.5 6.0 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 V V V V V V V V V V V Conditions Min 25 C Typ Max 40 C to +85 C 40 C to +125 C Unit Min Max Min Max

3.98 4.32 5.48 5.81

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

Table 6. Static characteristics continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOL Conditions Min LOW-level VI = VIH or VIL output voltage IO = 20 A; VCC = 2.0 V IO = 20 A; VCC = 4.5 V IO = 20 A; VCC = 6.0 V IO = 4.0 mA; VCC = 4.5 V IO = 5.2 mA; VCC = 6.0 V II ICC CI input leakage current VI = VCC or GND; VCC = 6.0 V 25 C Typ 0 0 0 0.15 0.16 3.5 Max 0.1 0.1 0.1 0.26 0.26 0.1 8.0 40 C to +85 C 40 C to +125 C Unit Min Max 0.1 0.1 0.1 0.33 0.33 1.0 80 Min Max 0.1 0.1 0.1 0.4 0.4 1.0 160 V V V V V A A pF

supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V input capacitance HIGH-level input voltage LOW-level input voltage VCC = 4.5 V to 5.5 V VCC = 4.5 V to 5.5 V

74HCT4017 VIH VIL VOH 2.0 1.6 1.2 0.8 2.0 0.8 2.0 0.8 V V

HIGH-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 4 mA LOW-level VI = VIH or VIL; VCC = 4.5 V output voltage IO = 20 A IO = 4.0 mA input leakage current VI = VCC or GND; VCC = 5.5 V

4.4

4.5

0.1 0.26 0.1 8.0

4.4 3.84 -

0.1 0.33 1.0 80

4.4 3.7 -

0.1 0.4 1.0 160

V V V V A A

3.98 4.32 0 0.15 -

VOL

II ICC ICC

supply current VI = VCC or GND; VCC = 5.5 V; IO = 0 A additional per input pin; supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A CP0 input CP1 input MR input

25 40 50 3.5

90 144 180 -

113 180 225 -

123 196 245 -

A A A pF

CI

input capacitance

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

8 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

10. Dynamic characteristics

Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11. Symbol Parameter 74HC4017 tpd propagation delay CP0 to Qn; CP0 to Q5-9; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CP1 to Qn; CP1 to Q5-9; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V tPHL HIGH to LOW propagation delay MR to Q[1:9]; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tPLH LOW to HIGH propagation delay MR to Q5-9, Q0; see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tt transition time see Figure 10 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V tW pulse width CP0 and CP1 (HIGH or LOW); see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V MR (HIGH); see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 80 16 14 19 7 6 100 20 17 120 24 20 ns ns ns 80 16 14 17 6 5 100 20 17 120 24 20 ns ns ns
[2] [1]

Conditions Min

25 C Typ Max

40 C to +85 C 40 C to +125 C Unit Min Max Min Max

63 23 20 18

230 46 39

290 58 49

345 69 59

ns ns ns ns

61 22 20 18

250 50 43

315 63 54

375 75 64

ns ns ns ns

52 19 15

230 46 39

290 58 49

345 69 59

ns ns ns

55 20 16 19 7 6

230 46 39 75 15 13

290 58 49 95 19 16

345 69 59 110 22 19

ns ns ns ns ns ns

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

9 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

Table 7. Dynamic characteristics continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11. Symbol Parameter tsu set-up time Conditions Min CP1 to CP0; CP0 to CP1; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V th hold time CP1 to CP0; CP0 to CP1; see Figure 8 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V trec recovery time MR to CP0 and MR to CP1; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V fmax maximum frequency CP0 or CP1; see Figure 9 VCC = 2.0 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF VCC = 6.0 V CPD power dissipation capacitance propagation delay VI = GND to VCC; VCC = 5 V; fi = 1 MHz
[3]

25 C Typ Max

40 C to +85 C 40 C to +125 C Unit Min Max Min Max

50 10 9

8 3 2

65 13 11

75 15 13

ns ns ns

50 10 9

17 6 5

65 13 11

75 15 13

ns ns ns

5 5 5 6.0 30 25 -

17 6 5 23 70 77 83 35

5 5 5 4.8 24 28 -

5 5 5 4.0 20 24 -

ns ns ns MHz MHz MHz MHz pF

74HCT4017 tpd CP0 to Qn; CP0 to Q5-9; see Figure 10 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CP1 to Qn; CP1 to Q5-9; see Figure 10 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF tPHL HIGH to LOW propagation delay LOW to HIGH propagation delay MR to Q[1:9]; see Figure 10 VCC = 4.5 V MR to Q5-9, Q0; see Figure 10 VCC = 4.5 V 20 46 58 69 ns 22 46 58 69 ns 25 21 50 63 75 ns ns
[1]

25 21

46 -

58 -

69 -

ns ns

tPLH

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

10 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

Table 7. Dynamic characteristics continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; see Figure 11. Symbol Parameter tt tW transition time pulse width Conditions Min see Figure 10 VCC = 4.5 V CP0 and CP1 (HIGH or LOW); see Figure 9 VCC = 4.5 V MR (HIGH); see Figure 9 VCC = 4.5 V tsu set-up time CP1 to CP0; CP0 to CP1; see Figure 8 VCC = 4.5 V th hold time CP1 to CP0; CP0 to CP1; see Figure 8 VCC = 4.5 V trec recovery time MR to CP0 and MR to CP1; see Figure 9 VCC = 4.5 V fmax maximum frequency CP0 or CP1; see Figure 9 VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD power dissipation capacitance VI = GND to VCC 1.5 V; VCC = 5 V; fi = 1 MHz
[3] [2]

25 C Typ 7 Max 15

40 C to +85 C 40 C to +125 C Unit Min Max 19 Min Max 22 ns

16 16

7 4

20 20

24 24

ns ns

10

13

15

ns

10

13

15

ns

5 30 -

5 61 67 36

5 24 -

5 20 -

ns MHz MHz pF

[1] [2] [3]

tpd is the same as tPHL and tPLH. tt is the same as tTHL and tTLH. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs.

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

11 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

11. Waveforms
VI CP0 input GND tsu VI CP1 input GND
001aah245

VM th tsu th

VM

Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.

Fig 8. Waveforms showing the set-up and hold times for CP0 to CP1 and CP1 to CP0

1/f max tW VI CP0 input GND 1/f max VI CP1 input GND VI MR input GND tW VOH Q1 - Q9 output VOL tPHL VOH Q0, Q5 - Q9 output VOL tPLH VM
001aah246

VM

VM tW trec VM

VM

Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load.

Fig 9. Waveforms showing the minimum pulse width for CP0, CP1 and MR input; the maximum frequency for CP0 and CP1 input; the recovery time for MR and the MR input to Qn and Q5-9 output propagation delays

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

VI CP0 input GND VI CP1 input GND tPHL VOH Q1 - Q9 output VOL tPLH VOH Q0, Q5 - Q9 output VOL VM tTLH tTHL 001aah247 tPHL VM tPLH VM VM

Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Conditions: CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW transition.

Fig 10. Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times Table 8. Type 74HC4017 74HCT4017 Measurement points Input VM 0.5 VCC 1.3 V Output VM 0.5 VCC 1.3 V

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

VI negative pulse 0V

tW 90 % VM 10 % tf tr tr tf 90 % VM 10 % tW VM VM

VI positive pulse 0V

VCC

VCC

PULSE GENERATOR

VI

VO

RL

S1

DUT
RT CL

open

001aad983

Test data is given in Table 9. Denitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch.

Fig 11. Load circuitry for measuring switching times Table 9. Type 74HC4017 74HCT4017 Test data Input VI VCC 3V tr, tf 6 ns 6 ns Load CL 15 pF, 50 pF 15 pF, 50 pF RL 1 k 1 k S1 position tPHL, tPLH open open tPZH, tPHZ GND GND tPZL, tPLZ VCC VCC

12. Application information

Some examples of applications for the 74HC4017; 74HCT4017 are:

Decade counter with decimal decoding 1 out of n decoding counter (when cascaded) Sequential controller Timer

Figure 12 shows a technique for extending the number of decoded output states for the 74HC4017; 74HCT4017. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay).

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

14 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

CP0

MR

CP0

MR

CP0

MR

74HC4017 74HCT4017
CP1 Q0 Q1- - - - Q8 Q9

74HC4017 74HCT4017
CP1 Q0 Q1- - - - Q8 Q9

74HC4017 74HCT4017
CP1 Q1 - - - - - - Q8 Q9

9 decoded outputs

8 decoded outputs

8 decoded outputs

clock

first stage

intermediate stages

last stage
001aah248

Fig 12. Counter expansion

Remark: It is essential not to enable the counter on CP1 when CP0 is HIGH, or on CP0 when CP1 is LOW, as this would cause an extra count. Figure 13 shows an example of a divide-by 2 through divide-by 10 circuit using one 74HC4017; 74HCT4017. Since the 74HC4017; 74HCT4017 has an asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths can be enlarged by inserting an RC network at the MR input.

74HC4017 74HCT4017
divide - by 5 Q5 Q1 Q0 divide - by 2 divide - by 6 divide - by 7 divide - by 3 Q2 Q6 Q7 Q3 GND VCC MR CP0 CP1 Q5-9 Q9 Q4 Q8 divide - by 10 divide - by 9 divide - by 4 divide - by 8 fin VCC

fout
001aah249

Fig 13. Divide-by 2 through divide-by 10

74HC_HCT4017_3

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Product data sheet

Rev. 03 8 January 2008

15 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

13. Package outline

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

D seating plane

ME

A2

A1

c Z e b1 b 16 9 b2 MH w M (e 1)

pin 1 index E

5 scale

10 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 b2 1.25 0.85 0.049 0.033 c 0.36 0.23 0.014 0.009 D (1) 19.50 18.55 0.77 0.73 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 0.76 0.03

Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT38-4 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION

ISSUE DATE 95-01-14 03-02-13

Fig 14. Package outline SOT38-4 (DIP16)

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Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

SO16: plastic small outline package; 16 leads; body width 3.9 mm

SOT109-1

A X

c y HE v M A

Z 16 9

Q A2 pin 1 index Lp 1 e bp 8 w M L detail X A1 (A 3) A

2.5 scale

5 mm

DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 Z (1) 0.7 0.3

0.010 0.057 0.069 0.004 0.049

0.019 0.0100 0.39 0.014 0.0075 0.38

0.244 0.041 0.228

0.028 0.004 0.012

8 o 0

ISSUE DATE 99-12-27 03-02-19

Fig 15. Package outline SOT109-1 (SO16)

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Product data sheet

Rev. 03 8 January 2008

17 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm

SOT338-1

A X

c y HE v M A

Z 16 9

Q A2 A1 pin 1 index Lp L 1 bp 8 w M detail X (A 3) A

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 o 0
o

Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION

ISSUE DATE 99-12-27 03-02-19

Fig 16. Package outline SOT338-1 (SSOP16)

74HC_HCT4017_3 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

18 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm

SOT403-1

c y HE v M A

16

Q A2 pin 1 index A1 Lp L (A 3) A

1
e bp

8
w M detail X

2.5 scale

5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 5.1 4.9 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.40 0.06 8 o 0
o

Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18

Fig 17. Package outline SOT403-1 (TSSOP16)

74HC_HCT4017_3 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

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NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT763-1 16 terminals; body 2.5 x 3.5 x 0.85 mm

A A1 E c

terminal 1 index area

detail X

terminal 1 index area e 2 L

e1 b 7 v M C A B w M C y1 C

C y

1 Eh 16

8 e 9

15 Dh

10 X 2.5 scale 5 mm

DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 3.6 3.4 Dh 2.15 1.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1

Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT763-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27

Fig 18. Package outline SOT763-1 (DHVQFN16)

74HC_HCT4017_3 NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

20 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

14. Abbreviations
Table 10. Acronym CMOS DUT ESD HBM MM TTL Abbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model Transistor-Transistor Logic

15. Revision history

Table 11. Revision history Release date 20080108 Data sheet status Product data sheet Change notice Supersedes 74HC_HCT4017_CNV_2 Document ID 74HC_HCT4017_3 Modications:

The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 3: DHVQFN16 package added. Section 7: derating values added for DHVQFN16 package. Section 13: outline drawing added for DHVQFN16 package. Product specication -

74HC_HCT4017_CNV_2

19970829

74HC_HCT4017_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

21 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

16. Legal information

16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]

Product status[3] Development Qualication Production

Denition This document contains data from the objective specication for product development. This document contains data from the preliminary specication. This document contains the product specication.

Please consult the most recently issued document before initiating or completing a design. The term short data sheet is explained in section Denitions. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

16.2 Denitions
Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofce. In case of any inconsistency or conict with the short data sheet, the full data sheet shall prevail.

malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specied use without further testing or modication. Limiting values Stress above one or more limiting values (as dened in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/prole/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

16.3 Disclaimers
General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or

16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

17. Contact information

For additional information, please visit: http://www.nxp.com For sales ofce addresses, send an email to: salesaddresses@nxp.com

74HC_HCT4017_3

NXP B.V. 2008. All rights reserved.

Product data sheet

Rev. 03 8 January 2008

22 of 23

NXP Semiconductors

74HC4017; 74HCT4017
Johnson decade counter with 10 decoded outputs

18. Contents
1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 7 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Application information. . . . . . . . . . . . . . . . . . 14 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 21 Legal information. . . . . . . . . . . . . . . . . . . . . . . 22 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 22 Denitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Contact information. . . . . . . . . . . . . . . . . . . . . 22 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information.

NXP B.V. 2008.

All rights reserved.

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 January 2008 Document identifier: 74HC_HCT4017_3