International Journal of Electronics Engineering, 2(1), 2010, pp.

143-149

A Low-power Full-adder Cell based on Static CMOS Inverter

Pooja Mendiratta1 & Garima Bakshi2
ECE Department, Northern India Engineering College, IP University, Delhi, India

Abstract: A new low-powerful-adder based on CMOS inverter is presented. This full-adder is comprised of inverters. Universal gate such as NOR, NAND and MAJORITY- NOT gates are implemented with a set of inverters and non-conventional implementation of them. In the proposed design approach the time consuming XOR gates are eliminated. As full-adders are frequently employed in a tree-structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is employed to evaluate the full-adders in a realistic application environment. The circuits being studied were optimized for energy efficiency using 0.18 mm and 90nm CMOS process technologies. The proposed full- adder shows full swing logic, balanced outputs and strong output drivability. It is also observed that the presented design can be utilized in many cases especially when ever the lowest possible power consumption is targeted. Circuits layout implementations and checking their functionality have been done using Cadence IC package and Synopsys HSpice, respectively. Keywords: Low-power Full-adder, Low-power CMOS Design, Inverter-based Full-adder Design, Transmission Gate.

1. INTRODUCTION

Addition is a very basic operation in arithmetic. Subtraction, multiplication, division and address calculation are some of the well-known operations based on addition. These operations are widely used in many VLSI applications, since the full-adder cell is the building block of the binary adder, enhancing the performance of the1-bitfull-adder is a significant goal and has attracted much attention. A variety of full-adders using different logic styles and technologies have been reported in literature [112] and they commonly aim at reducing power consumption and increasing speed. The total power dissipated in a generic digital CMOS gate is given by Ptotal = Pdynamic + Pshortcircuit + Pstatic (1) = Vdd Fclk Viswing Ci load i + Vdd + Iisc + Vdd Il where Fclk denote system clock frequency, Vi swing is the voltage swing at node i (ideally equal to Vdd), Ci load is the load capacitance at node i, i is the activity factor at node i, and Ii sc and Il are the short circuit and leakage currents. Many full-adders have been designed and published in literature. They are built upon different logic styles. Among these adders the circuits explained below will be used for comparison in this paper. Although all of them perform a similar function, but the method of producing the intermediate nodes and the outputs, the loads on them and the transistor count are varied. Different logic styles tend to favor one performance aspect at the expense of the other. Some of them use one logic style for the whole full- adder and the others use more than one logic style for their implementation. In all of these full-adders, it is tried to reduce

power and delay factors and thus decrease power-delay product (PDP) in comparison to the previous ones. In the following, a brief description of each full-adder is presented. The most conventional one is complementary CMOS fulladder (C-CMOS) [13]. It is based on regular CMOS structure with pull-up and pull-down transistors and has 28 transistors. Another conventional adder is the Complementary PassTransistor Logic (CPL) [7,14,15] with swing restoration which uses 32 transistors. CPL produces many intermediate nodes and their complement to make the outputs. The basic difference between the pass- transistor logic and the complementary CMOS logic styles is that the source side of the pass logic transistor network is connected to some input signals instead of the power lines [2,16]. In [17] the Transmission Function Full-Adder (TFA) is proposed. It is based on transmission function theory and transmission gates and has 16 transistors. Transmission gates [16,18] consist of a PMOS transistor and a NMOS transistor that are connected in parallel. Another Transmission Gate Full-Adder (TGA) presented in [18] contains 20 transistors. TFA and TGA are inherently low- power consuming and they are good for designing XOR or XNOR gates [13, 14, 19]. The main disadvantage of these logic styles is the lack of driving capability. When TGA or TFA are cascaded, their performance degrades significantly. The 14-Transistor (14T) full-adder uses more than one logic style for their implementation called hybrid logic design style [7, 14, 20]. It suffers from then one full swing pass transistors with swing restored transmission gate techniques.The10-Transistor (10T)full-adder [21] uses hybrid logic style similar to 14T. It has small transistor count but it is not full swing. This full-adder and 14 Tfull-adder suffer from the lack of driving

144 capabilities in fan- out situation and their performances degrade dramatically when they are cascaded. It must be stated that this full-adder cannot work properly when supply voltage is less than1.8V. Another full- adder cell is hybrid full-adder [14]. In this design the pass logic circuit that generates the intermediate XOR and XNOR outputs has been improved. This full-adder cell can work at low supply voltage. It uses 26 transistors but has the full swing logic, balanced output and good output drivability. In the last two full-adders [10, 11], the time consuming XOR and XNOR gates have been eliminated by the technique used in designing MAJORITY-NOT function. They enjoy lowpower dissipation due to their transistor counts. In this study a new low-powerful-adder circuit is introduced which only uses inverters and transmission gates. This full-adder has a simple structure but it operates very well and results in remarkable advances in reducing power in comparison to other well-known designs. This reduction is due to simple structure, reduced number of transistors and the lowering in switching activities. Again, it is worth mentioning that in the proposed design only a few inverters and pass gates have been used, thus the number of transistors have been decreased. In achieving this design the other possible schemes have been investigated and in every step it is tried to overcome the design problems and improve it. The remaining of the paper is organized as follows. A new design technique for NAND, NOR and MAJORITYNOT gates is proposed in Section (2). Section (3) analyzes their performance and power consumption. The simulation results have also been shown in Section(3).The full-adder cell is presented in Section (4).Section(5) shows the postlayout simulation result and layout implementation of the proposed full-adder and finally some conclusions and future research directions are summarized in Section(6).
2. NEW TECHNIQUE IN DESIGNING STATIC CMOS GATES BASED ON CMOS INVERTER

International Journal of Electronics Engineering

Figure. 1: Three Input NAND, NOR, MAJORITY- NOT Function Gate with Capacitors.

The circuit for implementing the universal gates is illustrated in Fig. 1. Because of just two transistors in Fig. 1 the supply voltage can be reduced. In this situation Pshort-circuit is eliminated due to Eq. (2), and because of low voltage scaling, Pdynamic is reduced in a quadratic manner. So the average power dissipation is lower than conventional CMOS gates. Although lowering supply voltage and modifying the threshold voltage results in decreasing the power consumption, modifying Vth and reducing supply voltage have direct influence on latency of the circuit, and as shown in Eqs.(3) and (4) any increase in Vth or decrease in supply voltage causes reduction in performance of the circuit [22].

C1Vdd TPropagation NMOS = TPH L H K (V V ) 2 n dd tn

C1Vdd TPropagation PMOS = TPL H K (V | V |)2 p dd tp

(3) (4)

Generally the power dissipation in a CMOS circuit is calculated by Eq.(1). As shown in this equation there are three major components of power dissipation, Pdynamic, Pshort, Pstatic. In classical CMOS inverters, when both transistors circuit turn on at the same time, power consumption will be increased. If P short-circuit can be eliminated, the power dissipation will be decreased by a remarkable amount. This can occur when both of transistors are not able to be on at the same time. The condition that creates this situation is demonstrated in the following equation. Vdd < |Vtp | + Vtn (2)

Where: Vtp and Vtn are threshold voltages for PMOS and NMOS transistors, respectively. Threshold voltage is a voltage at which channel formation occurs in a metaloxide semiconductor field- effect transistor (MOSFET).

As shown in Fig. 1 the new circuit in [10, 11] is used to implement functions with inverter. Because of only one transistor either in charge or in discharge phase, the proposed circuit is faster than the conventional ones, except in one situation (Table1). The dynamic NOR gate is faster than the proposed one but still then new one has lower PDP and power consumption. To implement NAND Gate with Fig. 1 it is just enough to use high-Vth NMOS and low-Vth PMOS. For implementing NOR gate, high-Vth PMOS and low-Vth NMOS have been used and finally in order to have MAJORITYNOT Function both transistors are replaced with high-Vth transistors. Using high-threshold voltage transistors and lowthreshold voltage transistors in addition to normal-threshold transistors have been accomplished in low-power application, and many circuits have enjoyed this technique in low-power design. Multi-threshold CMOS (MTCMOS) circuits and dual-Vth techniques use high-Vth transistors to eliminate and reduce the leakage current through a transistor,

A Low-power Full-adder Cell based on Static CMOS Inverter

145 (1) Delay Comparison: The values of power, delay and power-delay product of conventional and presented gates are illustrated in Table1, for comparison. For each transition, the delay is measured from 50% of the input voltage swing to 50% of the output voltage swing. The maximum delay is taken as the cell delay. The new design of NAND gate Is 16% and 36% faster than Dynamic and Static NAND gates, respectively. The delayof Dynamic NOR gate is smaller than the new design, but this degradation is compensated with its improvement in power dissipation and as it is shown this new design has better Power-Delay Product. (2) Power Comparison: HSpice generated an average power consumption value for each circuit. As Table1 shows, simulation results illustrate that the Static3 input gates with revising threshold voltage has lowest power dissipation amongst the other gates. The proposed NOR gate consumes 8%, 23%, NANDgate7%, 25% and MAJORITY-NOT Function gate 21%, 22% less power than the Static and Dynamic gates, respectively. (3) Power-delay Product Comparison: The PDP is a quantitative measure of the efficiency and a compromise between power dissipation and speed. PDP is particularly important when low-power operation is needed. As Table1 shows, among all of these gates the presented circuits have the best PDP. PDP simulations are also per formed in 0 and 70 deg C to measure the susceptibility to noise. Results show that the new circuit can work reliably in these temperatures and increasing or decreasing the delay and power consumption in 0 and 70 deg C toward 27 deg C is acceptable. This method can be expanded to build logical gates with more inputs by increasing input capacitors; however, this reduces noise margin. In this design input voltage of CMOS inverters are 0, 1/3Vdd, 2/3Vdd or Vdd when 0, 1, 2or 3 of inputs are high. Using more than eight levels exposes the circuits to serious sensibility to noise. Simulation shows that six-input gate can be implemented by means of this method without any critical reduction in immunity to noise where as the difficult task of making six-input gate by conventional Static or Dynamic logic style requires large number of transistors.
4. THE PROPOSED FULL-ADDER DESIGN

thereby decreasing leakage power consumption while maintaining performance. So reducing the leakage power and the propagation delay time to design energy efficient high speed circuit with low-power-delay product is achievable by using modified threshold voltage transistor in circuit path.
Table 1 Simulation Results for NAND, NOR and MAJORITY-NOT Function in 0.18 mm Technology at 27 1C. NAND Proposed Delay (ns) Power(mW) PDP (fJ) 0.02282 0.03779 0.00862 NOR Proposed Delay (ns) Power(mW) PDP (fJ) 0.02645 0.0388 0.01026 Static 0.03917 0.041959 0.01643 Dynamic 0.02519 0.050501 0.01272 Static 0.03547 0.040646 0.01442 Dynamic 0.02725 0.050414 0.01374

MAJORITY-NOT Function Proposed Delay (ns) Power(mW) PDP (fJ) 0.01803 0.03734 0.00673 Static 0.0423 0.047552 0.02011 Dynamic 0.0354 0.048169 0.01705

In the next section, all of the comparisons are done between the circuit that is shown in Fig. 1 by revising Vth and the conventional dynamic and static circuits.
3. ANALYSIS AND RESULTS

Simulations using HSpice have been performed on nine circuits including: Static3 input NAND, Static3 input NOR, Static3 input MAJORITY-NOT Function, Dynamic 3 input NAND, Dynamic3 input NOR, Dynamic3 input MAJORITY-NOT Function, New Static 3 input NAND, New Static3 input NOR and New Static3 input MAJORITY-NOT Not Function with revising threshold voltage. The technology being used is 0.18mm. For the six previous static and dynamic circuits the threshold voltage of the NMOS and PMOS transistors are around 0.39 and 0.42 V, respectively, but by modifying the threshold voltage of the circuit shown in Fig. 1, NAND, NOR, and MAJORITY-NOT Function can be implemented. The operating frequency is 100MHz and the supply voltage is1V at 27 deg C. The inputs are fed from the buffers (two cascaded inverters) to give more realistic input signals. A randomly generated input pattern is applied to the cells for a long period in order to measure the average power consumption of the cells. Comparison of different NAND, NOR and MAJORITY-NOT Function to achieve minimum PDP is discussed below and the three subsections refer to DELAY, POWER, and PDP.

In this section the new design for full-adder is discussed. The main idea is shown in the circuit of Fig. 2. The carry output is equal to majority of inputs. Here Cout is implemented with a MAJORITY-NOT gate. As it can be seen in Table2, in six states of the inputs, the sum output is the reversed of the carry output. The two other states can be implemented

146 with a NOR and a NAND gate. When all three inputs of the full-adder are logic zero, the sum output will be logic zero. Thus, a NOR gate can be used to obtain the respective output. When the three inputs are logic one, the sum output will be logic one and this output can be detected with a NAND gate. Finally when the three inputs are in the other six states, both of the output transistor, the MN1 and the MP1 are off and as was cited, in these six states the sum output of the fulladder is equal to the Cout. In the all-0-state the output of NOR gate is1 and the MN1 transistor is on. As a result, the sum output is connected to the GND. The all-1-state is detected with the NAND gate. Only in this state the output of this gate is 0 and the MP1 is on which connects the sum output to the power supply.

International Journal of Electronics Engineering

The NAND, NOR and MAJORITY-NOT gates used in this circuit have a similar structure as it was shown in previous section (Fig. 1). All of them are based on an inverter. An inverter can implement NOR function if the output is low when the algebraic sum of inputs becomes greater than or equal to logical 1. Identical inverter can implement the NAND gate if the output is low only when algebraic sum of inputs is equal to logical 3. And finally MAJORITY-NOT gate is implemented with an inverter that is low when the algebraic sum of inputs is greater than logical 2. Only with justification of the threshold voltage of the used inverter as it is explained previously, NAND, NOR or MAJORITYNOT gates are generated (Fig. 3). The schematic of the proposed circuit based on inverters is shown in Fig. 4. In six mid-states of the truth table the Sum output is equal to Cout and theMN1and MP1 transistors are off. But in all- onestate and all-zero-state the Sum output is obtained by the NAND and NOR gates, respectively. In order to make the circuit operate in the mentioned states, the path between Cout output and Sum output should be disconnected. Therefore, one NMOS and one PMOS transistor are used as pass transistors and added to the circuit as shown in Fig. 5. These transistors disconnect the path between Cout and SUM in allzero-state and all-one-state. In order to have full swing voltage circuit, all pass transistors are substituted with transmission gates and the final circuit is shown in Fig. 6.
5. SIMULATION RESULTS

Figure. 2: The Main Idea of New Full-adder Circuit A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Cout 0 0 0 1 0 1 1 1

Cout
1 1 1 0 1 0 0 0

Sum 0 1 1 0 1 0 0 1

Figure. 3: Three Input NAND, NOR, MAJORITY-NOT Function Gate with Capacitors

In this section, the proposed circuit (Fig. 6) is evaluated and compared to the other ones chosen from literature. The fulladder cells are simulated using 0.18 mm and 90 nm CMOS technology files with 250 MHz and at 27 deg C and the supply voltages varying from 0.8 to 1.8V for 0.18 mm and 0.61.2V for 90 nm. It has been a common practice to treat the full-adder cell as a standalone cell in simulation [17, 1921]. It is also not unusual that the full-adder cells that perform well in such simulation still fail upon actual deployment because of the lack of driving power. This is because full-adder cells are normally cascaded to form a useful arithmetic circuit. Therefore, the full adder cells must possess sufficient drivability to provide then excel with clean inputs [7]. In short, the driving cell must provide almost full swing outputs to the driven cells. Otherwise, the performance of the circuit will be degraded dramatically or become nonoperative at low supply voltage. For this reason, the adder cells of TFA, TGA, 14T, and 10T cannot be cascaded without additional buffers attached to the outputs of each cell. In order to have a practical application for the proposed circuit, the suggested structure for simulation is shown in Fig. 7, which is made of 16 cascaded full-adder cells. This structure simulates the circuits like regular multipliers and binary adders that use full-adder cells as the building block. The

A Low-power Full-adder Cell based on Static CMOS Inverter

147 Apart from immunity to temperature and supply voltage noises, the proposed design has been checked against the noisy inputs.

inputs are fed from the buffers to give more realistic input signals and the outputs are loaded with buffers to give proper loading condition. All the required input-pattern-to-inputpattern transitions are included in the test patterns. The power consumption value and delay are measured for the ninth cell. In the proposed circuit, three similar capacitors with capacitance of 10.41fF are required. As HSpice simulation shows this capacitance value resulted in the best performance of the circuit. Simulation results are presented in Tables 3 and 4 for 0.18 mm and Tables 5 and 6 for 90nm technologies. The values of power, delay and power-delay product of CCMOS, CPL, TFA, TGA, 14T, 10T, Hybrid, Majority-based adder and the proposed full-adder are presented in Tables3 6 for comparison. As already mentioned the lowest operating voltage for 10T is 1.8V but the supply voltage for C-CMOS, CPL, TFA, TGA, the Majority- based adder, Hybrid and the proposed full-adder can be down to 0.8V and for 14 T is limited to 1V in 0.18 mm. Furthermore, 10T is not operable in 90nm technology. Simulation results show that the new proposed full-adder consumes less power than the C-CMOS, CPL, TFA, TGA, Hybrid, and Majority- based design as shown in Tables 36. This is quite clear that the proposed full-adder has a very low switching activity. A sit can be seen in Table7, there are only four states at the inverter outputs (111, 101, 100 and 000) and therefore very low switching activity is achieved. In addition, we have only one transition in the NAND output, one transition in the NOR output and three transitions in the Majority-Not output. The simulation results also exhibit that C-CMOS, TFA, TGA, CPL, Hybrid, Majority-based design, and the proposed full-adder can function reliably at supply voltage as low as 0.8 V for 0.18 mm and 0.6V for 90nm. As Tables 36 show, the PDP of all of the other fulladders are small at the very low voltages and then new stated full-adder has the best PDP in comparison with others. The values of delay and power consumption for the proposed and some of conventional adder cells including C-CMOS, CPL and Hybrid in different temperatures are shown in Table10. Simulation results in Tables 36 were measured at room temperature of around 27 deg C but, values of Table 10 were attained at 0 and 70 deg C with similar supply voltage to Tables 3 and 5. As Table 10 shows, lowering temperature decreases the power consumption and speed of circuits but any increase in temperature enlarges these parameters. It is also obvious from Table10 that the new design can perform reliable in these temperatures and increasing or decreasing of delay and power consumption at 0 and 70 deg C toward 27 deg C is acceptable. It means that the proposed design has an acceptable functionality in a vast temperature range.

Figure. 4: New Inverter- based Full-adder.

Figure. 5: New Inverter-based Full-adder with Pass Transistors

Figure. 6: New Inverter-based Full-adder with Transmission Gates.

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International Journal of Electronics Engineering Table 6 Simulation Results for Full-adders in 90nm Technology and 1.2V Supply Voltage Design C-CMOS CPL TFA TGA 14T 10T Hybrid Majority-based 0.7525 0.5865 0.8475 0.7565 4.7863 1.3265 0.7420 0.5936 0.7215 0.5190 0.5218 0.7256 0.6538 12.7580 19.0287 0.5045 0.4006 0.3209 Proposed FA A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 Temp. 0 deg C 90nm (Vdd = 0.6) Delay C-CMOS CPL Hybrid Majority Proposed 0.402 0.254 0.385 0.243 0.261 Power 0.163 0.345 0.152 0.147 0.074 0.18mm (Vdd = 0.8 V) Delay 0.78 0.62 0.758 0.621 0.741 Power 0.649 0.791 0.588 0.592 0.383 Average power (mW) 1.5893 1.7683 1.7459 1.7796 3.3329 1.5793 1.5751 1.4739 C 0 1 0 1 0 1 0 1 Delay(ns) 0.1274 0.0785 0.3258 0.2348 0.3477 0.2203 0.0939 0.2002 PDP(fJ) 0.2025 0.1388 0.5688 0.4179 1.1588 0.3479 0.1479 0.2951 NAND 1 1 1 1 1 1 1 0

Figure. 7: Test-bench Structure. Table3 Simulation Results for Full-adder sin 0.18 mm Technology and 0.8V Supply Voltage (Supply Voltage for 10T and 14T is 1.8 and 1V ). Design CCMOS CPL TFA TGA 14T 10T Hybrid Majoritybased Proposed FA Average power(mW) 0.6898 0.8897 0.8562 0.8643 2.6657 14.3451 0.6800 0.6749 0.4449 Delay(ns) PDP(fJ)

Table4 Simulation Results for Full-adders in 0.18 mm Technology and 1.8V Supply Voltage Design Average Power(mW) 6.2341 7.7234 8.2552 8.4768 12.7312 14.3451 6.3956 6.3227 5.8459 Delay(ns) 0.2927 0.1843 0.2882 0.2949 0.3827 1.3265 0.2743 0.1854 0.1971 PDP(fJ) 1.8247 1.4234 2.3791 2.4998 4.7822 19.0287 1.1727 1.1722 1.1522

Tech.

CCMOS CPL TFA TGA 14T 10T Hybrid Majority-based Proposed FA

6. CONCLUSION

Table 5 Simulation Results for Full-adders in 90nm Technology and 0.6V Supply Voltage Design Average power(mW) 0.1881 0.3887 0.3642 0.3784 0.1781 0.1730 0.1037 Delay(ns) 0.3765 0.2237 0.4715 0.3805 0.3660 0.2176 0.3455 PDP(fJ) 0.0708 0.0870 0.1717 0.1440 0.0652 0.0376 0.0358

C-CMOS CPL TFA TGA 14T 10T Hybrid Majority-based Proposed FA

A novel low-power inverter- based 1-bit full-adder is proposed in this paper. Its simple 16 transistors structure results in a significant improvement in power consumption, PDP and performance of a1-bit full-adder cell. Few transistor counts, the ability to work at ultralow-power supply voltages, and finally elimination of short circuit current are the three major features of the proposed adder cell. Synopsys HSpice pre-layout and Cadence Spectre post-layout simulations have been performed to evaluate the full-adder cell. This observation indicates that the inverter- based full-adder is a suitable structure for constructing big low- power and highperformance VLSI systems. Directions for future works may include more detailed performance metrics evaluations, as well as implementing many other circuits in nanometer regime such as Single Electron Transistor (SET), Carbon Nano Tube (CNT), Quantum-dot Cellular Automata (QCA), and generally whenever the threshold detects or technique is applicable.

A Low-power Full-adder Cell based on Static CMOS Inverter

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