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K.L.N.

COLLEGE OF ENGINEERING
POTTAPALAYAM - 6 3 0 6 1 1 .
(AN ISO 9001:2008 CERTIFIED INSTITUTION AFFILIATED TO ANNA UNIVERSITY)

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING


(ACCREDITED BY NBA)

FOR VI SEMESTER
ELECTRONICS AND COMMUNICATION ENGINEERING
(Even Semester 2010 - 2011)

EC 1356 VLSI DESIGN


LABORATORY MANUAL

Compiled By
D.Anand, M.E.,
Asst.Professor-2/ECE

K.L.N.COLLEGE OF ENGINEERING
POTTAPALAYAM - 6 3 0 6 1 1
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CLASS

: VI SEMESTER

BRANCH

: ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT

: VLSI DESIGN LABORATORY

SUB. CODE : EC 1356


LIST OF EXPERIMENTS

3
4
5

I - Cycle

SL. NO
1
2

10

II - Cycle

PAGE NO

Study of Development Tool for FPGA for Schematic Entry and Verilog
Design of Traffic Light Controller Using Verilog and Above Tools
Design and Simulation of Pipelined Serial and Parallel Adder to
Add/Subtract 8 Bit Number of Size, 12 Bits Each in 2's Complement
Design and Simulation of Back Annotated Verilog Files for
Multiplying Two Signed, 8 Bit Numbers in 2's Complement. Design
must be Pipelined and Completely RTL Compliant

NAME OF THE EXPERIMENTS


Study of Simulation Using Tools
Study of Synthesis Tools
Place and Root and Back Annotation for FPGAs

Study of FPGA Board and Testing on Board LEDs and Switches Using
Verilog Codes.
Testing the Traffic Controller Design Developed in SI. NO.5 on the
FPGA Board
Design a Real-time Clock (2 Digits, 7 Segments LED Displays Each
for HRS., MTS, And SECS.) and demonstrate its Working on the
FPGA Board (An Expansion Card is Required
for the Displays)

STAFF INCHARGE

HOD/EEE

K.L.N.COLLEGE OF ENGINEERING
POTTAPALAYAM - 6 3 0 6 1 1
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

VI SEMESTER/ECE
EC 1356 VLSI DESIGN LABORATORY
NAME OF THE STUDENT :

_________________________________

ROLL NUMBER

_________________________________

YEAR & SEMESTER

_________________________________

Sl.

DATE

No

OF

NAME OF THE EXPERIMENT

DATE OF
SUBMISSION

SIGNATURE

MARK

EXP.

SIGNATURE OF STAFF INCHARGE

Expt.No:
Date :

STUDY OF SIMULATION TOOLS

AIM:
To study the Simulation tools.
THEORY:
Creating a Test Bench for Simulation:
In this section, you will create a test bench waveform containing input stimulus you
can use to simulate the counter module. This test bench waveform is a graphical view
of a test bench. It is used with a simulator to verify that the counter design meets both
behavioral and timing design requirements. You will use the Waveform Editor to
create a test bench
waveform (TBW) file.
1. Select the counter HDL file in the Sources in Project window.
2. Create a new source by selecting Project _ New Source.
3. In the New Source window, select Test Bench Waveform as the source type, and
type test bench in the File Name field.
4. Click Next.
5. The Source File dialog box shows that you are associating the test bench with the
source file: counter. Click Next.
6. Click Finish. You need to set initial values for your test bench waveform in the
Initialize Timing dialog box before the test bench waveform editing window opens.
7. Fill in the fields in the Initialize Timing dialog box using the information below:
Clock Time High: 20 ns.
Clock Time Low: 20 ns.
Input Setup Time: 10 ns.
Output Valid Delay: 10 ns.
Initial Offset: 0 ns
Global Signals: GSR (FPGA)
Leave the remaining fields with their default values.
8. Click OK to open the waveform editor. The blue shaded areas are associated with
each input signal and correspond to the Input Setup Time in the Initialize Timing
dialog box. In this tutorial, the input transitions occur at the edge of the blue cells
located under each rising edge of the CLOCK input.

Fig 2: Waveform Editor - Test Bench

Fig 3:Waveform Editor - Expected Results


9. In this design, the only stimulus that you will provide is on the DIRECTION port.
Make the transitions as shown below for the DIRECTION port:
Click on the blue cell at approximately the 300 ns clock transition. The signal
switches to high at this point.
Click on the blue cell at approximately the 900 ns clock transition. The signal
switches back to low.
Click on the blue cell at approximately the 1400 ns clock transition. The signal
switches to high again.
10. Select File _ Save to save the waveform. In the Sources in Project window, the
TBW file is automatically added to your project.
11. Close the Waveform Editor window.

Adding Expected Results to the Test Bench Waveform:


In this step you will create a self-checking test bench with expected outputs that
correspond to your inputs. The input setup and output delay numbers that were
entered into the Initialize Timing dialog when you started the waveform editor are
evaluated against actual results when the design is simulated. This can be useful in the
Simulate Post- Place & Route HDL Model process, to verify that the design behaves
as expected in the target device both in terms of functionality and timing.
To create a self-checking test bench, you can edit output transitions manually, or you
can run the Generate Expected Results process:
1. Select the testbench.tbw file in the Sources in Project window.
2. Double-click the Generate Expected Simulation Results process. This process
converts the TBW into HDL and then simulates it in a background process.
3. The Expected Results dialog box will open. Select Yes to post the results in the
waveform editor.

4. Click the + to expand the COUNT_OUT bus and view the transitions that
correspond to the Output Valid Delay time (yellow cells) in the Initialize Timing
dialog box.
5. Select File _ Save to save the waveform.
6. Close the Waveform Editor.Now that you have a test bench, you are ready to
simulate your design.
Simulating the Behavioral Model (ISE Simulator):
If you are using ISE Base or Foundation, you can simulate your design with the ISE
Simulator. If you wish to simulate your design with a ModelSim simulator, skip this
section and proceed to the Simulating the Behavioral Model (ModelSim) section.

Fig 4:Simulator Processes for Test Bench

Fig 5:Behavioral Simulation in ISE Simulator


To run the integrated simulation processes in ISE:
1. Select the test bench waveform in the Sources in Project window. You can see the
Xilinx ISE Simulator processes in the Processes for Source window.
2. Double-click the Simulate Behavioral Model process. The ISE Simulator opens
and runs the simulation to the end of the test bench.
3. To see your simulation results, select the test bench tab and zoom in on the
transitions. You can use the zoom icons in the waveform view, or right click and
select a zoom command.The ISE window, including the waveform view.

4. Zoom in on the area between 300 ns and 900 ns to verify that the counter is
counting up and down as directed by the stimulus on the DIRECTION port.
5. Close the waveform view window. You have completed simulation of your design
using the ISE Simulator. Skip past the ModelSim section below and proceed to the
Creating and Editing Timing and Area
Constraintssection.
Simulating the Behavioral Model (ModelSim):
If you have a ModelSim simulator installed, you can simulate your design using the
integrated ModelSim flow. You can run processes from within ISE which launches
the installed ModelSim simulator.
To run the integrated simulation processes in ISE:
1. Select the test bench in the Sources in Project window. You can see
ModelSim Simulator processes in the Processes for Source window in Fig 6.

Fig 6: Simulator Processes for Test Bench

Fig 7:Behavioral Simulation in ModelSim


2. Double-click the Simulate Behavioral Model process. The ModelSim simulator
opens and runs your simulation to the end of the test bench.
The ModelSim window, including the waveform, should look like Fig 7.
To see your simulation results, view the Wave window.
1. Right-click in the Wave window and select a zoom command.
2. Zoom in on the area between 300 ns and 900 ns to verify that the counter is
counting up
and down as directed by the stimulus on the DIRECTION port.
3. Close the ModelSim window.

RESULT:

Expt.No:
Date :

STUDY OF SYNTHESIS TOOLS

AIM:
To study the Synthesis tools.
THEORY:
Now that you have created the source files, verified the designs behavior with
simulation,and added constraints, you are ready to synthesize and implement the
design.
Implementing the Design:
1. Select the counter source file in the Sources in Project window.
2. In the Processes for Source window, click the + sign next to
Implement Design. The Translate, Map, and Place & Route processes are displayed.
Expand those processes as well by clicking on the + sign. You can see that there are
many sub-processes and options that can be run during design implementation.
3. Double-click the top level Implement Design process.ISE determines the current
state of your design and runs the processes needed to pull your
design through implementation. In this case, ISE runs the Translate, Map and PAR
processes. Your design is now pulled through to a placed-and-routed state. This
feature is called the pull through model.
4. After the processes have finished running, notice the status markers in the
Processes for Source window. You should see green checkmarks next to several of the
processes, indicating that they ran successfully. If there are any yellow exclamation
points, check the warnings in the Console tab or the Warnings tab within the
Transcript window. If a red X appears next to a process, you must locate and fix the
error before you can continue.
Verification of Synthesis:
Your synthesized design can be viewed as a schematic in the Register Transfer Level
(RTL) Viewer. The schematic view shows gates and elements independent of the
targeted Xilinx device.
1. In the Processes for Source window, double-click View RTL Schematic
found in the Synthesize - XST process group. The top level schematic
representation of your synthesized design opens in the workspace.
2. Right-click on the symbol and select Push Into the Selected Instance to view the
schematic in detail.
The Design tab appears in the Sources in Project window, enabling you to view the
design hierarchy. In the schematic, you can see the design components you created in
the HDL source, and you can push into symbols to view increasing levels of detail.
3. Close the schematic window.

RESULT:

Figure 1: Floorplanner View - Detailed View

Figure 2: Design Summary View

Expt.No:
Date :

STUDY OF PLACE AND ROOT AND BACK


ANNOTATION FOR FPGAS.

AIM:
To study the Place and Root and Back annotation for FPGAs.
THEORY:
After implementation is complete, you can verify your design before downloading it
to a device.
Viewing Placement:
In this section, you will use the Floor planner to verify your pin outs and placement.
Floor planner is also very useful for creating area groups for designs.
1. Select the counter source file in the Sources in Project window.
2. Click the + sign to expand the Place & Route group of processes.
3. Double-click the View/Edit Placed Design (Floorplanner) process. The
Floorplanner view opens.
4. Select View _ Zoom _ ToBox and then use the mouse to draw a box around the
counter instance, shown in green on the right side of the chip.
5. This Fig 1 shows where the entire design was placed. Click on any of the
components listed in the Design Hierarchy window to see where each component is
placed.
6. Zoom in to the right side of the chip even more, and place your mouse over the
K13pad. You can see that your pinout constraint was applied - the DIRECTION pin is
placed at K13.
7. Close the Floorplanner without saving.
Viewing Resource Utilization in Reports:
Many ISE processes produce summary reports which enable you to check information
about your design after each process is run. Detailed reports are available from the
Processes for Source window. You can also view summary information and access
most often-utilized reports in the Design Summary.
1. Click on the Design Summary tab at the bottom of the window. If you closed the
summary during this tutorial, you can reopen it by double-clicking the View Design
Summary process.

Figure 3: Timing Analyzer - Timing Summary

Figure 4: FPGA Editor - Detailed View


2. In the Device Utilization Summary section, observe the number of Slice Flip Flops
that were used during implementation. You should see 4 flip flops, since you
implemented a 4-bit counter.
3. To see other reports, scroll to the bottom of the Design Summary. You can click on
a report from here to view it in the ISE Text Editor.
Timing Closure:
In this section, you will run timing analysis on your design to verify that your timing
constraints were met. Timing closure is the process of working on your design to
ensure that it meets your necessary timing requirements. ISE provides several tools to
assist with timing closure.
1. In the Processes for Source window, under the Place & Route group of processes,
expand the Generate Post-Place & Route Static Timing group by clicking the
+sign.

2. Double-click the Analyze Post-Place & Route Static Timing process. The Timing
Analyzer opens.
3. To analyze the design, select Analyze Against Timing Constraints. The Analyze
with Timing Constraints dialog box opens.
4. Click OK. When analysis is complete, the timing report opens.
5. Select Timing summary from the Timing Report Description tree in the left
window. This displays the summary section of the timing report, where you can see
that no timing errors were reported.
6. Close the Timing Analyzer without saving.
Viewing the Placed and Routed Design:
In this section, you will use the FPGA Editor to view the design. You can view your
design on the FPGA device, as well as edit the placement and routing with the FPGA
Editor.
1. Double-click the View/Edit Routed Design (FPGA Editor) process found in the
Place & Route group of processes. Your implemented design opens in the FPGA
Editor.
2. Look in the List window to examine your design components.
3. Click on the COUNT_OUT K12 IOB in the List window to select the row. This is
one of the outputs in your design.
4. With the COUNT_OUT K12 row selected, select View _ Zoom Selection. In the
editor window, you can see the COUNT_OUT<0> IOB highlighted in red.
5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB. You should
see Fig 4.
6. Enlarge the window and zoom in so you can see more detail. This view shows the
inside of an FPGA at the lowest viewable level. The blue line shows the route that is
used through the IOB. The red lines show the routes that are available.

Figure 5: Simulator Processes for Test Bench

Figure 6: Timing Simulation in ISE Simulator

7. Verify that the signal goes to the pad as an output.


8. Close the FPGA Editor.
Timing Simulation (ISE Simulator):
You can verify that your design meets your timing requirements by running a timing
simulation. You can use the same test bench waveform that was used earlier in the
design flow for behavioral simulation.
When running timing simulation, the ISE tools create a structural HDL file which
includes timing information available after Place and Route is run. The simulator will
run on a model that is created based on the design to be downloaded to the FPGA.
If you are using ISE Base or Foundation, you can simulate your design with the ISE
Simulator. To simulate your design with ModelSim, skip to the Timing Simulation
(ModelSim) section.
To run the integrated simulation processes:
1. Select the test bench waveform in the Sources in Project window. You can see the
ISE Simulator processes in the Processes for Source window.
2. Double-click the Simulate Post-Place & Route Model process.
This process generates a timing-annotated netlist from the implemented design and
simulates it. The resulting simulation is displayed in the Waveform Viewer. These
results look different than those you saw in the behavioral simulation earlier in this
tutorial. These results show timing delays.
3. To see your simulation results, zoom in on the transitions and view the area
between 300 ns and 900 ns to verify that the counter is counting up and down as
directed by the stimulus on the DIRECTION port.
4. Zoom in again to see the timing delay between a rising clock edge and an output
transition.
5. Click the Measure Marker button and then click near the 300 ns mark. Drag the
second marker to the point where the output becomes stable to see the time delay
between the clock edge and the transition.
6. Close the waveform view window.You have completed timing simulation of your
design using the ISE Simulator. Skip past the ModelSim section below, and proceed
to the Creating Configuration Data section.
Timing Simulation (ModelSim):
If you have a ModelSim simulator installed, you can simulate your design using
theintegrated ModelSim flow. You can run processes from within ISE which launches
the installed ModelSim simulator.
1. To run the integrated simulation processes, select the test bench in the Sources in
Project window. You can see the ModelSim Simulator processes in the Processes for
Source window.

Figure 7: Simulator Processes for Test Bench

Figure 8: Timing Simulation in ModelSim


2. Double-click the Simulate Post-Place & Route VHDL/Verilog Model process.
3. Zoom in on the area between 300 ns and 900 ns to verify that the counter is
counting up
and down as directed by the stimulus on the DIRECTION port.
4. Zoom in on the rising clock edges to see that the output transitions occur slightly
later
due to the timing delay.
5. Close the ModelSim window.

RESULT:

Expt.No:
Date :
AIM:

BASIC LOGIC GATES

To implement basic logic gates using Verilog HDL.


APPARATUS REQUIRED:

PC with Windows XP.


XILINX, ModelSim software.
FPGA kit.
RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system.


Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim or
Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.

AND Gate:

Output:
#
#
#
#
#
#
#
#
#

AND Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
0
1
0
0
1
1
1
-------------------------------------------------

PROGRAM:
AND Gate:
// Module Name: Andgate
module Andgate(i1, i2, out);
input i1;
input i2;
output out;
and (out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Andgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tAND Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
OR Gate:

Output:
#
#
#
#
#
#
#
#
#

OR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
1
1
0
1
1
1
1
------------------------------------------------

PROGRAM:
OR Gate:
// Module Name: Orgate
module Orgate(i1, i2, out);
input i1;
input i2;
output out;
or(out,i1,i2);
endmodule
// Module Name: Simulus.v
module Simulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Orgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin

$display("\t\t\t\tOR Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
NAND Gate:

Output:
#
#
#
#
#
#
#
#
#

NAND Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
1
0
1
1
1
0
1
1
1
0
------------------------------------------------

NAND Gate:
// Module Name: Nandgate
module Nandgate(i1, i2, out);
input i1;
input i2;
output out;
nand(out,i1,i2);

endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Nandgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tNAND Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
NOR Gate:

Output:
#
#
#
#

NOR Gate
-----------------------------------------------Input1
Input2
Output
------------------------------------------------

#
#
#
#
#

0
0
1
0
1
0
1
0
0
1
1
0
------------------------------------------------

NOR Gate:
// Module Name: Norgate
module Norgate(i1, i2, out);
input i1;
input i2;
output out;
nor(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Norgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tNOR Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin

i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule
XOR Gate:

Output:
#
#
#
#
#
#
#
#
#

XOR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
0
0
1
1
1
0
1
1
1
0
-------------------------------------------------

XOR Gate:
// Module Name: Xorgate
module Xorgate(i1, i2, out);
input i1;
input i2;
output out;
xor(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;

// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Xorgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tXOR Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule

XNOR Gate:

Output:
#
#
#
#
#
#
#
#
#

XNOR Gate
-----------------------------------------------Input1
Input2
Output
-----------------------------------------------0
0
1
0
1
0
1
0
0
1
1
1
------------------------------------------------

XNOR Gate:
// Module Name: Xnorgate
module Xnorgate(i1, i2, out);
input i1;
input i2;
output out;
xnor(out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Xnorgate uut (
.i1(i1),
.i2(i2),
.out(out)
);
initial
begin
$display("\t\t\t\tXNOR Gate");
$display("\t\t--------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Output");
$display("\t\t--------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);
#4 $display("\t\t--------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;

#1 $stop;
end
endmodule
Not Gate:

Output:
#
#
#
#
#
#
#

NOT Gate
--------------------------Input
Output
--------------------------0
1
1
0
---------------------------

NOT Gate:
// Module Name: Notgate
module Notgate(in, out);
input in;
output out;
not(out,in);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg in;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Notgate uut (
.in(in),
.out(out)
);
initial
begin
$display("\t\t NOT Gate");
$display("\t\t------------------------");

$display("\t\tInput\t\tOutput");
$display("\t\t------------------------");
$monitor("\t\t %b\t\t %b",in,out);
#2 $display("\t\t------------------------");
end
initial
begin
in=0;
#1 in=1;
#1 $stop;
end
endmodule
Buffer:

Output:
#
#
#
#
#
#
#

BUFFER
--------------------------Input
Output
--------------------------0
0
1
1
---------------------------

Buffer:
// Module Name: Buffer
module Buffer(in, out);
input in;
output out;
buf(out,in);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg in;
// Outputs

wire out;
// Instantiate the Unit Under Test (UUT)
Buffer uut (
.in(in),
.out(out)
);
initial
begin
$display("\t\t
BUFFER");
$display("\t\t------------------------");
$display("\t\tInput\t\tOutput");
$display("\t\t------------------------");
$monitor("\t\t %b\t\t %b",in,out);
#2 $display("\t\t------------------------");
end
initial
begin
in=0;
#1 in=1;
#1 $stop;
end
endmodule

RESULT:

Expt. No:
Date :
AIM:

HALF ADDER AND FULL ADDER

To implement half adder and full adder using Verilog HDL.


APPARATUS REQUIRED:

PC with Windows XP
XILINX, ModelSim software.
FPGA kit
RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system.


Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim or
Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.

Half Adder:

Output:
#
#
#
#
#
#
#
#
#

Half Adder
-----------------------------------------------------------------Input1
Input2
Carry
Sum
-----------------------------------------------------------------0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
0
------------------------------------------------------------------

PROGRAM:
Half Adder:
// Module Name: HalfAddr
module HalfAddr(sum, c_out, i1, i2);
output sum;
output c_out;
input i1;
input i2;
xor(sum,i1,i2);
and(c_out,i1,i2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
// Outputs
wire sum;
wire c_out;
// Instantiate the Unit Under Test (UUT)
HalfAddr uut (
.sum(sum),
.c_out(c_out),
.i1(i1),
.i2(i2)
);
initial
begin
$display("\t\t\t\t Half Adder");
$display("\t\t----------------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Carry\t\t Sum");
$display("\t\t----------------------------------------------");
$monitor("\t\t %b\t\t %b\t\t %b\t\t %b",i1,i2,c_out,sum);
#4 $display("\t\t----------------------------------------------");
end
initial
begin
i1=1'b0; i2=1'b0;
#1 i2=1'b1;
#1 i1=1'b1; i2=1'b0;
#1 i1=1'b1; i2=1'b1;
#1 $stop;
end
endmodule

Full Adder:

Output:
#
----------#
Sum
#
----------#
#
#
#
#
#
#
#
#
------------

Full Adder
------------------------------------------------------------------------------------i1

i2

C_in

C_out

------------------------------------------------------------------------------------0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
-------------------------------------------------------------------------------------

Full Adder:
// Module Name: FullAddr
module FullAddr(i1, i2, c_in, c_out, sum);
input i1;
input i2;
input c_in;
output c_out;
output sum;
wire s1,c1,c2;
xor n1(s1,i1,i2);
and n2(c1,i1,i2);
xor n3(sum,s1,c_in);
and n4(c2,s1,c_in);

or n5(c_out,c1,c2);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i1;
reg i2;
reg c_in;
// Outputs
wire c_out;
wire sum;
// Instantiate the Unit Under Test (UUT)
FullAddr uut (
.i1(i1),
.i2(i2),
.c_in(c_in),
.c_out(c_out),
.sum(sum)
);
initial
begin
$display("\t\t\t\t\t\tFull Adder");
$display("\t\t----------------------------------------------------------------");
$display("\t\ti1\t\ti2\t\tC_in\t\t\tC_out\t\tSum");
$display("\t\t----------------------------------------------------------------");
$monitor("\t\t%b\t\t%b\t\t%b\t\t\t%b\t\t%b",i1,i2,c_in,c_out,sum);
#9 $display("\t\t------------------------------------------------------------------");
end
initial begin
i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 0;
#1 i1 = 0;i2 = 0;c_in = 1;
#1 i1 = 0;i2 = 1;c_in = 0;
#1 i1 = 0;i2 = 1;c_in = 1;
#1 i1 = 1;i2 = 0;c_in = 0;
#1 i1 = 1;i2 = 0;c_in = 1;
#1 i1 = 1;i2 = 1;c_in = 0;
#1 i1 = 1;i2 = 1;c_in = 1;
#2 $stop;
end
endmodule
RESULT:

Expt. No:
Date

HALF SUBTRACTOR & FULL SUBTRACTOR, 4


BIT MULTIPLIER, 8 BIT ADDER

AIM:
To implement half subtractor and full subtractor using Verilog HDL.
APPARATUS REQUIRED:

PC with Windows XP
XILINX, ModelSim software.
FPGA kit
RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system.


Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim or
Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.

Half Subtractor:

Output:
#
#
#
#
#
#
#
#
#

Half Subtractor
-----------------------------------------------------------------------Input1
Input2
Borrow
Difference
------------------------------------------------------------------------0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
------------------------------------------------------------------------

PROGRAM:
Half Subtractor:
// Module Name: HalfSub
module HalfSub(i0, i1, bor, dif);
input i0;
input i1;
output bor;
output dif;
wire i0n;
not(i0n,i0);
xor(dif,i0,i1);
and(bor,i0n,i1);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0;
reg i1;
// Outputs
wire bor;
wire dif;
// Instantiate the Unit Under Test (UUT)
HalfSub uut (
.i0(i0),
.i1(i1),
.bor(bor),
.dif(dif)
);
initial
begin
$display("\t\t\t\t\tHalf Subtractor");
$display("\t\t----------------------------------------------------------");
$display("\t\tInput1\t\t Input2\t\t Borrow\t\t Difference");
$display("\t\t----------------------------------------------------------");
$monitor("\t\t\t%b\t\t%b\t\t%b\t\t%b",i0,i1,bor,dif);
#4 $display("\t\t-----------------------------------------------------------");
end
initial
begin
i0=1'b0; i1=1'b0;
#1 i1=1'b1;
#1 i0=1'b1; i1=1'b0;
#1 i0=1'b1; i1=1'b1;
#1 $stop;
end

endmodule
Full Subtractor:

Output:
#
#
----------#
Difference
#
----------#
#
#
#
#
#
#
#
#
------------

Full Subtractor
------------------------------------------------------------------------------------B_in

I1

i0

B_out

------------------------------------------------------------------------------------0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
0
1
1
0
0
1
0
0
1
1
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
-------------------------------------------------------------------------------------

Full Subtractor:
// Module Name: FullSub
module FullSub(b_in, i1, i0, b_out, dif);
input b_in;
input i1;
input i0;
output b_out;
output dif;
assign {b_out,dif}=i0-i1-b_in;
endmodule

// Module Name: Stimulus.v


module Stimulus_v;
// Inputs
reg b_in;
reg i1;
reg i0;
// Outputs
wire b_out;
wire dif;
// Instantiate the Unit Under Test (UUT)
FullSub uut (
.b_in(b_in),
.i1(i1),
.i0(i0),
.b_out(b_out),
.dif(dif)
);
initial
begin
$display("\t\t\t\t\t\tFull Subtractor");
$display("\t\t------------------------------------------------------------------------");
$display("\t\tB_in\t\tI1\t\ti0\t\t\tB_out\t\tDifference");
$display("\t\t------------------------------------------------------------------------");
$monitor("\t\t%b\t\t%b\t\t%b\t\t\t %b\t\t\t %b",b_in,i1,i0,b_out,dif);
#9 $display("\t\t------------------------------------------------------------------------");
end
initial begin
// Initialize Inputs
b_in = 0;i1 = 0;i0 = 0;
#1 b_in = 0;i1 = 0;i0 = 0;
#1 b_in = 0;i1 = 0;i0 = 1;
#1 b_in = 0;i1 = 1;i0 = 0;
#1 b_in = 0;i1 = 1;i0 = 1;
#1 b_in = 1;i1 = 0;i0 = 0;
#1 b_in = 1;i1 = 0;i0 = 1;
#1 b_in = 1;i1 = 1;i0 = 0;
#1 b_in = 1;i1 = 1;i0 = 1;
#2 $stop;
end
endmodule
module Multiplier_verilog(Nibble1, Nibble2,Result);
input Nibble1, Nibble2;

output Result;

assign Result= (unsigned(Nibble1) * unsigned(Nibble2));


end module
Simulation Waveform

8 BIT ADDER
module 8bitadder_carryinput(A, B, Carry_in, SUM);
input [7:0] A;
input [7:0] B;
input Carry_in;
output [7:0] SUM;
assign SUM = A + B + Carry_in;
endmodule

RESULT:

Expt. No:
Date :

MULTIPLEXER & DEMULTIPLEXER

AIM:
To implement Multiplexer & Demultiplexer using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP.


XILINX, ModelSim software.
FPGA kit.
RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system.


Write the Verilog code for above system.
Enter the Verilog code in Xilinx software.
Check the syntax and simulate the above verilog code (using ModelSim or
Xilinx) and verify the output waveform as obtained.
Implement the above code in Spartan III using FPGA kit.

Multiplexer:
Output:
#
#
#
#
#
#
#
#
#
#
#

4to1 Multiplexer
----------------------------------------------Input=1011
----------------------------------------------Selector
Output
----------------------------------------------{0,0}
1
{1,0}
0
{0,1}
1
{1,1}
1
-----------------------------------------------

PROGRAM:
Multiplexer:
// Module Name: Mux4to1
module Mux4to1(i0, i1, i2, i3, s0, s1, out);
input i0;
input i1;
input i2;
input i3;
input s0;
input s1;
output out;
wire s1n,s0n;
wire y0,y1,y2,y3;
not (s1n,s1);
not (s0n,s0);
and (y0,i0,s1n,s0n);
and (y1,i1,s1n,s0);
and (y2,i2,s1,s0n);
and (y3,i3,s1,s0);
or (out,y0,y1,y2,y3);
endmodule
// Module Name: Stimulus.v
module Stimulus_v;
// Inputs
reg i0;
reg i1;
reg i2;
reg i3;
reg s0;
reg s1;
// Outputs
wire out;
// Instantiate the Unit Under Test (UUT)
Mux4to1 uut (
.i0(i0),
.i1(i1),
.i2(i2),

.i3(i3),
.s0(s0),
.s1(s1),
.out(out)
);

Demultiplexer:

initial
begin
$display("\t\t\t 4to1 Multiplexer");
$display("\t\t------------------------------------");
#1 $display("\t\t\t Input=%b%b%b%b",i0,i1,i2,i3);
$display("\t\t------------------------------------");
$display("\t\tSelector\t\t\t\tOutput");
$display("\t\t------------------------------------");
$monitor("\t\t{%b,%b}\t\t\t\t\t%b",s0,s1,out);
#4 $display("\t\t------------------------------------");
end
initial
begin
i0=1; i1=0; i2=1; i3=1;
#1 s0=0; s1=0;
#1 s0=1; s1=0;
#1 s0=0; s1=1;
#1 s0=1; s1=1;
#1 $stop;
end
endmodule
Demultiplexer:
// Module Name: Dux1to4
module Dux1to4(in, s0, s1, out0, out1, out2, out3);
input in;
input s0;
input s1;

output out0;
output out1;
output out2;
output out3;
wire s0n,s1n;
not(s0n,s0);
not(s1n,s1);
and (out0,in,s1n,s0n);
and (out1,in,s1n,s0);
and (out2,in,s1,s0n);
and (out3,in,s1,s0);
endmodule
// Module Name: stimulus.v
module stimulus_v;
// Inputs
Output:
#
#
#
#
#
#
#
#
#
#
#

1to4 Demultiplexer
----------------------------------------------Input=1
----------------------------------------------Status
Output
----------------------------------------------{0,0}
1000
{0,1}
0100
{1,0}
0010
{1,1}
0001
---------------------------------------------

reg in;
reg s0;
reg s1;
// Outputs
wire out0;
wire out1;
wire out2;
wire out3;
// Instantiate the Unit Under Test (UUT)
Dux1to4 uut (
.in(in),
.s0(s0),

.s1(s1),
.out0(out0),
.out1(out1),
.out2(out2),
.out3(out3)
);
initial
begin
$display("\t\t 1to4 Demultiplexer");
$display("\t\t------------------------------------");
#1 $display("\t\t\t\tInput=%b",in);
$display("\t\t------------------------------------");
$display("\t\tStatus\t\t\t\tOutput");
$display("\t\t------------------------------------");
$monitor("\t\t{%b,%b}\t\t\t\t%b%b%b%b",s1,s0,out0,out1,out2,out3);
#4 $display("\t\t------------------------------------");
end
initial
begin
in=1;
#1 s1=0;s0=0;
#1 s1=0;s0=1;
#1 s1=1;s0=0;
#1 s1=1;s0=1;
#1 $stop;
end
endmodule

RESULT:

Expt. No:
Date:
AIM:

DESIGN OF TRAFFIC LIGHT CONTROLLER

To design a simple traffic light controller for a 4 way crossing.


using Verilog HDL
APPARATUS REQUIRED:

PC with Windows XP.


XILINX, ModelSim software.
FPGA kit.
RS 232 cable.

WORKING:
A traffic light controller works by giving GREEN signal to each road one by one for
determined period of time, the YELLOW signal are generated for very short duration
to intimate the closing of GREEN signal.
Step 1: We would design a simple 8 state counter, and each state would
control the GREEN &YELLOW LEDs.
Step 2: Each GREEN state would stay in state of 10 clock cycles, the
YELLOW state would remain in its state for 3 clock cycles only.
Step 3: The main state counter would increment after 10 clock cycles if
he is in
GREEN state, but it would increment in 3 clock cycles
only if he is in
YELLOW state.
Step 4: There would be state decoders which will identify the GREEN &
YELLOW states.
Step 5: For controlling the RED signal, it would not be NOR operation of GREEN
& YELLOW signals of its junction. As if any of the GREEN & YELLOW lights are
ON, then the RED should go OFF, else it should be ON.
PROGRAM :
Traffic Light Controller:
module Traffic_Top_FPGA(
clock,Rst,G3,R4,R2,R1,R3,Y2,Y3,G2,Y4,Y1,G1,G4);
input clock,Rst;
output G3,R4,R2,R1,R3,Y2,Y3,G2;
output Y4,Y1,G1,G4;
wire w18,w19,w20,w21,w22,w23,w24,w25;
wire w26,w27,w28,w29,w30,w31,w32,w33;
wire w34,w35,w36,w37,w38,w39,w40,w41;
wire w42,w43,w44,w45,w46,w47,w48,w49;
wire w50,w51,w52,w53,w54,w55,w56,w57;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;

wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112,w113;
wire w114,w115,w116,w117,w118,w119,w120,w121;
wire w122,w123,w124,w125,w126,w127,w128,w129;
wire w130,w131,w132,w133,w134,w135,w136,w137;
wire w138,w139,w140,w141,w142,w143,w144,w145;
wire w146,w147,w148,w149,w150,w151,w152,w153;
wire w154,w155,w156,w157,w158,w159,w160,w161;
wire w162,w163,w164,w165,w166,w167,w168,w169;
wire w170,w171,w172,w173,w174,w175,w176,w177;
wire w178,w179,w180,w181,w182,w183,w184,w185;
wire w186,w187,w188,w189,w190,w191,w192,w193;
wire w194,w195,w196,w197,w198,w199,w200;
and and3_Tr1(w21,w18,w19,w20);
or or2_Tr2(w24,w22,w23);
or or2_Tr3(w25,Rst,w23);
dreg dreg101_Tr4(Y1,w27,w26,Rst,w15);
nor nor3_Tr5(w29,w28,w19,w20);
dreg dreg102_Tr6(G2,w31,w30,Rst,w15);
or or3_Tr7(w32,Y3,Y2,Y4);
nor nor2_Tr8(R1,G1,Y1);
nor nor3_Tr9(w33,w28,w18,w20);
or or2_Tr10(w34,Y1,w32);
dreg dreg103_Tr11(Y3,w36,w35,Rst,w15);
dreg dreg104_Tr12(G1,w38,w37,Rst,w15);
dreg dreg105_Tr13(Y4,w40,w39,Rst,w15);
dreg dreg106_Tr14(G3,w42,w41,Rst,w15);
nor nor2_Tr15(w43,w28,w19);
dreg dreg107_Tr16(Y2,w45,w44,Rst,w15);
dreg dreg108_Tr17(G4,w47,w46,Rst,w15);
nor nor3_Tr18(w48,w28,w18,w19);
and and2_Tr19(w39,w21,w49);
nor nor2_Tr20(w50,w28,w18);
nor nor2_Tr21(w51,w28,w20);
nor nor3_Tr22(w52,w28,w18,w19);
and and2_Tr23(w41,w19,w33);
and and2_Tr24(w26,w20,w48);
and and3_Tr25(w35,w50,w19,w20);
and and2_Tr26(w30,w18,w29);
and and3_Tr27(w44,w43,w18,w20);
not inv_Tr28(w49,w28);
nor nor2_Tr29(R4,G4,Y4);
nor nor2_Tr30(R2,G2,Y2);
nor nor2_Tr31(R3,G3,Y3);
not inv_Tr32(w53,w20);
and and2_Tr33(w37,w53,w52);
dreg dreg109_Tr34(w55,w56,w54,Rst,w15);

dreg dreg110_Tr35(w57,w58,w55,Rst,w15);
and and2_Tr36(w59,w58,w55);
and and2_Tr37(w54,w60,w28);
or or2_Tr38(w61,Rst,w59);
nor nor3_Tr39(w60,w18,w19,w20);
and and3_Tr40(w46,w51,w18,w19);
not inv_co1_Tr41(w62,w61);
xor xor2_co2_Tr42(w63,w20,w62);
xor xor2_co3_Tr43(w65,w28,w64);
xor xor2_co4_Tr44(w67,w19,w66);
dreg dreg67_co5_Tr45(w18,w69,w68,w61,w24);
xor xor2_co6_Tr46(w68,w18,w70);
and and2_co7_Tr47(w70,w19,w66);
dreg dreg68_co8_Tr48(w20,w71,w63,w61,w24);
dreg dreg69_co9_Tr49(w19,w72,w67,w61,w24);
and and2_co10_Tr50(w64,w18,w70);
and and2_co11_Tr51(w66,w20,w62);
dreg dreg70_co12_Tr52(w28,w73,w65,w61,w24);
dreg dreg7_Di13_Tr53(w23,w75,w74,Rst,w15);
and and2_Di14_Tr54(w74,w76,w77);
not inv_Di15_Tr55(w77,w78);
xor xor2_Tf1_Di16_Tr56(w79,w78,w34);
and and2_Tf2_Di17_Tr57(w80,w78,w34);
dreg dreg1_Tf3_Di18_Tr58(w78,w81,w79,Rst,w15);
xor xor2_Tf4_Di19_Tr59(w82,w76,w80);
and and2_Tf5_Di20_Tr60(w83,w76,w80);
dreg dreg1_Tf6_Di21_Tr61(w76,w84,w82,Rst,w15);
not inv_Di22_Tr62(w85,w25);
xor xor2_Di23_Tr63(w87,w86,w85);
xor xor2_Di24_Tr64(w90,w88,w89);
dreg dreg28_Di25_Tr65(w92,w93,w91,w25,w15);
xor xor2_Di26_Tr66(w96,w94,w95);
and and2_Di27_Tr67(w95,w92,w97);
dreg dreg29_Di28_Tr68(w86,w99,w98,w25,w15);
dreg dreg30_Di29_Tr69(w88,w101,w100,w25,w15);
mux mux_Di30_Tr70(w102,w96,w25,w22);
and and2_Di31_Tr71(w89,w86,w85);
dreg dreg31_Di32_Tr72(w22,w104,w103,w25,w15);
and and2_Di33_Tr73(w97,w88,w89);
mux mux_Di34_Tr74(w100,w90,w25,w22);
mux mux_Di35_Tr75(w98,w87,w25,w22);
dreg dreg32_Di36_Tr76(w94,w105,w102,w25,w15);
xor xor2_Di37_Tr77(w106,w92,w97);
mux mux_Di38_Tr78(w91,w106,w25,w22);
and and3_Di39_Tr79(w107,w99,w101,w93);
and and2_Di40_Tr80(w103,w94,w107);
not inv_co81(w108,Rst);
xor xor2_co82(w110,w109,w108);
xor xor2_co83(w112,w16,w111);
xor xor2_co84(w115,w113,w114);

dreg dreg111_co85(w117,w118,w116,Rst,clock);
xor xor2_co86(w116,w117,w119);
and and2_co87(w119,w113,w114);
dreg dreg112_co88(w109,w120,w110,Rst,clock);
dreg dreg113_co89(w113,w121,w115,Rst,clock);
and and2_co90(w111,w122,w123);
and and2_co91(w114,w109,w108);
dreg dreg114_co92(w16,w124,w112,Rst,clock);
dreg dreg114_co93(w126,w127,w125,Rst,clock);
xor xor2_co94(w125,w126,w128);
xor xor2_co95(w131,w129,w130);
dreg dreg114_co96(w129,w132,w131,Rst,clock);
xor xor2_co97(w135,w133,w134);
dreg dreg114_co98(w133,w136,w135,Rst,clock);
dreg dreg114_co99(w122,w138,w137,Rst,clock);
xor xor2_co100(w137,w122,w123);
and and2_co101(w128,w117,w119);
and and2_co102(w130,w126,w128);
and and2_co103(w134,w129,w130);
and and2_co104(w123,w133,w134);
not inv_co105(w139,Rst);
xor xor2_co106(w141,w140,w139);
xor xor2_co107(w143,w15,w142);
xor xor2_co108(w146,w144,w145);
dreg dreg111_co109(w148,w149,w147,Rst,w17);
xor xor2_co110(w147,w148,w150);
and and2_co111(w150,w144,w145);
dreg dreg112_co112(w140,w151,w141,Rst,w17);
dreg dreg113_co113(w144,w152,w146,Rst,w17);
and and2_co114(w142,w153,w154);
and and2_co115(w145,w140,w139);

Output:
dreg dreg114_co116(w15,w155,w143,Rst,w17);
dreg dreg114_co117(w157,w158,w156,Rst,w17);

xor xor2_co118(w156,w157,w159);
xor xor2_co119(w162,w160,w161);
dreg dreg114_co120(w160,w163,w162,Rst,w17);
xor xor2_co121(w166,w164,w165);
dreg dreg114_co122(w164,w167,w166,Rst,w17);
dreg dreg114_co123(w153,w169,w168,Rst,w17);
xor xor2_co124(w168,w153,w154);
and and2_co125(w159,w148,w150);
and and2_co126(w161,w157,w159);
and and2_co127(w165,w160,w161);
and and2_co128(w154,w164,w165);
not inv_co129(w170,Rst);
xor xor2_co130(w172,w171,w170);
xor xor2_co131(w174,w17,w173);
xor xor2_co132(w177,w175,w176);
dreg dreg111_co133(w179,w180,w178,Rst,w16);
xor xor2_co134(w178,w179,w181);
and and2_co135(w181,w175,w176);
dreg dreg112_co136(w171,w182,w172,Rst,w16);
dreg dreg113_co137(w175,w183,w177,Rst,w16);
and and2_co138(w173,w184,w185);
and and2_co139(w176,w171,w170);
dreg dreg114_co140(w17,w186,w174,Rst,w16);
dreg dreg114_co141(w188,w189,w187,Rst,w16);
xor xor2_co142(w187,w188,w190);
xor xor2_co143(w193,w191,w192);
dreg dreg114_co144(w191,w194,w193,Rst,w16);
xor xor2_co145(w197,w195,w196);
dreg dreg114_co146(w195,w198,w197,Rst,w16);
dreg dreg114_co147(w184,w200,w199,Rst,w16);
xor xor2_co148(w199,w184,w185);
and and2_co149(w190,w179,w181);
and and2_co150(w192,w188,w190);
and and2_co151(w196,w191,w192);
and and2_co152(w185,w195,w196);
endmodule

RESULT:

Expt No:
Date :

IMPLEMENTATION OF SERIAL ADDER

AIM:
To design pipeline Serial Adder module for adding two 8-bit numbers using
Verilog HDL
APPARATUS REQUIRED:

PC with Windows XP.


XILINX, Modelsim software.
FPGA kit.
RS 232 cable.

WORKING:
Step1: Two 8-bit numbers from A, B inputs are stored into two 8-bit shift registers
by activating the LOAD signal.
Step2: These registered inputs from both registers are shifted serially,
From LSB to MSB bits into the 1-bit full adder section by the
arrival of
each clock pulse with the LOAD signal as low.
Step3: The carry_out from full adder section is feed back as carry_in to
the same
full adder section and the sum Output bits from the full
adder section are entered
as serially into the serial in parallel out
shift register by the arrival of each
clock pulse.
Step4: The addition process would take 8 clock cycles to complete. The
sum and
carry out bits are again stored into Parallel in parallel out
register, by the arrival of
the terminal count from the divide by 8
counter sections these sum and carry
bits are appeared on out put LEDs.
Serial adder

PROGRAM:
Serial Adder:
module SERIALADDER_TOP(
RST,LOAD,A3,A2,A0,A1,A5,A4,A6,A7,B7,B6,B4,B5,B1,B0,
B2,B3,clk1,S3,S4,S0,Cout,S2,S1,S7,S6,S5,Done);
input RST,LOAD,A3,A2,A0,A1,A5,A4;

input A6,A7,B7,B6,B4,B5,B1,B0;
input B2,B3,clk1;
output S3,S4,S0,Cout,S2,S1,S7,S6;
output S5,Done;
wire w50,w51,w52,w53,w54,w55,w56,w57;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;
wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112,w113;
wire w114,w115,w116,w117,w118,w119,w120,w121;
wire w122,w123,w124,w125,w126,w127,w128,w129;
wire w130,w131,w132,w133,w134,w135,w136,w137;
dreg #(12) dreg6(w32,w36,w34,w35,clk1);
mux #(10) mux(w34,w32,LOAD,LOAD);
or #(16) or2(w35,RST,Done);
dreg #(12) dreg7(w38,w39,w37,w31,clk1);
dreg #(12) dreg8(Cout,w49,w38,RST,Done);
or #(86) or21(w31,RST,LOAD);
mux #(12) mux_Sh1(w51,w50,A5,LOAD);
mux #(12) mux_Sh2(w53,w52,A6,LOAD);
dreg #(6) dreg2_Sh3(w54,w55,w51,RST,clk1);
dreg #(6) dreg1_Sh4(w52,w57,w56,RST,clk1);
mux #(12) mux_Sh5(w58,w54,A4,LOAD);
dreg #(6) dreg3_Sh6(w60,w61,w59,RST,clk1);
mux #(12) mux_Sh7(w56,RST,A7,LOAD);
dreg #(6) dreg1_Sh8(w50,w62,w53,RST,clk1);
mux #(12) mux_Sh9(w59,w63,A2,LOAD);
dreg #(6) dreg3_Sh10(w63,w65,w64,RST,clk1);
mux #(12) mux_Sh11(w64,w66,A3,LOAD);
mux #(12) mux_Sh12(w68,w67,A0,LOAD);
dreg #(6) dreg3_Sh13(w14,w69,w68,RST,clk1);
mux #(12) mux_Sh14(w70,w60,A1,LOAD);
dreg #(6) dreg3_Sh15(w67,w71,w70,RST,clk1);
dreg #(6) dreg3_Sh16(w66,w72,w58,RST,clk1);
mux #(12) mux_Sh17(w74,w73,B5,LOAD);
mux #(12) mux_Sh18(w76,w75,B6,LOAD);
dreg #(6) dreg2_Sh19(w77,w78,w74,RST,clk1);
dreg #(6) dreg1_Sh20(w75,w80,w79,RST,clk1);
mux #(12) mux_Sh21(w81,w77,B4,LOAD);
dreg #(6) dreg3_Sh22(w83,w84,w82,RST,clk1);
mux #(12) mux_Sh23(w79,RST,B7,LOAD);
dreg #(6) dreg1_Sh24(w73,w85,w76,RST,clk1);
mux #(12) mux_Sh25(w82,w86,B2,LOAD);
dreg #(6) dreg3_Sh26(w86,w88,w87,RST,clk1);
mux #(12) mux_Sh27(w87,w89,B3,LOAD);
mux #(12) mux_Sh28(w91,w90,B0,LOAD);

dreg #(6) dreg3_Sh29(w23,w92,w91,RST,clk1);


mux #(12) mux_Sh30(w93,w83,B1,LOAD);
dreg #(6) dreg3_Sh31(w90,w94,w93,RST,clk1);
dreg #(6) dreg3_Sh32(w89,w95,w81,RST,clk1);
not #(23) inv_Di33(w96,w31);
xor #(15) xor2_Di34(w98,w97,w96);
xor #(15) xor2_Di35(w101,w99,w100);
dreg #(2) dreg137_Di36(w103,w104,w102,w31,clk1);
xor #(15) xor2_Di37(w107,w105,w106);
and #(15) and2_Di38(w106,w103,w108);
dreg #(15) dreg138_Di39(w97,w110,w109,w31,clk1);
dreg #(2) dreg139_Di40(w99,w112,w111,w31,clk1);
mux #(12) mux_Di41(w113,w107,w31,Done);
and #(26) and2_Di42(w100,w97,w96);
dreg #(6) dreg140_Di43(Done,w115,w114,w31,clk1);
and #(26) and2_Di44(w108,w99,w100);
mux #(12) mux_Di45(w111,w101,w31,Done);
mux #(12) mux_Di46(w109,w98,w31,Done);
dreg #(17) dreg141_Di47(w105,w116,w113,w31,clk1);
xor #(15) xor2_Di48(w117,w103,w108);
mux #(12) mux_Di49(w102,w117,w31,Done);
and #(15) and3_Di50(w114,w118,w116,w32);
and #(15) and3_Di51(w118,w110,w99,w103);
dreg #(6) dreg108_Se52(w43,w119,w44,RST,clk1);
dreg #(6) dreg110_Se53(w41,w120,w42,RST,clk1);
dreg #(6) dreg111_Se54(w44,w121,w45,RST,clk1);
dreg #(6) dreg104_Se55(w45,w122,w46,RST,clk1);
dreg #(6) dreg105_Se56(w48,w123,w40,RST,clk1);
dreg #(6) dreg107_Se57(w46,w124,w47,RST,clk1);
dreg #(6) dreg105_Se58(w47,w125,w48,RST,clk1);
dreg #(6) dreg106_Se59(w42,w126,w43,RST,clk1);
xor #(26) xor2_fu60(w127,w14,w23);
and #(15) and2_fu61(w128,w14,w23);
xor #(15) xor2_fu62(w40,w127,w38);
and #(15) and2_fu63(w129,w127,w38);
or #(15) or2_fu64(w37,w129,w128);
dreg #(6) dreg116_SH65(S4,w130,w45,RST,Done);
dreg #(6) dreg117_SH66(S3,w131,w44,RST,Done);
dreg #(6) dreg118_SH67(S5,w132,w46,RST,Done);
dreg #(6) dreg119_SH68(S7,w133,w48,RST,Done);
dreg #(6) dreg120_SH69(S1,w134,w42,RST,Done);
dreg #(6) dreg121_SH70(S6,w135,w47,RST,Done);
dreg #(6) dreg122_SH71(S2,w136,w43,RST,Done);
dreg #(6) dreg123_SH72(S0,w137,w41,RST,Done);
endmodule
// Simulation parameters in Verilog Format
always
#1000 RST=~RST;
#2000 LOAD=~LOAD;

#4000 A3=~A3;
#8000 A2=~A2;
#16000 A0=~A0;
#32000 A1=~A1;
#64000 A5=~A5;
#128000 A4=~A4;
#256000 A6=~A6;
#512000 A7=~A7;
#1024000 B7=~B7;
#2048000 B6=~B6;
#4096000 B4=~B4;
#8192000 B5=~B5;
#16384000 B1=~B1;
#32768000 B0=~B0;
#65536000 B2=~B2;
#131072000 B3=~B3;
#1000 clk1=~clk1;
// Simulation parameters
// RST CLK 10 10
// LOAD CLK 20 20
// A3 CLK 40 40
// A2 CLK 80 80
// A0 CLK 160 160
// A1 CLK 320 320
// A5 CLK 640 640
// A4 CLK 1280 1280
// A6 CLK 2560 2560
// A7 CLK 5120 5120
// B7 CLK 10240 10240
// B6 CLK 20480 20480
// B4 CLK 40960 40960
// B5 CLK 81920 81920
// B1 CLK 163840 163840
// B0 CLK 327680 327680
// B2 CLK 655360 655360
// B3 CLK 1310720 1310720
// clk1 CLK 10.00 10.00
Output:

RESULT:

Expt No:
Date :

IMPLEMENTATION OF PARALLEL PIPELINE


ADDER & SUBTRACTOR

AIM:
To design pipelined Adder and Sub tractor for two 8-bit numbers using
Verilog HDL.
APPARATUS REQUIRED:

PC with Windows XP.


XILINX, Modelsim software.
FPGA kit.
RS 232 cable.

WORKING:
The adder/subtractor works on the principle of addition of 2s complement input with
another input for subtraction.
Step1: Circuit loads two 8-bit numbers from A, B inputs and stores these two
numbers in two 8-bit registers.
Step2: The registered inputs from B- reg and its complements are applied to the
multiplexer section. By using the selection line Add/Sub of mux it selects one of the
B inputs.
Step3: Multiplexer output is complimented form of B when selection
line as
sub and same inputs of B when selection line as add.
Step4: Both registered outputs are applied to the parallel adder section in first clock
cycle, and result is stored in 9-bit register and
registered output appears
on out put LEDs.
Step5: Circuit acts as adder when selection line is zero and acts as
Subtractor when selection line is one.
BLOCK DIAGRAM:

PROGRAM:
module Adder_Subtractor_Top( B5,addbsub,clk1,RST,A7,A6,A5,A4,
A3,A2,A1,B7,B6,B4,B3,B2,
B1,B0,A0,Q7,COUT,Q0,Q1,Q2,
Q3,Q4,Q5,Q6);
input B5,addbsub,clk1,RST,A7,A6,A5,A4;
input A3,A2,A1,B7,B6,B4,B3,B2;
input B1,B0,A0;

output Q7,COUT,Q0,Q1,Q2,Q3,Q4,Q5;
output Q6;
wire w68,w69,w70,w71,w72,w73,w74,w75;
wire w76,w77,w78,w79,w80,w81,w82,w83;
wire w84,w85,w86,w87,w88,w89,w90,w91;
wire w92,w93,w94,w95,w96,w97,w98,w99;
wire w100,w101,w102,w103,w104,w105,w106,w107;
wire w108,w109,w110,w111,w112,w113,w114,w115;
wire w116,w117,w118,w119,w120,w121,w122,w123;
wire w124,w125,w126,w127,w128,w129,w130;
not #(17) inv(w21,RST);
dreg #(12) dreg2(w23,w24,w22,RST,clk1);
not #(10) inv(w66,w23);
mux #(10) mux(COUT,w23,w66,addbsub);
not #(10) inv(w67,w21);
mux #(17) mux(w50,w67,w21,addbsub);
dreg #(3) dreg16_re1(w16,w68,B4,RST,clk1);
dreg #(3) dreg17_re2(w15,w69,B3,RST,clk1);
dreg #(3) dreg18_re3(w13,w70,B0,RST,clk1);
dreg #(3) dreg19_re4(w12,w71,B1,RST,clk1);
dreg #(3) dreg20_re5(w14,w72,B2,RST,clk1);
dreg #(3) dreg21_re6(w18,w73,B6,RST,clk1);
dreg #(3) dreg22_re7(w19,w74,B7,RST,clk1);
dreg #(3) dreg23_re8(w17,w75,B5,RST,clk1);
mux #(19) mux_mu9(w26,w19,w76,addbsub);
mux #(19) mux_mu10(w25,w18,w77,addbsub);
not #(12) inv_mu11(w78,w17);
mux #(19) mux_mu12(w31,w16,w79,addbsub);
not #(12) inv_mu13(w80,w15);
not #(12) inv_mu14(w81,w14);
not #(12) inv_mu15(w82,w12);
not #(12) inv_mu16(w83,w13);
not #(12) inv_mu17(w76,w19);
not #(12) inv_mu18(w77,w18);
mux #(19) mux_mu19(w32,w17,w78,addbsub);
not #(12) inv_mu20(w79,w16);
mux #(19) mux_mu21(w27,w15,w80,addbsub);
mux #(19) mux_mu22(w28,w14,w81,addbsub);
mux #(19) mux_mu23(w29,w12,w82,addbsub);
mux #(19) mux_mu24(w30,w13,w83,addbsub);
dreg #(3) dreg16_re25(Q4,w84,w45,RST,clk1);
dreg #(3) dreg17_re26(Q3,w85,w41,RST,clk1);
dreg #(3) dreg18_re27(Q0,w86,w43,RST,clk1);
dreg #(3) dreg19_re28(Q1,w87,w44,RST,clk1);
dreg #(3) dreg20_re29(Q2,w88,w42,RST,clk1);
dreg #(3) dreg21_re30(Q6,w89,w47,RST,clk1);
dreg #(3) dreg22_re31(Q7,w90,w48,RST,clk1);
dreg #(3) dreg23_re32(Q5,w91,w46,RST,clk1);
or #(17) or2_fa1_pa33(w94,w92,w93);

xor #(17) xor2_fa2_pa34(w95,w30,w50);


and #(10) and2_fa3_pa35(w93,w30,w50);
and #(10) and2_fa4_pa36(w92,w95,w49);
xor #(10) xor2_fa5_pa37(w43,w95,w49);
or #(17) or2_fa6_pa38(w98,w96,w97);
xor #(17) xor2_fa7_pa39(w99,w29,w94);
and #(10) and2_fa8_pa40(w97,w29,w94);
and #(10) and2_fa9_pa41(w96,w99,w51);
xor #(10) xor2_fa10_pa42(w44,w99,w51);
or #(17) or2_fa11_pa43(w102,w100,w101);
xor #(17) xor2_fa12_pa44(w103,w28,w98);
and #(10) and2_fa13_pa45(w101,w28,w98);
and #(10) and2_fa14_pa46(w100,w103,w52);
xor #(10) xor2_fa15_pa47(w42,w103,w52);
or #(17) or2_fa16_pa48(w106,w104,w105);
xor #(17) xor2_fa17_pa49(w107,w27,w102);
and #(10) and2_fa18_pa50(w105,w27,w102);
and #(10) and2_fa19_pa51(w104,w107,w53);
xor #(10) xor2_fa20_pa52(w41,w107,w53);
or #(17) or2_fa21_pa53(w110,w108,w109);
xor #(17) xor2_fa22_pa54(w111,w31,w106);
and #(10) and2_fa23_pa55(w109,w31,w106);
and #(10) and2_fa24_pa56(w108,w111,w54);
xor #(10) xor2_fa25_pa57(w45,w111,w54);
or #(17) or2_fa26_pa58(w114,w112,w113);
xor #(17) xor2_fa27_pa59(w115,w32,w110);
and #(10) and2_fa28_pa60(w113,w32,w110);
and #(10) and2_fa29_pa61(w112,w115,w55);
xor #(10) xor2_fa30_pa62(w46,w115,w55);
or #(17) or2_fa31_pa63(w118,w116,w117);
xor #(17) xor2_fa32_pa64(w119,w25,w114);
and #(10) and2_fa33_pa65(w117,w25,w114);
and #(10) and2_fa34_pa66(w116,w119,w57);
xor #(10) xor2_fa35_pa67(w47,w119,w57);
or #(10) or2_fa36_pa68(w22,w120,w121);
xor #(17) xor2_fa37_pa69(w122,w26,w118);
and #(10) and2_fa38_pa70(w121,w26,w118);
and #(10) and2_fa39_pa71(w120,w122,w56);
xor #(10) xor2_fa40_pa72(w48,w122,w56);
dreg #(3) dreg16_re73(w54,w123,A4,RST,clk1);
dreg #(3) dreg17_re74(w53,w124,A3,RST,clk1);
dreg #(3) dreg18_re75(w49,w125,A0,RST,clk1);
dreg #(3) dreg19_re76(w51,w126,A1,RST,clk1);
dreg #(3) dreg20_re77(w52,w127,A2,RST,clk1);
dreg #(3) dreg21_re78(w57,w128,A6,RST,clk1);
dreg #(3) dreg22_re79(w56,w129,A7,RST,clk1);
dreg #(3) dreg23_re80(w55,w130,A5,RST,clk1);
endmodule
// Simulation parameters in Verilog Format
always

#1000 B5=~B5;
#2000 add/sub=~add/sub;
#500 clk1=~clk1;
#4000 RST=~RST;
#8000 A7=~A7;
#16000 A6=~A6;
#32000 A5=~A5;
#64000 A4=~A4;
#128000 A3=~A3;
#256000 A2=~A2;
#512000 A1=~A1;
#1024000 B7=~B7;
#2048000 B6=~B6;
#4096000 B4=~B4;
#8192000 B3=~B3;
#16384000 B2=~B2;
#32768000 B1=~B1;
#65536000 B0=~B0;
#131072000 A0=~A0;
// Simulation parameters
// B5 CLK 10 10
// add/sub CLK 20 20
// clk1 CLK 5.000 5.000
// RST CLK 40 40
// A7 CLK 80 80
// A6 CLK 160 160
// A5 CLK 320 320
// A4 CLK 640 640
// A3 CLK 1280 1280
// A2 CLK 2560 2560
// A1 CLK 5120 5120
// B7 CLK 10240 10240
// B6 CLK 20480 20480
// B4 CLK 40960 40960
// B3 CLK 81920 81920
// B2 CLK 163840 163840
Output:

// B1 CLK 327680 327680


// B0 CLK 655360 655360
// A0 CLK 1310720 1310720
RESULT:

Expt No:
Date :
AIM:

IMPLEMENTATION OF PARALLEL
PIPELINE ADDER

To implement Parallel Pipeline Adder using Verilog HDL


APPARATUS REQUIRED:

PC with Windows XP.


XILINX, Modelsim software.
FPGA kit.
RS 232 cable.

WORKING:
Step1: Circuit loads two 8-bit numbers from A, B inputs and stores these two
numbers in two 8-bit registers, also store carry input in one bit register.
Step2: Registered two 8-bit inputs and carry input are applied to the
parallel adder section in first clock cycle.
Step3: 8-bit sum and single bit carry out puts from the parallel adder are stored in
9-bit registers and the result appears on output LEDs in
the second clock cycle.

BLOCK DIAGRAM:

PROGRAM:
module Adder_Par_Top( Cin,RST,B7,clk1,A7,A6,A5,A4,
A3,A2,A1,A0,B6,B5,B4,B3,
B2,B1,B0,R0,R7,R6,R5,R4,
R3,R2,R1,Cout);
input Cin,RST,B7,clk1,A7,A6,A5,A4;
input A3,A2,A1,A0,B6,B5,B4,B3;
input B2,B1,B0;
output R0,R7,R6,R5,R4,R3,R2,R1;
output Cout;
wire w58,w59,w60,w61,w62,w63,w64,w65;
wire w66,w67,w68,w69,w70,w71,w72,w73;

wire w74,w75,w76,w77,w78,w79,w80,w81;
wire w82,w83,w84,w85,w86,w87,w88,w89;
wire w90,w91,w92,w93,w94,w95,w96,w97;
wire w98,w99,w100,w101,w102,w103,w104,w105;
wire w106,w107,w108,w109,w110,w111,w112;
dreg dreg1(w3,w47,Cin,RST,clk1);
dreg dreg2(Cout,w57,w18,w56,clk1);
or or2_fa1_pa1(w60,w58,w59);
xor xor2_fa2_pa2(w61,w1,w3);
and and2_fa3_pa3(w59,w1,w3);
and and2_fa4_pa4(w58,w61,w2);
xor xor2_fa5_pa5(w19,w61,w2);
or or2_fa6_pa6(w64,w62,w63);
xor xor2_fa7_pa7(w65,w4,w60);
and and2_fa8_pa8(w63,w4,w60);
and and2_fa9_pa9(w62,w65,w5);
xor xor2_fa10_pa10(w20,w65,w5);
or or2_fa11_pa11(w68,w66,w67);
xor xor2_fa12_pa12(w69,w6,w64);
and and2_fa13_pa13(w67,w6,w64);
and and2_fa14_pa14(w66,w69,w7);
xor xor2_fa15_pa15(w21,w69,w7);
or or2_fa16_pa16(w72,w70,w71);
xor xor2_fa17_pa17(w73,w8,w68);
and and2_fa18_pa18(w71,w8,w68);
and and2_fa19_pa19(w70,w73,w9);
xor xor2_fa20_pa20(w22,w73,w9);
or or2_fa21_pa21(w76,w74,w75);
xor xor2_fa22_pa22(w77,w10,w72);
and and2_fa23_pa23(w75,w10,w72);
and and2_fa24_pa24(w74,w77,w11);
xor xor2_fa25_pa25(w23,w77,w11);
or or2_fa26_pa26(w80,w78,w79);
xor xor2_fa27_pa27(w81,w12,w76);
and and2_fa28_pa28(w79,w12,w76);
and and2_fa29_pa29(w78,w81,w13);
Output:

xor xor2_fa30_pa30(w24,w81,w13);
or or2_fa31_pa31(w84,w82,w83);
xor xor2_fa32_pa32(w85,w14,w80);
and and2_fa33_pa33(w83,w14,w80);
and and2_fa34_pa34(w82,w85,w17);
xor xor2_fa35_pa35(w25,w85,w17);
or or2_fa36_pa36(w18,w86,w87);
xor xor2_fa37_pa37(w88,w16,w84);
and and2_fa38_pa38(w87,w16,w84);
and and2_fa39_pa39(w86,w88,w15);
xor xor2_fa40_pa40(w26,w88,w15);
dreg dreg16_re41(w11,w89,A4,RST,clk1);
dreg dreg17_re42(w9,w90,A3,RST,clk1);
dreg dreg18_re43(w2,w91,A0,RST,clk1);
dreg dreg19_re44(w5,w92,A1,RST,clk1);
dreg dreg20_re45(w7,w93,A2,RST,clk1);
dreg dreg21_re46(w17,w94,A6,RST,clk1);
dreg dreg22_re47(w15,w95,A7,RST,clk1);
dreg dreg23_re48(w13,w96,A5,RST,clk1);
dreg dreg16_re49(w10,w97,B4,RST,clk1);
dreg dreg17_re50(w8,w98,B3,RST,clk1);
dreg dreg18_re51(w1,w99,B0,RST,clk1);
dreg dreg19_re52(w4,w100,B1,RST,clk1);
dreg dreg20_re53(w6,w101,B2,RST,clk1);
dreg dreg21_re54(w14,w102,B6,RST,clk1);
dreg dreg22_re55(w16,w103,B7,RST,clk1);
dreg dreg23_re56(w12,w104,B5,RST,clk1);
dreg dreg16_re57(R4,w105,w23,RST,clk1);
dreg dreg17_re58(R3,w106,w22,RST,clk1);
dreg dreg18_re59(R0,w107,w19,RST,clk1);
dreg dreg19_re60(R1,w108,w20,RST,clk1);
dreg dreg20_re61(R2,w109,w21,RST,clk1);
dreg dreg21_re62(R6,w110,w25,RST,clk1);
dreg dreg22_re63(R7,w111,w26,RST,clk1);
dreg dreg23_re64(R5,w112,w24,RST,clk1);
endmodule

RESULT:

Expt. No:
Date:

IMPLEMENTATION OF REAL TIME CLOCK

AIM:
To implement Real Time Clock using Verilog HDL
APPARATUS REQUIRED:

PC with Windows XP
XILINX, Modelsim software.
FPGA kit
RS 232 cable.

WORKING:
Step1: By using the combination of the 10-bit and 6-bit counter we
construct 60-bit counter, this one is used for counting seconds.
Step2: Similar 60-bit counter is constructed for counting minutes, and is triggered
by the terminal count from seconds counter, after
completion of every
sixty seconds.
Step3: By using 10-bit counter and 2-bit counter 24-bit hours counter is
constructed and is triggered by the terminal count from the
minutes counter,
after completion of every sixty minutes.
Step4: All these BCD output signals (Hours, Minutes and Seconds) are
converted
into seven segments output by using BCD to seven
segment decoder.
Step5: All these selection lines are applied to the multiplexer section, and one of the
out put is selected at a time by using 3- selection lines
from the 3-stage counter
.Same selection lines are applied to the
3to 8 decoder section to generate enable
signals for multiplexed
mode seven segments in the FPGA kit.
Block Diagram:

PROGRAM:
Real Time Clock:
module RTC_FPGA_working_SEVEN(
clk1,RST,EN5,EN1,EN4,EN0,EN2,EN3, G,A,B,C,D,E,F);
input clk1,RST;
output EN5,EN1,EN4,EN0,EN2,EN3,G,A;
output B,C,D,E,F;
wire w84,w85,w86,w87,w88,w89,w90,w91;
wire w92,w93,w94,w95,w96,w97,w98,w99;
wire w100,w101,w102,w103,w104,w105,w106,w107;
wire w108,w109,w110,w111,w112,w113,w114,w115;
wire w116,w117,w118,w119,w120,w121,w122,w123;
wire w124,w125,w126,w127,w128,w129,w130,w131;
wire w132,w133,w134,w135,w136,w137,w138,w139;
wire w140,w141,w142,w143,w144,w145,w146,w147;
wire w148,w149,w150,w151,w152,w153,w154,w155;
wire w156,w157,w158,w159,w160,w161,w162,w163;
wire w164,w165,w166,w167,w168,w169,w170,w171;
wire w172,w173,w174,w175,w176,w177,w178,w179;
wire w180,w181,w182,w183,w184,w185,w186,w187;
wire w188,w189,w190,w191,w192,w193,w194,w195;
wire w196,w197,w198,w199,w200,w201,w202,w203;
wire w204,w205,w206,w207,w208,w209,w210,w211;
wire w212,w213,w214,w215,w216,w217,w218,w219;
wire w220,w221,w222,w223,w224,w225,w226,w227;
wire w228,w229,w230,w231,w232,w233,w234,w235;
wire w236,w237,w238,w239,w240,w241,w242,w243;
wire w244,w245,w246,w247,w248,w249,w250,w251;
wire w252,w253,w254,w255,w256,w257,w258,w259;
wire w260,w261,w262,w263,w264,w265,w266,w267;
wire w268,w269,w270,w271,w272,w273,w274,w275;
wire w276,w277,w278,w279,w280,w281,w282,w283;
wire w284,w285,w286,w287,w288,w289,w290,w291;
wire w292,w293,w294,w295,w296,w297,w298,w299;
wire w300,w301,w302,w303,w304,w305,w306,w307;
wire w308,w309,w310,w311,w312,w313,w314,w315;
wire w316,w317,w318,w319,w320,w321,w322,w323;
wire w324,w325,w326,w327,w328,w329,w330,w331;
wire w332,w333,w334,w335,w336,w337,w338,w339;
wire w340,w341,w342,w343,w344,w345,w346,w347;
wire w348,w349,w350,w351,w352,w353,w354,w355;
wire w356,w357,w358,w359,w360,w361,w362,w363;
wire w364,w365,w366,w367,w368,w369,w370,w371;
wire w372,w373,w374,w375,w376,w377,w378,w379;
wire w380,w381,w382,w383,w384,w385,w386,w387;
wire w388,w389,w390,w391,w392,w393,w394,w395;
wire w396,w397,w398,w399,w400,w401,w402,w403;
wire w404,w405,w406,w407,w408,w409,w410,w411;

wire w412,w413,w414,w415,w416,w417,w418,w419;
wire w420,w421,w422,w423,w424,w425,w426,w427;
wire w428,w429,w430,w431,w432,w433,w434,w435;
wire w436,w437,w438,w439,w440,w441,w442,w443;
wire w444,w445,w446,w447,w448,w449,w450,w451;
wire w452,w453,w454,w455,w456,w457,w458,w459;
wire w460,w461,w462,w463,w464,w465,w466,w467;
wire w468,w469,w470,w471,w472,w473,w474,w475;
wire w476,w477,w478,w479,w480,w481,w482,w483;
wire w484,w485,w486,w487,w488,w489,w490,w491;
wire w492,w493,w494,w495,w496,w497,w498,w499;
wire w500,w501,w502,w503,w504,w505,w506,w507;
wire w508,w509,w510,w511,w512,w513,w514,w515;
wire w516,w517,w518,w519,w520,w521,w522,w523;
wire w524,w525,w526,w527,w528,w529,w530,w531;
wire w532,w533,w534,w535,w536,w537,w538,w539;
wire w540,w541,w542,w543,w544,w545,w546,w547;
wire w548,w549,w550,w551,w552,w553,w554,w555;
wire w556,w557,w558,w559,w560,w561,w562,w563;
wire w564,w565,w566,w567,w568,w569,w570,w571;
wire w572,w573,w574,w575,w576,w577,w578,w579;
wire w580,w581,w582,w583,w584,w585,w586,w587;
wire w588,w589,w590,w591,w592,w593,w594,w595;
not inv(w34,RST);
not inv_DE1(w84,w2);
and and3_DE2(EN3,w2,w3,w85);
not inv_DE3(w85,w1);
not inv_DE4(w86,w3);
and and3_DE5(EN2,w84,w3,w85);
and and3_DE6(EN0,w84,w86,w85);
and and3_DE7(EN1,w2,w86,w85);
and and3_DE8(EN4,w84,w86,w1);
and and3_DE9(EN5,w2,w86,w1);
not inv_Di1_Di1_RT10(w87,RST);
xor xor2_Di2_Di2_RT11(w88,w21,w87);
xor xor2_Di3_Di3_RT12(w90,w20,w89);
dreg dreg70_Di4_Di4_RT13(w19,w93,w91,RST,w92);
and and3_Di5_Di5_RT14(w96,w19,w94,w95);
xor xor2_Di6_Di6_RT15(w98,w19,w97);
dreg dreg71_Di7_Di7_RT16(w21,w95,w99,RST,w92);
dreg dreg72_Di8_Di8_RT17(w20,w94,w100,RST,w92);
mux mux_Di9_Di9_RT18(w91,w98,RST,w101);
and and2_Di10_Di10_RT19(w89,w21,w87);
dreg dreg73_Di11_Di11_RT20(w101,w102,w96,RST,w92);
and and2_Di12_Di12_RT21(w97,w20,w89);
mux mux_Di13_Di13_RT22(w100,w90,RST,w101);
mux mux_Di14_Di14_RT23(w99,w88,RST,w101);
not inv_Di15_Di15_RT24(w103,RST);
xor xor2_Di16_Di16_RT25(w104,w25,w103);
xor xor2_Di17_Di17_RT26(w106,w24,w105);

dreg dreg65_Di18_Di18_RT27(w23,w109,w107,RST,w108);
xor xor2_Di19_Di19_RT28(w111,w22,w110);
and and2_Di20_Di20_RT29(w110,w23,w112);
dreg dreg66_Di21_Di21_RT30(w25,w114,w113,RST,w108);
dreg dreg67_Di22_Di22_RT31(w24,w116,w115,RST,w108);
mux mux_Di23_Di23_RT32(w117,w111,RST,w92);
and and2_Di24_Di24_RT33(w105,w25,w103);
dreg dreg68_Di25_Di25_RT34(w92,w119,w118,RST,w108);
and and2_Di26_Di26_RT35(w112,w24,w105);
mux mux_Di27_Di27_RT36(w115,w106,RST,w92);
mux mux_Di28_Di28_RT37(w113,w104,RST,w92);
dreg dreg69_Di29_Di29_RT38(w22,w120,w117,RST,w108);
xor xor2_Di30_Di30_RT39(w121,w23,w112);
mux mux_Di31_Di31_RT40(w107,w121,RST,w92);
and and3_Di32_Di32_RT41(w122,w114,w116,w109);
and and2_Di33_Di33_RT42(w118,w22,w122);
not inv_Di1_Di34_RT43(w123,RST);
xor xor2_Di2_Di35_RT44(w124,w28,w123);
xor xor2_Di3_Di36_RT45(w126,w27,w125);
dreg dreg70_Di4_Di37_RT46(w26,w129,w127,RST,w128);
and and3_Di5_Di38_RT47(w132,w26,w130,w131);
xor xor2_Di6_Di39_RT48(w134,w26,w133);
dreg dreg71_Di7_Di40_RT49(w28,w131,w135,RST,w128);
dreg dreg72_Di8_Di41_RT50(w27,w130,w136,RST,w128);
mux mux_Di9_Di42_RT51(w127,w134,RST,w108);
and and2_Di10_Di43_RT52(w125,w28,w123);
dreg dreg73_Di11_Di44_RT53(w108,w137,w132,RST,w128);
and and2_Di12_Di45_RT54(w133,w27,w125);
mux mux_Di13_Di46_RT55(w136,w126,RST,w108);
mux mux_Di14_Di47_RT56(w135,w124,RST,w108);
not inv_Di15_Di48_RT57(w138,RST);
xor xor2_Di16_Di49_RT58(w139,w12,w138);
xor xor2_Di17_Di50_RT59(w141,w31,w140);
dreg dreg65_Di18_Di51_RT60(w30,w143,w142,RST,w11);
xor xor2_Di19_Di52_RT61(w145,w29,w144);
and and2_Di20_Di53_RT62(w144,w30,w146);
dreg dreg66_Di21_Di54_RT63(w12,w148,w147,RST,w11);
dreg dreg67_Di22_Di55_RT64(w31,w150,w149,RST,w11);
mux mux_Di23_Di56_RT65(w151,w145,RST,w128);
and and2_Di24_Di57_RT66(w140,w12,w138);
dreg dreg68_Di25_Di58_RT67(w128,w153,w152,RST,w11);
and and2_Di26_Di59_RT68(w146,w31,w140);
mux mux_Di27_Di60_RT69(w149,w141,RST,w128);
mux mux_Di28_Di61_RT70(w147,w139,RST,w128);
dreg dreg69_Di29_Di62_RT71(w29,w154,w151,RST,w11);
xor xor2_Di30_Di63_RT72(w155,w30,w146);
mux mux_Di31_Di64_RT73(w142,w155,RST,w128);
and and3_Di32_Di65_RT74(w156,w148,w150,w143);
and and2_Di33_Di66_RT75(w152,w29,w156);
and and2_Di67_RT76(w159,w157,w158);

not inv_Di68_RT77(w160,w17);
and and3_Di69_RT78(w157,w16,w160,w161);
not inv_Di70_RT79(w161,w18);
or or2_Di71_RT80(w162,w159,RST);
not inv_Di1_Di72_RT81(w163,w162);
xor xor2_Di2_Di73_RT82(w164,w14,w163);
xor xor2_Di3_Di74_RT83(w166,w13,w165);
mux mux_Di4_Di75_RT84(w167,w164,w162,w158);
mux mux_Di5_Di76_RT85(w168,w166,w162,w158);
dreg dreg38_Di6_Di77_RT86(w158,w171,w169,w162,w170);
dreg dreg39_Di7_Di78_RT87(w14,w172,w167,w162,w170);
dreg dreg40_Di8_Di79_RT88(w13,w173,w168,w162,w170);
and and2_Di9_Di80_RT89(w169,w14,w173);
and and2_Di10_Di81_RT90(w165,w14,w163);
not inv_Di11_Di82_RT91(w174,w162);
xor xor2_Di12_Di83_RT92(w175,w18,w174);
xor xor2_Di13_Di84_RT93(w177,w17,w176);
dreg dreg65_Di14_Di85_RT94(w16,w179,w178,w162,w101);
xor xor2_Di15_Di86_RT95(w181,w15,w180);
and and2_Di16_Di87_RT96(w180,w16,w182);
dreg dreg66_Di17_Di88_RT97(w18,w184,w183,w162,w101);
dreg dreg67_Di18_Di89_RT98(w17,w186,w185,w162,w101);
mux mux_Di19_Di90_RT99(w187,w181,w162,w170);
and and2_Di20_Di91_RT100(w176,w18,w174);
dreg dreg68_Di21_Di92_RT101(w170,w189,w188,w162,w101);
and and2_Di22_Di93_RT102(w182,w17,w176);
mux mux_Di23_Di94_RT103(w185,w177,w162,w170);
mux mux_Di24_Di95_RT104(w183,w175,w162,w170);
dreg dreg69_Di25_Di96_RT105(w15,w190,w187,w162,w101);
xor xor2_Di26_Di97_RT106(w191,w16,w182);
mux mux_Di27_Di98_RT107(w178,w191,w162,w170);
and and3_Di28_Di99_RT108(w192,w184,w186,w179);
and and2_Di29_Di100_RT109(w188,w15,w192);
not inv_Di1_DI110(w193,RST);
xor xor2_Di2_DI111(w195,w194,w193);
xor xor2_Di3_DI112(w198,w196,w197);
dreg dreg39_Di4_DI113(w200,w201,w199,RST,clk1);
xor xor2_Di5_DI114(w204,w202,w203);
and and2_Di6_DI115(w203,w200,w205);
dreg dreg40_Di7_DI116(w194,w207,w206,RST,clk1);
dreg dreg41_Di8_DI117(w196,w209,w208,RST,clk1);
mux mux_Di9_DI118(w211,w204,RST,w210);
and and2_Di10_DI119(w197,w194,w193);
dreg dreg42_Di11_DI120(w210,w213,w212,RST,clk1);
and and2_Di12_DI121(w205,w196,w197);
mux mux_Di13_DI122(w208,w198,RST,w210);
mux mux_Di14_DI123(w206,w195,RST,w210);
dreg dreg43_Di15_DI124(w202,w214,w211,RST,clk1);
xor xor2_Di16_DI125(w215,w200,w205);
mux mux_Di17_DI126(w199,w215,RST,w210);

and and3_Di18_DI127(w216,w207,w209,w201);
and and2_Di19_DI128(w212,w202,w216);
not inv_Di20_DI129(w217,RST);
xor xor2_Di21_DI130(w219,w218,w217);
xor xor2_Di22_DI131(w222,w220,w221);
dreg dreg6_Di23_DI132(w224,w225,w223,RST,w210);
and and3_Di24_DI133(w228,w224,w226,w227);
xor xor2_Di25_DI134(w230,w224,w229);
dreg dreg7_Di26_DI135(w218,w227,w231,RST,w210);
dreg dreg8_Di27_DI136(w220,w226,w232,RST,w210);
mux mux_Di28_DI137(w223,w230,RST,w33);
and and2_Di29_DI138(w221,w218,w217);
dreg dreg9_Di30_DI139(w33,w233,w228,RST,w210);
and and2_Di31_DI140(w229,w220,w221);
mux mux_Di32_DI141(w232,w222,RST,w33);
mux mux_Di33_DI142(w231,w219,RST,w33);
and and2_BC143(w41,w34,w234);
not inv_BC144(w235,w15);
not inv_BC145(w236,w16);
not inv_BC146(w237,w18);
not inv_BC147(w238,w17);
and and3_BC148(w239,w15,w236,w238);
and and3_BC149(w240,w235,w16,w18);
or or2_BC150(w243,w241,w242);
and and2_BC151(w244,w17,w235);
or or2_BC152(w245,w239,w240);
or or2_BC153(w247,w246,w244);
or or2_BC154(w248,w245,w247);
and and3_BC155(w249,w18,w17,w235);
and and2_BC156(w250,w235,w236);
and and3_BC157(w251,w235,w238,w237);
or or2_BC158(w234,w252,w253);
and and2_BC159(w254,w238,w235);
and and2_BC160(w255,w18,w235);
and and2_BC161(w256,w16,w235);
and and2_BC162(w257,w238,w236);
or or2_BC163(w258,w254,w255);
or or2_BC164(w259,w256,w257);
or or2_BC165(w260,w258,w259);
and and3_BC166(w261,w236,w238,w237);
and and3_BC167(w262,w235,w236,w17);
and and3_BC168(w263,w235,w17,w237);
and and2_BC169(w264,w16,w235);
and and2_BC170(w265,w18,w238);
and and2_BC171(w266,w265,w264);
or or2_BC172(w267,w261,w262);
or or2_BC173(w268,w263,w266);
or or2_BC174(w269,w267,w268);
and and3_BC175(w270,w236,w238,w237);
and and3_BC176(w271,w235,w17,w237);

and and3_BC177(w272,w236,w238,w237);
or or2_BC178(w273,w271,w272);
and and3_BC179(w274,w235,w16,w238);
and and3_BC180(w275,w15,w236,w238);
and and3_BC181(w276,w235,w16,w237);
or or2_BC182(w277,w274,w275);
or or2_BC183(w278,w276,w270);
or or2_BC184(w279,w277,w278);
and and3_BC185(w280,w15,w236,w238);
and and3_BC186(w281,w235,w16,w238);
and and3_BC187(w282,w235,w16,w237);
and and3_BC188(w283,w235,w236,w17);
or or2_BC189(w252,w280,w281);
or or2_BC190(w253,w282,w283);
and and2_BC191(w284,w236,w238);
or or2_BC192(w241,w249,w284);
or or2_BC193(w242,w250,w251);
and and3_BC194(w246,w236,w238,w237);
and and2_BC195(w40,w34,w248);
and and2_BC196(w39,w34,w243);
and and2_BC197(w38,w34,w260);
and and2_BC198(w37,w34,w269);
and and2_BC199(w36,w34,w273);
and and2_BC200(w35,w34,w279);
and and2_BC201(w48,w34,w285);
not inv_BC202(w286,RST);
not inv_BC203(w287,RST);
not inv_BC204(w288,w14);
not inv_BC205(w289,w13);
and and3_BC206(w290,RST,w287,w289);
and and3_BC207(w291,w286,RST,w14);
or or2_BC208(w294,w292,w293);
and and2_BC209(w295,w13,w286);
or or2_BC210(w296,w290,w291);
or or2_BC211(w298,w297,w295);
or or2_BC212(w299,w296,w298);
and and3_BC213(w300,w14,w13,w286);
and and2_BC214(w301,w286,w287);
and and3_BC215(w302,w286,w289,w288);
or or2_BC216(w285,w303,w304);
and and2_BC217(w305,w289,w286);
and and2_BC218(w306,w14,w286);
and and2_BC219(w307,RST,w286);
and and2_BC220(w308,w289,w287);
or or2_BC221(w309,w305,w306);
or or2_BC222(w310,w307,w308);
or or2_BC223(w311,w309,w310);
and and3_BC224(w312,w287,w289,w288);
and and3_BC225(w313,w286,w287,w13);
and and3_BC226(w314,w286,w13,w288);

and and2_BC227(w315,RST,w286);
and and2_BC228(w316,w14,w289);
and and2_BC229(w317,w316,w315);
or or2_BC230(w318,w312,w313);
or or2_BC231(w319,w314,w317);
or or2_BC232(w320,w318,w319);
and and3_BC233(w321,w287,w289,w288);
and and3_BC234(w322,w286,w13,w288);
and and3_BC235(w323,w287,w289,w288);
or or2_BC236(w324,w322,w323);
and and3_BC237(w325,w286,RST,w289);
and and3_BC238(w326,RST,w287,w289);
and and3_BC239(w327,w286,RST,w288);
or or2_BC240(w328,w325,w326);
or or2_BC241(w329,w327,w321);
or or2_BC242(w330,w328,w329);
and and3_BC243(w331,RST,w287,w289);
and and3_BC244(w332,w286,RST,w289);
and and3_BC245(w333,w286,RST,w288);
and and3_BC246(w334,w286,w287,w13);
or or2_BC247(w303,w331,w332);
or or2_BC248(w304,w333,w334);
and and2_BC249(w335,w287,w289);
or or2_BC250(w292,w300,w335);
or or2_BC251(w293,w301,w302);
and and3_BC252(w297,w287,w289,w288);
and and2_BC253(w47,w34,w299);
and and2_BC254(w46,w34,w294);
and and2_BC255(w45,w34,w311);
and and2_BC256(w44,w34,w320);
and and2_BC257(w43,w34,w324);
and and2_BC258(w42,w34,w330);
and and2_BC259(w55,w34,w336);
not inv_BC260(w337,RST);
not inv_BC261(w338,w19);
not inv_BC262(w339,w21);
not inv_BC263(w340,w20);
and and3_BC264(w341,RST,w338,w340);
and and3_BC265(w342,w337,w19,w21);
or or2_BC266(w345,w343,w344);
and and2_BC267(w346,w20,w337);
or or2_BC268(w347,w341,w342);
or or2_BC269(w349,w348,w346);
or or2_BC270(w350,w347,w349);
and and3_BC271(w351,w21,w20,w337);
and and2_BC272(w352,w337,w338);
and and3_BC273(w353,w337,w340,w339);
or or2_BC274(w336,w354,w355);
and and2_BC275(w356,w340,w337);
and and2_BC276(w357,w21,w337);

and and2_BC277(w358,w19,w337);
and and2_BC278(w359,w340,w338);
or or2_BC279(w360,w356,w357);
or or2_BC280(w361,w358,w359);
or or2_BC281(w362,w360,w361);
and and3_BC282(w363,w338,w340,w339);
and and3_BC283(w364,w337,w338,w20);
and and3_BC284(w365,w337,w20,w339);
and and2_BC285(w366,w19,w337);
and and2_BC286(w367,w21,w340);
and and2_BC287(w368,w367,w366);
or or2_BC288(w369,w363,w364);
or or2_BC289(w370,w365,w368);
or or2_BC290(w371,w369,w370);
and and3_BC291(w372,w338,w340,w339);
and and3_BC292(w373,w337,w20,w339);
and and3_BC293(w374,w338,w340,w339);
or or2_BC294(w375,w373,w374);
and and3_BC295(w376,w337,w19,w340);
and and3_BC296(w377,RST,w338,w340);
and and3_BC297(w378,w337,w19,w339);
or or2_BC298(w379,w376,w377);
or or2_BC299(w380,w378,w372);
or or2_BC300(w381,w379,w380);
and and3_BC301(w382,RST,w338,w340);
and and3_BC302(w383,w337,w19,w340);
and and3_BC303(w384,w337,w19,w339);
and and3_BC304(w385,w337,w338,w20);
or or2_BC305(w354,w382,w383);
or or2_BC306(w355,w384,w385);
and and2_BC307(w386,w338,w340);
or or2_BC308(w343,w351,w386);
or or2_BC309(w344,w352,w353);
and and3_BC310(w348,w338,w340,w339);
and and2_BC311(w54,w34,w350);
and and2_BC312(w53,w34,w345);
and and2_BC313(w52,w34,w362);
and and2_BC314(w51,w34,w371);
and and2_BC315(w50,w34,w375);
and and2_BC316(w49,w34,w381);
and and2_BC317(w62,w34,w387);
not inv_BC318(w388,w29);
not inv_BC319(w389,w30);
not inv_BC320(w390,w12);
not inv_BC321(w391,w31);
and and3_BC322(w392,w29,w389,w391);
and and3_BC323(w393,w388,w30,w12);
or or2_BC324(w396,w394,w395);
and and2_BC325(w397,w31,w388);
or or2_BC326(w398,w392,w393);

or or2_BC327(w400,w399,w397);
or or2_BC328(w401,w398,w400);
and and3_BC329(w402,w12,w31,w388);
and and2_BC330(w403,w388,w389);
and and3_BC331(w404,w388,w391,w390);
or or2_BC332(w387,w405,w406);
and and2_BC333(w407,w391,w388);
and and2_BC334(w408,w12,w388);
and and2_BC335(w409,w30,w388);
and and2_BC336(w410,w391,w389);
or or2_BC337(w411,w407,w408);
or or2_BC338(w412,w409,w410);
or or2_BC339(w413,w411,w412);
and and3_BC340(w414,w389,w391,w390);
and and3_BC341(w415,w388,w389,w31);
and and3_BC342(w416,w388,w31,w390);
and and2_BC343(w417,w30,w388);
and and2_BC344(w418,w12,w391);
and and2_BC345(w419,w418,w417);
or or2_BC346(w420,w414,w415);
or or2_BC347(w421,w416,w419);
or or2_BC348(w422,w420,w421);
and and3_BC349(w423,w389,w391,w390);
and and3_BC350(w424,w388,w31,w390);
and and3_BC351(w425,w389,w391,w390);
or or2_BC352(w426,w424,w425);
and and3_BC353(w427,w388,w30,w391);
and and3_BC354(w428,w29,w389,w391);
and and3_BC355(w429,w388,w30,w390);
or or2_BC356(w430,w427,w428);
or or2_BC357(w431,w429,w423);
or or2_BC358(w432,w430,w431);
and and3_BC359(w433,w29,w389,w391);
and and3_BC360(w434,w388,w30,w391);
and and3_BC361(w435,w388,w30,w390);
and and3_BC362(w436,w388,w389,w31);
or or2_BC363(w405,w433,w434);
or or2_BC364(w406,w435,w436);
and and2_BC365(w437,w389,w391);
or or2_BC366(w394,w402,w437);
or or2_BC367(w395,w403,w404);
and and3_BC368(w399,w389,w391,w390);
and and2_BC369(w61,w34,w401);
and and2_BC370(w60,w34,w396);
and and2_BC371(w59,w34,w413);
and and2_BC372(w58,w34,w422);
and and2_BC373(w57,w34,w426);
and and2_BC374(w56,w34,w432);
mux mux_Mu1_Mu375(A,w438,w439,w1);
mux mux_Mu2_Mu376(w440,w61,w80,w2);

mux mux_Mu3_Mu377(w441,w83,w54,w2);
mux mux_Mu4_Mu378(w439,w442,w443,w3);
mux mux_Mu5_Mu379(w438,w440,w441,w3);
mux mux_Mu6_Mu380(w442,w40,w47,w2);
mux mux_Mu7_Mu381(B,w444,w445,w1);
mux mux_Mu8_Mu382(w446,w60,w81,w2);
mux mux_Mu9_Mu383(w447,w82,w53,w2);
mux mux_Mu10_Mu384(w445,w448,w449,w3);
mux mux_Mu11_Mu385(w444,w446,w447,w3);
mux mux_Mu12_Mu386(w448,w39,w46,w2);
mux mux_Mu13_Mu387(F,w450,w451,w1);
mux mux_Mu14_Mu388(w452,w56,w75,w2);
mux mux_Mu15_Mu389(w453,w74,w49,w2);
mux mux_Mu16_Mu390(w451,w454,w455,w3);
mux mux_Mu17_Mu391(w450,w452,w453,w3);
mux mux_Mu18_Mu392(w454,w35,w42,w2);
mux mux_Mu19_Mu393(C,w456,w457,w1);
mux mux_Mu20_Mu394(w458,w59,w78,w2);
mux mux_Mu21_Mu395(w459,w79,w52,w2);
mux mux_Mu22_Mu396(w457,w460,w461,w3);
mux mux_Mu23_Mu397(w456,w458,w459,w3);
mux mux_Mu24_Mu398(w460,w38,w45,w2);
mux mux_Mu25_Mu399(E,w462,w463,w1);
mux mux_Mu26_Mu400(w464,w57,w72,w2);
mux mux_Mu27_Mu401(w465,w73,w50,w2);
mux mux_Mu28_Mu402(w463,w466,w467,w3);
mux mux_Mu29_Mu403(w462,w464,w465,w3);
mux mux_Mu30_Mu404(w466,w36,w43,w2);
mux mux_Mu31_Mu405(D,w468,w469,w1);
mux mux_Mu32_Mu406(w470,w58,w77,w2);
mux mux_Mu33_Mu407(w471,w76,w51,w2);
mux mux_Mu34_Mu408(w469,w472,w473,w3);
mux mux_Mu35_Mu409(w468,w470,w471,w3);
mux mux_Mu36_Mu410(w472,w37,w44,w2);
mux mux_Mu37_Mu411(G,w474,w475,w1);
mux mux_Mu38_Mu412(w476,w62,w70,w2);
mux mux_Mu39_Mu413(w477,w71,w55,w2);
mux mux_Mu40_Mu414(w475,w478,w479,w3);
mux mux_Mu41_Mu415(w474,w476,w477,w3);
mux mux_Mu42_Mu416(w478,w41,w48,w2);
and and2_cn417(w481,w3,w480);
xor xor2_cn418(w482,w1,w481);
dreg dreg18_cn419(w1,w483,w482,RST,w33);
dreg dreg19_cn420(w2,w485,w484,RST,w33);
dreg dreg20_cn421(w3,w487,w486,RST,w33);
xor xor2_cn422(w486,w3,w480);
not inv_cn423(w488,RST);
xor xor2_cn424(w484,w2,w488);
and and2_cn425(w480,w2,w488);
and and2_BC426(w71,w34,w489);

not inv_BC427(w490,w22);
not inv_BC428(w491,w23);
not inv_BC429(w492,w25);
not inv_BC430(w493,w24);
and and3_BC431(w494,w22,w491,w493);
and and3_BC432(w495,w490,w23,w25);
or or2_BC433(w498,w496,w497);
and and2_BC434(w499,w24,w490);
or or2_BC435(w500,w494,w495);
or or2_BC436(w502,w501,w499);
or or2_BC437(w503,w500,w502);
and and3_BC438(w504,w25,w24,w490);
and and2_BC439(w505,w490,w491);
and and3_BC440(w506,w490,w493,w492);
or or2_BC441(w489,w507,w508);
and and2_BC442(w509,w493,w490);
and and2_BC443(w510,w25,w490);
and and2_BC444(w511,w23,w490);
and and2_BC445(w512,w493,w491);
or or2_BC446(w513,w509,w510);
or or2_BC447(w514,w511,w512);
or or2_BC448(w515,w513,w514);
and and3_BC449(w516,w491,w493,w492);
and and3_BC450(w517,w490,w491,w24);
and and3_BC451(w518,w490,w24,w492);
and and2_BC452(w519,w23,w490);
and and2_BC453(w520,w25,w493);
and and2_BC454(w521,w520,w519);
or or2_BC455(w522,w516,w517);
or or2_BC456(w523,w518,w521);
or or2_BC457(w524,w522,w523);
and and3_BC458(w525,w491,w493,w492);
and and3_BC459(w526,w490,w24,w492);
and and3_BC460(w527,w491,w493,w492);
or or2_BC461(w528,w526,w527);
and and3_BC462(w529,w490,w23,w493);
and and3_BC463(w530,w22,w491,w493);
and and3_BC464(w531,w490,w23,w492);
or or2_BC465(w532,w529,w530);
or or2_BC466(w533,w531,w525);
or or2_BC467(w534,w532,w533);
and and3_BC468(w535,w22,w491,w493);
and and3_BC469(w536,w490,w23,w493);
and and3_BC470(w537,w490,w23,w492);
and and3_BC471(w538,w490,w491,w24);
or or2_BC472(w507,w535,w536);
or or2_BC473(w508,w537,w538);
and and2_BC474(w539,w491,w493);
or or2_BC475(w496,w504,w539);
or or2_BC476(w497,w505,w506);

and and3_BC477(w501,w491,w493,w492);
and and2_BC478(w83,w34,w503);
and and2_BC479(w82,w34,w498);
and and2_BC480(w79,w34,w515);
and and2_BC481(w76,w34,w524);
and and2_BC482(w73,w34,w528);
and and2_BC483(w74,w34,w534);
and and2_BC484(w70,w34,w540);
not inv_BC485(w541,RST);
not inv_BC486(w542,w26);
not inv_BC487(w543,w28);
not inv_BC488(w544,w27);
and and3_BC489(w545,RST,w542,w544);
and and3_BC490(w546,w541,w26,w28);
or or2_BC491(w549,w547,w548);
and and2_BC492(w550,w27,w541);
or or2_BC493(w551,w545,w546);
or or2_BC494(w553,w552,w550);
or or2_BC495(w554,w551,w553);
and and3_BC496(w555,w28,w27,w541);
and and2_BC497(w556,w541,w542);
and and3_BC498(w557,w541,w544,w543);
or or2_BC499(w540,w558,w559);
and and2_BC500(w560,w544,w541);
and and2_BC501(w561,w28,w541);
and and2_BC502(w562,w26,w541);
and and2_BC503(w563,w544,w542);
or or2_BC504(w564,w560,w561);
or or2_BC505(w565,w562,w563);
or or2_BC506(w566,w564,w565);
and and3_BC507(w567,w542,w544,w543);
and and3_BC508(w568,w541,w542,w27);
and and3_BC509(w569,w541,w27,w543);
and and2_BC510(w570,w26,w541);
and and2_BC511(w571,w28,w544);
and and2_BC512(w572,w571,w570);
or or2_BC513(w573,w567,w568);
or or2_BC514(w574,w569,w572);
or or2_BC515(w575,w573,w574);
and and3_BC516(w576,w542,w544,w543);
and and3_BC517(w577,w541,w27,w543);
and and3_BC518(w578,w542,w544,w543);
or or2_BC519(w579,w577,w578);
and and3_BC520(w580,w541,w26,w544);
and and3_BC521(w581,RST,w542,w544);
and and3_BC522(w582,w541,w26,w543);
or or2_BC523(w583,w580,w581);
or or2_BC524(w584,w582,w576);
or or2_BC525(w585,w583,w584);
and and3_BC526(w586,RST,w542,w544);

and and3_BC527(w587,w541,w26,w544);
and and3_BC528(w588,w541,w26,w543);
and and3_BC529(w589,w541,w542,w27);
or or2_BC530(w558,w586,w587);
or or2_BC531(w559,w588,w589);
and and2_BC532(w590,w542,w544);
or or2_BC533(w547,w555,w590);
or or2_BC534(w548,w556,w557);
and and3_BC535(w552,w542,w544,w543);
and and2_BC536(w80,w34,w554);
and and2_BC537(w81,w34,w549);
and and2_BC538(w78,w34,w566);
and and2_BC539(w77,w34,w575);
and and2_BC540(w72,w34,w579);
and and2_BC541(w75,w34,w585);
not inv_co542(w591,RST);
xor xor2_co543(w593,w592,w591);
xor xor2_co544(w596,w594,w595);
xor xor2_co545(w599,w597,w598);
dreg dreg1_co546(w601,w602,w600,RST,clk1);
xor xor2_co547(w600,w601,w603);
and and2_co548(w603,w597,w598);
dreg dreg2_co549(w592,w604,w593,RST,clk1);
dreg dreg3_co550(w597,w605,w599,RST,clk1);
and and2_co551(w606,w594,w595);
and and2_co552(w598,w592,w591);
dreg dreg4_co553(w594,w607,w596,RST,clk1);
dreg dreg5_co554(w609,w610,w608,RST,clk1);
xor xor2_co555(w608,w609,w611);
xor xor2_co556(w614,w612,w613);
dreg dreg6_co557(w612,w615,w614,RST,clk1);
xor xor2_co558(w618,w616,w617);
dreg dreg7_co559(w616,w619,w618,RST,clk1);
dreg dreg8_co560(w621,w622,w620,RST,clk1);
xor xor2_co561(w620,w621,w623);
and and2_co562(w611,w601,w603);
and and2_co563(w613,w609,w611);
and and2_co564(w617,w612,w613);
Output:

and and2_co565(w623,w616,w617);
and and2_co566(w626,w624,w625);
and and2_co567(w625,w627,w628);
xor xor2_co568(w631,w629,w630);
dreg dreg9_co569(w629,w632,w631,RST,clk1);
dreg dreg10_co570(w634,w635,w633,RST,clk1);
xor xor2_co571(w633,w634,w636);
dreg dreg11_co572(w638,w639,w637,RST,clk1);
xor xor2_co573(w637,w638,w626);
xor xor2_co574(w640,w624,w625);
dreg dreg12_co575(w624,w641,w640,RST,clk1);
dreg dreg13_co576(w643,w644,w642,RST,clk1);
and and2_co577(w646,w645,w606);
and and2_co578(w648,w643,w647);
dreg dreg14_co579(w650,w651,w649,RST,clk1);
dreg dreg15_co580(w645,w653,w652,RST,clk1);
and and2_co581(w628,w650,w646);
xor xor2_co582(w654,w627,w628);
and and2_co583(w630,w634,w636);
dreg dreg16_co584(w627,w655,w654,RST,clk1);
and and2_co585(w636,w638,w626);
xor xor2_co586(w649,w650,w646);
xor xor2_co587(w642,w643,w647);
xor xor2_co588(w652,w645,w606);
and and2_co589(w595,w621,w623);
dreg dreg17_co590(w657,w658,w656,RST,clk1);
dreg dreg18_co591(w660,w661,w659,RST,clk1);
and and2_co592(w663,w657,w662);
dreg dreg19_co593(w11,w665,w664,RST,clk1);
and and2_co594(w662,w660,w648);
xor xor2_co595(w664,w11,w666);
xor xor2_co596(w656,w657,w662);
and and2_co597(w666,w667,w668);
xor xor2_co598(w659,w660,w648);
dreg dreg20_co599(w667,w670,w669,RST,clk1);
and and2_co600(w647,w629,w630);
xor xor2_co601(w669,w667,w668);
xor xor2_co602(w672,w671,w663);
dreg dreg21_co603(w671,w673,w672,RST,clk1);
and and2_co604(w668,w671,w663);
dreg dreg22_co605(w675,w676,w674,RST,clk1);
xor xor2_co606(w674,w675,w668);
dreg dreg23_co607(w678,w679,w677,RST,clk1);
xor xor2_co608(w677,w678,w666);
endmodule

RESULT: