MICROPROCESSOR & INTERFACING

Q.1) a). Explain (1) ALU : Definition: Abbreviation of arithmetic logic unit, the part of a computer that performs all arithmetic computations, such as addition and multiplication, and all comparison operations. The ALU is one component of the CPU (central processing unit). OR
In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs.

Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science, falling under Arithmetic and logic structures in the ACM Computing Classification System Numerical systems An ALU must process numbers using the same format as the rest of the digital circuit. The format of modern processors is almost always the two's complement binary number representation. Early computers used a wide variety of number systems, including ones' complement, two's complement sign-magnitude format, and even true decimal systems, with various[NB 2] representation of the digits. ALUs for each one of these that makes it easier for the ALUs to calculate additions and subtractions. The ones' complement and two's complement number systems allow for subtraction to be accomplished by adding the negative of a number in a very simple way which negates the need for specialized circuits to do subtraction; however, calculating the negative in two's complement requires adding a one to the low order bit and propagating the carry. An alternative way to do two's complement subtraction of AB is to present a one to the carry input of the adder and use B rather than B as the second input. Practical overview Most of a processor's operations are performed by one or more ALUs. An ALU loads data from input registers, an external Control Unit then tells the ALU what operation to perform on that data, and then the ALU stores its result into an output register. The Control Unit is responsible for moving the processed data between these registers, ALU and memory. Simple operations A simple example arithmetic logic unit (2-bit ALU) that does AND, OR, XOR, and addition Most ALUs can perform the following operations: Bitwise logic operations (AND, NOT, OR, XOR) Integer arithmetic operations (addition, subtraction, and sometimes multiplication and division, though this is more expensive) Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or right, with or without sign extension). Shifts can be seen as multiplications and divisions by a power of two.

A simple example arithmetic logic unit (2-bit ALU) that does AND, OR, XOR, and addition

Complex operations Engineers can design an Arithmetic Logic Unit to calculate any operation. The more complex the operation, the more expensive the ALU is, the more space it uses in the processor, and the more power it dissipates. Therefore, engineers compromise. They make the ALU powerful enough to make the processor fast, yet not so complex as to become prohibitive. For example, computing the square root of a number might use: 1. Calculation in a single clock Design an extraordinarily complex ALU that calculates the square root of any number in a single step. 2. Calculation pipeline Design a very complex ALU that calculates the square root of any number in several steps. The intermediate results go through a series of circuits arranged like a factory production line. The ALU can accept new numbers to calculate even before having finished the previous ones. The ALU can now produce numbers as fast as a single-clock ALU, although the results start to flow out of the ALU only after an initial delay. 3. Iterative calculation Design a complex ALU that calculates the square root through several steps. This usually relies on control from a complex control unit with built-in microcode. 4. Co-processor Design a simple ALU in the processor, and sell a separate specialized and costly processor that the customer can install just beside this one, and implements one of the options above.

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5. Software libraries Tell the programmers that there is no co-processor and there is no emulation, so they will have to write their own algorithms to calculate square roots by software. 6. Software emulation Emulate the existence of the co-processor, that is, whenever a program attempts to perform the square root calculation, make the processor check if there is a coprocessor present and use it if there is one; if there isn't one, interrupt the processing of the program and invoke the operating system to perform the square root calculation through some software algorithm. The options above go from the fastest and most expensive one to the slowest and least expensive one. Therefore, while even the simplest computer can calculate the most complicated formula, the simplest computers will usually take a long time doing that because of the several steps for calculating the formula. Powerful processors like the Intel Core and AMD64 implement option #1 for several simple operations, #2 for the most common complex operations and #3 for the extremely complex operations. Inputs and outputs The inputs to the ALU are the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. Its output is the result of the computation. In many designs the ALU also takes or generates as inputs or outputs a set of condition codes from or to a status register. These codes are used to indicate cases such as carry-in or carry-out, overflow, divide-byzero, etc. A floating-point unit also performs arithmetic operations between two values, but they do so for numbers in floating-point representation, which is much more complicated than the two's complement representation used in a typical ALU. In order to do these calculations, a FPU has several complex circuits built-in, including some internal ALUs. In modern practice, engineers typically refer to the ALU as the circuit that performs integer arithmetic operations (like two's complement and BCD). Circuits that calculate more complex formats like floating point, complex numbers, etc. usually receive a more specific name such as FPU.

(2) PROGRAM COUNTER: DEFINITION : HARDWARE: (PC) A register in the central processing unit that contains the addresss of the next instruction to be executed. After each instruction is fetched, the PC is automatically incremented to point to the following instruction. It is not normally manipulated like an ordinary register but instead, special instructions are provided to alter the flow of control by writing a new value to the PC, e.g. JUMP, CALL, RTS. The program counter (PC), commonly called the instruction pointer (IP) in Intel x86 microprocessors, and sometimes called the instruction address register, or just part of the instruction sequencer in some computers, is a processor register that indicates where the computer is in its instruction sequence. Depending on the details of the particular computer, the PC or IP holds either the memory address of the instruction being executed, or the address of the next instruction to be executed. In most processors, the program counter is incremented automatically after fetching a program instruction, so that instructions are normally retrieved sequentially from memory, with certain instructions, such as branches, jumps and subroutine calls and returns, interrupting the sequence by placing a new value in the program counter. Such jump instructions allow a new address to be chosen as the start of the next part of the flow of instructions from the memory. They allow new values to be loaded (written) into the program counter register. A subroutine call is achieved simply by reading the old contents of the program counter, before they are overwritten by a new value, and saving them somewhere in memory or in another register. A subroutine return is then achieved by writing the saved value back in to the program counter again.

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Working of a simple program counter: The central processing unit (CPU) of a simple computer contains the hardware (control unit and arithmetic logic unit) that executes the instructions, as they are fetched from memory. Most instruction cycles consist of the CPU sending an address, on the address bus, to memory, which then responds by sending the contents of that memory location as data, on the data bus. (This is tied up with the idea of the storedprogram computer in which executable instructions are stored alongside ordinary data in memory, and handled identically by it). The Program Counter (PC) is just one of the many registers in the hardware of the CPU. It, like each of the other registers, consists of a bank of binary latches (a binary latch is also known as a flip-flop), with one flip-flop per bit in the integer that is to be stored (32 for a 32-bit CPU, for example). In the case of the PC, the integer represents the address in memory that is to be fetched next. Once the data (the instruction) has been received on the data bus, the PC is incremented. In some CPUs this is achieved by adding 000..001 to its contents, and latching the result into the register to be its new contents; on most CPUs, though, the PC is implemented as a register that is internally wired so that it counts up to the next value when a specific signal is applied to it externally. Such a register, in electronics, is referred to as a binary counter, and hence the origin of the term program counter. (3). INSTRUCTION DECODER: The Instruction Decoder reads the next instruction in from memory, and sends the component pieces of that instruction to the necessary destinations. RISC Instruction Decoder: The RISC instruction decoder is typically a very simple device. Because RISC instruction words are a fixed length, the positions of the fields are fixed. We can decode an instruction, therefore, by simply separating the machine word into small parts using wire slices. CISC Instruction Decoder: Decoding a CISC instruction word is much more difficult than the RISC case, and the increased complexity of the decoder is a common reason that people cite when they choose to use RISC over CISC in their designs. A CISC decoder is typically set up as a state machine. The machine reads the opcode field to determine what type of instruction it is, and where the other data values are. The instruction word is read in piece by piece, and decisions are made at each stage as to how the remainder of the instruction word will be read. Input Format: The input file consists of multiple testcases. The first line of each testcase contains one integer, N. (1 <= N <= 100,000). The following N lines contain one instructions each. Input terminates with a line containing N=0, which must not be processed. Output Format: For each testcase print one integer in a single line, denoting the number of different values the register can take after code execution. B). Explain addressing modes of 8085 microprocessor with example. The 8085 Addressing Modes The instructions MOV B, A or MVI A, 82H are to copy data from a source into a destination. In these instructions the source can be a register, an input port, or an 8-bit number (00H to FFH). Similarly, a destination can be a register or an output port. The sources and destination are operands. The various formats for specifying operands are called the ADDRESSING MODES. For 8085, they are: 1. Immediate addressing. 2. Register addressing. 3. Direct addressing. 4. Indirect addressing.
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Immediate addressing: Data is present in the instruction. Load the immediate data to the destination provided. Example: MVI R,data Register addressing: Data is provided through the registers. Example: MOV Rd, Rs Direct addressing: Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port 01H. Example: IN 00H or OUT 01H Indirect Addressing: This means that the Effective Address is calculated by the processor. And the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored. Note that this requires several memory accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to retrieve the data which is to be loaded into the register. C). Draw and explain the block diagram of 8085 microprocessor architecture.

Control Unit: Generates signals within uP to carry out the instruction, which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur.
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Arithmetic Logic Unit: The ALU performs the actual numerical and logic operation such as add, subtract, AND, OR, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores result of operation in Accumulator. Registers: The 8085/8080A-programming model includes six registers, one accumulator, and one flag register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the program counter. They are described briefly as follows. The 8085/8080A has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit operations. The programmer can use these registers to store or copy data into the registers by using data copy instructions. Accumulator: The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is used to store 8-bit data and to perform arithmetic and logical operations. The result of an operation is stored in the accumulator. The accumulator is also identified as register A. Flags: The ALU includes five flip-flops, which are set or reset after an operation according to data conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and their bit positions in the flag register are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For example, after an addition of two numbers, if the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) is set to one. When an arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it is not used as a register; five bit positions out of eight are used to store the outputs of the five flip-flops. The flags are stored in the 8-bit register so that the programmer can examine these flags (data conditions) by accessing the register through an instruction. These flags have critical importance in the decision-making process of the microprocessor. The conditions (set or reset) of the flags are tested through the software instructions. For example, the instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY flag is set. The thorough understanding of flag is essential in writing assembly language programs. Program Counter (PC): This 16-bit register deals with sequencing the execution of instructions. This register is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit register. The microprocessor uses this register to sequence the execution of the instructions. The function of the program counter is to point to the memory address from which the next byte is to be fetched. When a byte (machine code) is being fetched, the program counter is incremented by one to point to the next memory location Stack Pointer (SP): The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-bit address in the stack pointer. The stack concept is explained in the chapter "Stack and Subroutines." Instruction Register/Decoder: Temporary store for the current instruction of a program. Latest instruction sent here from memory prior to execution. Decoder then takes instruction and decodes or interprets the instruction. Decoded instruction then passed to next stage. Memory Address Register: Holds address, received from PC, of next program instruction. Feeds the address bus with addresses of location of the program under execution.

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Control Generator: Generates signals within uP to carry out the instruction which has been decoded. In reality causes certain connections between blocks of the uP to be opened or closed, so that data goes where it is required, and so that ALU operations occur. Register Selector: This block controls the use of the register stack in the example. Just a logic circuit which switches between different registers in the set will receive instructions from Control Unit. General Purpose Registers: uP requires extra registers for versatility. Can be used to store additional data during a program. More complex processors may have a variety of differently named registers. Microprogramming: How does the P knows what an instruction means, especially when it is only a binary number? The microprogram in a uP/uC is written by the chip designer and tells the uP/uC the meaning of each instruction uP/uC can then carry out operation. Q.2). a). Explain 1) CMA: COMPLEMENT ACCUMULATOR: These instructions are 1-byte instructions. In this instruction the accumulator is assumed to be the implicit operand. This instructions are stored in 8-bit binary format in memory; it requires one memory location. & no flags are affected. Op-code : CMA. Operand: NONE. Bytes: 1. M-Cycles: 1. T-States: 4. Task : Invert (compliment) each bit in the accumulator. Binary code: 0010 1111 Hex code: 2FH Example: Complement the accumulator, which has data byte 89H. Instruction: CMA Hex Code : 2F (A) 1 0 0 0 1 0 0 1 = 89H After CMA, (A) 0 1 1 1 0 1 1 0 = 76H 2) RRC: ROTATE ACCUMULATOR RIGHT: Each bit in the accumulator can be shifted right to the next position. Bit D0 is placed in the position of D7 as well as in the Carry flag. Op-code : RRC. Operand: NONE. Bytes: 1. M-Cycles: 1. T-States: 4. Binary code: 0000 1111 Hex code: 0FH Flags: CY is modified according to bit D0. S, Z, P, AC are not affected. Example: Rotate the content of the accumulator right, if it contains A7H & the Carry flag is reset to 0. Instruction: RRC Hex Code : 0F (A) (A) 1 0 1 0 0 1 1 1 1 1 0 1 0 0 1 1 & CY & CY 0 1

After RRC,

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3) RET: RETURN FROM SUBROUTINE UNCONDITIONALLY. The program sequence is transferred from the subroutine to the calling program. The two bytes from the top of the stack are copied into the program counter and the program execution begins at the new address. The instruction is equivalent to POP Program Counter. Op-code : RET. Operand: NONE. Bytes: 1. M-Cycles: 3. T-States: 10. Binary code: 1100 1001 Hex code: C9H Flags: No flags are affected. Example: Assume the SP is pointing to location 2095H. Explain the effect of the RET instruction if the contents of the SP are as follows: 2095 50 2096 20 After the RET, the program execution is transferred to location 2050H & the SP is shifted to location 2097H. Comment: This instruction is used in conjunction with CALL or conditional call instruction. W.A.P to load two unsigned number 42H and 67H respectively in register B and register C. Subtract C from B. if the result is in 2s complement, convert the result in absolute magnitude and display it at PORT1. Otherwise display the positive result.

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B) Design an memory interfacing circuit for a given 4K ROM chip. Use all 16 address line. Use any combination of inverter, Nand gate and 74LS138 decoder to generate the address. Determine the memory map of the design.

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Explain need and list of branching instructions of 8085. W.a.p to find whether the given number stored in memory location 8000H is positive, negative or zero. If number is positive place FFH, if number is negative place FEH and if number is zero place FDH in memory location 8050H. The branching instructions alter normal sequential program flow, either unconditionally or conditionally. The unconditional branching instructions are as follows: JMP CALL RET Jump Call Return

Conditional branching instructions examine the status of one of four condition flags to determine whether the specified branch is to be executed. The conditions that may be specified are as follows: NZ Z NC C PO PE P M Not Zero (Z = Zero (Z = 1) No Carry (C = Carry (C = 1) Parity Odd (P Parity Even (P Plus (S = 0) Minus (S = 1) 0) 0) = 0) = 1)

Thus, the conditional branching instructions are specified as follows: Jumps C INC JZ JNZ JP JM JPE JP0 Calls CC CNC CZ CNZ CP CM CPE CPO Returns RC RNC RZ RNZ RP RM RPE RPO (Carry) (No Carry) (Zero) (Not Zero) (Plus) (Minus) (Parity Even) (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program counter: PCHL RST Move H & L to Program Counter Special Restart Instruction Used with Interrupts

PROGRAM:

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Q.3). Explain 1) Ready: (Input) If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle. 2) INTR: (Input) INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted 3) ALE: (Output) Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated. Draw and explain the timing diagram of instruction MVI A,32H. Find execution time required, if clock frequency is 2MHz. Each instruction requires specific time for the execution of instruction and this time is called instruction cycle. Each instruction cycle consists 1 to 5 machine cycle -- opcode fetch, memory read, memory write, IO read, IO write and each machine cycle consist 3 to 6 T - states. Time required to execute 1 T-state = 1/ operating frequency of 8085 Microprocessor for example operating frequency = 2MHz then time required to execute 1 T-state = 0.5 uSec

The MVI instruction in the 8085 microprocessor contains 7 or 10 T-Cycles, each one clock cycle, not including wait states. Each cycle starts on the falling edge of CLK. <> <> <> T1a - ALE goes high for one half clock. During this time, S0, S1, IO/M-, A15-A8, and AD7-AD0 become valid, and are guaranteed valid at the falling edge of ALE. (AD7-AD0 represent A7-A0, and must be strobed by external hardware.) A15-A0 will be the address of the MVI instruction. Somewhat after ALE, AD7-AD0 will float.

T2a - RD- goes low for one clock cycle. While RD- is low, the external hardware has permission to drive AD7-AD0. It must supply the opcode for MVI. READY is sampled at the beginning of T2 - If it is low, T2 will be repeated, until READY is sampled high.

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T3a - RD- remains low for one more half clock cycle. The external hardware must guarantee AD7-AD0 valid by the beginning of T3a. The 8085 samples AD7-AD0 at the beginning of T3a. This will give it the MVI opcode. T4a - Nothing happens externally. All lines persist their prior state. The 8085 processes the MVI opcode and sets itself up for the required actions. T1b - This is the same timing as T1a, except that the address is one greater. T2b - This is the same timing as T2a. During this time, the external hardware must drive the immediate value of the MVI instruction onto AD7-AD0. T3b - This is the same timing as T3a. At the conclusion of T3b the 8085 knows the value to store in the destination. If the destination was an internal register, the instruction is complete. If the destination was M, the cycles continue. T1c - This is the same timing as T1a, except that the address is the contents of the HL register, H sent on A15-A8, and L sent on AD7-AD0. T2c - This is the same timing as T1a, except that WR- is used instead of RD-, and the AD7-AD0 lines do not float - they emit the immediate value retrieved in T3b. The AD7-AD0 line will change sometime between ALE and WR-. T3c - This is the same timing as T3a, except that WR- goes high at the beginning instead of at the halfway point. The external hardware is expected to save the AD7-AD0 lines into the address specified during T1c on the rising edge of WR-. The 8085 will persist the AD7-AD0 lines for one half clock cycle to guarantee the AD7-AD0 lines. MVI A,32H 7 T states Td=M+[(count)x N) -3]. Where M= no. of T states outside loop. N=no. of T states inside loop.

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B). Draw and explain the block diagram of 8255A programmable peripheral port.

Data Bus Buffer: It is an 8 bit data buffer used to interface 8255 with 8085. It is connected to D0-D7 bits of 8255. Read/write control logic:It consists of inputs RD,WR,A0,A1,CS . RD,WR are used for reading and writing on to 8255 and are connected to MEMR,MEMW of 8085 respectively. A0,A1 are Port select signals used to select the particular port . CS is used to select the 8255 device . It is controlled by the output of the 3:8 decoder used to decode the address lines of 8085. Group A and Group B Control:
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 Group A control consists of Port A and Port C upper. Group B control consists of Port A and Port C lower. Each group is controlled through software. They receive commands from the RD, WR pins to allow access to bit pattern of 8085. The bit pattern consists of : 1. Information about which group is operated. 2. Information about mode of Operation. A0,A1 decide the port to be used in 8255. A1 0 0 1 1 A0 0 1 0 1 Selected port Port A Port B Port C Control Register

PORT A,B:These are bi-directional 8 bit ports each and are used to interface 8255 with CPU or peripherals. Port A is controlled by Group A while Port B is controlled by Group B Control. PORT C: This is a bi-directional 8 bit port controlled partially by Group A control and partially by Group B control . It is divided into two parts Port C upper and Port C lower each of a nibble. It is used mainly for control signals and interfacing with peripherals. 8255 MODES:

Mode 0 : Simple I/O Any of A, B, CL and CH can be programmed as input or output

Mode 1: I/O with Handshake A and B can be used for I/O C provides the handshake signals

Mode 2: Bi-directional with handshake A is bi-directional with C providing handshake signals B is simple I/O (mode-0) or handshake I/O (mode-1)
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BSR (Bit Set Reset) Mode Only C is available for bit mode access. Allows single bit manipulation for control application

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