Middle East Technical University Department of Computer Engineering LAB-3 Due to: Part 1: Sunday, April 15, 2012,

23:55hrs Part 2: Sunday, April 22, 2012, 23:55hrs Submission: via COW

CENG232 Spring 2011-12

Introduction
This assignment aims to make you familiar with Verilog language, related software tools, and the FPGA boards. There are two parts in this assignment. The first part is a Verilog simulation of an imaginary flip-flop design, which you are required to implement and test on your own. The second part consists of simulation and implementation (on FPGA) of a vending machine. The first part has a deadline of 1 week, and the second part has a deadline of 2 weeks, both beginning at the announcement of the laboratory assignment.

Part 1: AB Flip Flop (Individual Work)

This part of the lab will be performed and submitted individually. You are given a specification of a new type of flip-flop, and a new 74xxx series chip that uses the flip flop. Your task is to implement these in Verilog, and prove that they work according to their specifications by simulation.

Problem Definition
1.a. Implement the following AB flip-flop in Verilog with respect to the provided truth table. A A CLK B AB Flip-Flop Q 0 0 1 1 X B 0 1 0 1 X CLK Q X Q Q X Q Qnext 0 Q' Q' 1 Q

The AB Flip-Flop changes its state only at rising clock edges. Note that there is no no change action of the flip-flop, either it is reset, it is set, or it toggles its value. 1

1.b. Implement the following IC74999 chip that contains 2 AB flip-flops. The chip has an output X which is set to 1 when the outputs of the flip-flops differ, and 0 otherwise

A0 B0 A1 B1

A B A B

Q0

Q1
X

CLK

Use the following module definitions for the modules:

module abflipflop(input a, input b, input clk, output reg q) module ic74999(input a0, input b0, input a1, input b1, input clk, output q0, output q1, output x)

Simulation
A sample testbench for abflipflop module will be provided to you. It is your responsibility to extend the testbench, and also to write a testbench for ic74999 module.

Deliverables
Implement both modules in a single Verilog file: lab3_1.v. Do NOT submit your testbenches. You can share your testbenches on the newsgroup. Submit the file through the COW system before the given deadline. April 15, 2012, 23:55hrs This part is supposed to be done individually, not with your partner. Any kind of cheating is not allowed.

Part 2: Basic Vending Machine (Teamwork)

This part of the lab will be performed and submitted with your group partner. Only submit a single copy per group. In this part, you are going to code basic functionality of a vending machine as a Verilog module. Money can be deposited into the vending machine, multiple products may be ordered, and the machine will give back the remainder amount in coins. Although the vending machine works synchronously, there will be an asynchronous reset function.

Problem Definition
Your basic vending machine (BVM) module will have the following inputs and outputs: Name Keypad Mode CLK RESET Credits Coins Input Input Input Input Output Output Type 3-bits 2-bits 1-bit 1-bit 8-bits 6-bits Size

BVM can operate in one the following four modes of operation: 1. Do-nothing mode (DN) 2. Money-deposit mode (MD) 3. Product-receive mode (PR) 4. Return remainder of money (RR) MD, PR and RR modes will be synchronized to clock input (CLK) and input will take effect with the rising edge of clock. In DN mode, changes in CLK input won't have any effect. BVM will work according to the following mechanism: 1. Initially the machine will be in DN mode, waiting for a customer. Credits and Coins outputs are equal to zero. 2. When a customer deposits a money into the vending machine, Mode will be set to MD, and Keypad will reflect the type of money that is inserted. With the rising edge of clock (CLK input), BVM will read and deposit the amount of money represented by Keypad input. Credits output should be incremented by the amount represented by Keypad input. 3. The customer can continue depositing money into the vending machine. Each money bill will be deposited in a separate clock cycle. 4. After depositing of money is done, Mode will be set to PR, and customer will enter the code of the desired product by setting Keypad. With the rising edge of CLK, BVM will decrement the amount of Credits by selected product's price. 5. The customer can receive multiple products from the vending machine. Each product will be dispensed in a separate clock cycle. 6. After customer receives all products she wants, she switches Mode to RR to receive remainder of money in coins. Each bit of Coins output corresponds to one type of coin. Only a single coin can be dispensed in a clock cycle. Remainder of money is returned by turning corresponding coin bit to 1. 7. Until Credits reaches to 0, BVM will continue to dispense coins in each clock cycle. 3

Formats of inputs and outputs in each mode are explained in more detail below: Do nothing mode (DN 00) BVM can be switched to this mode by setting Mode to 00. In this mode, no output shall change when the clock input comes. Money deposit mode (MD 01) BVM can be switched to this mode by setting Mode to 01. This mode allows customer to deposit money to the machine. The amount of money represented by Keypad input is determined according to the following table: Value of Keypad input 000 001 010 011 100 101 110 111 Amount represented 1 TL 2 TL 5 TL 10 TL 20 TL 50 TL 100 TL 200 TL

With the rising edge of CLK, the amount represented by Keypad will be deposited to the machine and Credits output shall be incremented by that amount. Credits will always represent the amount of money available in the machine in the binary form. Rightmost bit will be the least significant. Product receive mode (PR 10) BVM can be switched to this mode by setting Mode to 10. This mode will decrement amount of money deposited by the amount of desired product's price. Desired product is selected by setting product code using Keypad input. Product codes, product names and their prices are given in the table below: Product code 000 001 010 011 100 101 110 Soda Soda (Diet) Biscuit Water Candy Chocolate Product Name Sandwich 220 120 180 55 13 25 85 Price

Product code 111 Cracker

Product Name 75

Price

After the product code is set, with the rising edge of CLK, the price of product is subtracted from the available Credits. If available credits is less than the price of product, the product is not dispensed and there should be no change in credits. Return remainder of money (RR 11) BVM can be switched to this mode by setting Mode to 11. When the customer is done with purchasing products, this mode will be used to dispense the remainder credits. Each bit of Coins output corresponds to a specific amount of coin. With each rising edge of CLK the machine will dispense a single coin (i.e. one bit of Coins will be 1 at a time which corresponds to the coin returned to the customer), starting from the coin with highest possible value. Each time a coin is dispensed to the customer, Credits will be decremented by the value of returned coin. Bits of Coins and corresponding coins are given in the following table: Bit of Remainder Value of coin RESET input The machine has an asynchronous RESET input which will take effect immediately (without waiting for change in CLK) and reset all outputs to zero. 5th 50 TL 4th 20 TL 3rd 10 TL 2nd 5 TL 1st 2 TL 0th (LSB) 1 TL

Specifications
1. Maximum amount of money that can be available in the machine is 255 (when all bits of Credits are one). 2. There should not be overflow in Credits. If amount of money will exceed 255 when customer tries to deposit more money, the machine won't accept the money and value Credits won't change. (if Credits=70 and customer tries to deposit 200TL, Creditsnew will still be 70) 3. Minimum amount of money that can be available in the machine is zero (when all bits of Credits is zero). 4. There should not be underflow in Credits in PR and RR modes. 5. In PR mode, if price of the desired product is larger than available amount of money, there should not be any change in Credits with the rising edge of CLK. 6. In RR mode, if Credits is 0 when rising edge of CLK is received, no new coins shall be dispensed (all Coins outputs are set to 0). 7. When machine is switched to RR mode from another mode, all bits of Remainder should be zero until rising edge of CLK dispensing of coins start at the receipt of rising CLK edge. 8. When machine is not in RR mode, all bits of Coins should be 0.

Use the following Verilog definition for the module:

module BasicVendingMachine(input [2:0] Keypad, input [1:0] Mode, input CLK, input RESET, output reg [7:0] Credit, output reg [5:0] Coins)

Simulation
A sample testbench will be provided to you. This testbench is only a starting point, which you should extend for proper testing of all operations of the vending machine. Test your Verilog file in simulation mode first to find any problems, before moving on to FPGA implementation part.

FPGA Implementation
You will be provided with a Board232.v file (and a ready-to-use Xilinx project), which will bind inputs and outputs of the FPGA board with your Verilog module. You are required to test your Verilog module on the FPGA boards. After the submission date, you will make a demo to course assistants. Name Keypad Mode CLK RESET Credit Coins FPGA Board SW2, SW1, SW0 SW7, SW6 BTN3 BTN0 7-segment displays LD5, LD4, LD3, LD2, LD1, LD0 Right-most 6 leds (F) Description Right-most 3 switches (A) Left-most 2 switches (B) Left-most button (C) Right-most button (D)

F B A C D

Deliverables
Implement your module in a single Verilog file: lab3_2.v. Do NOT submit your testbenches. You may share your testbenches on the newsgroup. Submit the file through the COW system before the given deadline. April 22, 2012, 23:55hrs This part is supposed to be done with your group partner. Make sure both of you take roles in implementation of the project. Any kind of inter-group cheating is not allowed. Use the newsgroup metu.ceng.course.232 for any questions regarding the homework. You will make a demo with the FPGA board the next week after the submissions (in your lab session hours). The exact dates and place will be announced later. 6