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User Guide
Table of Contents
i
6234CATARM22-Mar-07
Table of Contents
ii
6234CATARM22-Mar-07
Section 1 Overview
1.1
Scope
The AT91SAM9260-EK evaluation kit enables the evaluation of and code development for applications running on an AT91SAM9260 device. This guide focuses on the AT91SAM9260-EK board as an evaluation platform. The board supports the AT91SAM9260 in an LFBGA217 package as well as in a PQFP208 package.
1.2
Deliverables
The AT91SAM9260-EK package contains the following items: ! an AT91SAM9260-EK board ! universal input AC/DC power supply with US and Europe plug adapter ! one A/B-type USB cable ! one serial RS232 cable ! one RJ45 crossed Ethernet cable ! one CD-ROM that allows the user to begin evaluating the AT91 ARM Thumb 32-bit microcontroller quickly.
1.3
The board is equipped with an AT91SAM9260 (217-ball LFBGA package) together with the following: ! 64 Mbytes of SDRAM memory ! 256 Mbytes of NANDFlash memory ! one Atmel serial DataFlash ! one Atmel TWI serial EEPROM ! one USB device port interface ! two USB Host port interfaces ! one DBGU serial communication port ! one complete MODEM serial communication port
1-1
6234CATARM22-Mar-07
Overview
! one additional serial communication port with RTS/CTS handshake control ! JTAG/ICE debug interface ! one PHY Ethernet 100-base TX with three status LEDs ! one Atmel AT73C213 Audio DAC ! one Power LED and one general-purpose LED ! two user input push buttons ! one Wakeup input push button ! one reset push button ! one DataFlash, SD/MMC card slot ! four expansion connectors (PIOA, PIOB, PIOC, IMAGE SENSOR) ! one BGA-like EBI expansion footprint connector ! one Lithium Coin Cell Battery Retainer for 12 mm cell size
1-2
6234CATARM22-Mar-07
2.1
Electrostatic Warning
The AT91SAM9260-EK evaluation board is shipped in protective anti-static packaging. The board must not be subjected to high electrostatic potentials. A grounding strap or similar protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
2.2
Requirements
In order to set up the AT91SAM9260-EK evaluation board, the following items are needed: ! the AT91SAM9260-EK evaluation board itself. ! AC/DC power adapter (5V at 2A), 2.1 mm by 5.5 mm
2-1
6234CATARM22-Mar-07
2.3
Layout
2-2
6234CATARM22-Mar-07
2.4
The AT91SAM9260-EK requires 5V DC (5%). DC power is supplied to the board via the 2.1 mm by 5.5 mm socket J1. Coaxial plug center positive standard.
2.5
The user has the possibility to plug a battery (3V Lithium Battery CR1225 or equivalent) in order to permanently power the backup part of the device. In this case, J10 configuration must be set in position 1, 2. Refer to Section 4.1.
2.6
Getting Started
The AT91SAM9260-EK evaluation board is delivered with a CD-ROM containing all necessary information and step-by-step procedures for working with the most common development toolchains. Please refer to this CD-ROM, or to the AT91 web site, http://www.atmel.com/products/AT91/, for the most up-to-date information on getting started with the AT91SAM9260-EK.
2-3
6234CATARM22-Mar-07
2-4
PA[0..31] AT91SAM9260 D[0..31] A[0..22] A[0..14] A[0..14] RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 BA0 BA1 RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE NBS1 NBS3 A16 A17 SHDN PC[0..15] RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 D[0..31] A[0..22] D[0..31] MEMORY PIO
2.7
5VDC
MCLK SDIN LRFS BCLK SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 PB[0..31] PB[0..31] DBGU_TXD DBGU_RXD PIO PIO D[0..15] NANDOE NANDWE
DAC
AT73C213
NRST
NRST
01 - POWER SUPPLY
SERIAL INTERFACES
DBGU
DTXD DRXD
PB15 PB14
SDRAM
RS232
USB
HOST A
HDMB HDPB PA[0..31] ETXCK/REFCLK
HDMA HDPA
HDMA HDPA
HOST B
HDMB HDPB
05 - COMMUNICATION
RMII_MII ETHERNET
TX_CLK
PA19
RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFWE_NWE_NWR0 NBS1 NBS3 CFOE_NRD NANDOE NANDWE NCS0 NRST PA[0..31] PB[0..31] PC[0..15] NRST PA[0..31] PB[0..31] PC[0..15]
RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 CFOE_NRD NANDOE NANDWE NCS0 NRST PA[0..31] PB[0..31] PC[0..15]
TXD3 TXD2 TXD1 TXD0 TX_EN ERX3 ERX2 ERX1 ERX0 ERXCK ERXDV ETXER ERXER ECOL ECRS EMDC EMDIO PIO
RX_CLK RX_DV
PA27 PA17
TX_ER RX_ER
PA22 PA18
COL CRS
PA29 PA28
NRST
NRST 02 - AT91SAM9260
03 - RMII_MII ETHERNET
6234CATARM22-Mar-07
POWER SUPPLY
POWERLED
PA9
SHDN
COM0
TXD0 RXD0 RTS0 CTS0 DTR0 DSR0 DCD0 RI0 SPI0_MISO MCDB0 MCDB1 MCDB2 SPI0_NPCS0 MCDB3 MCCK SPI0_MOSI MCCDB
PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 PA0 PA5 PA4 PA3 PA8 PA1
DAT0 DAT1 DAT2 DAT3 CLK CMD PA2 PC11 NRST SCK CS NRST
CARD READER
COM1
PC[0..15]
SPI0_SPCK SPI0_NPCS1
TWCK TWD
PA24 PA23
DEVICE
SCL SDA
3.1
AT91SAM9260 Microcontroller
Incorporates the ARM926EJ-S ARM Thumb Processor DSP Instruction Extensions, ARM Jazelle Technology for Java Acceleration 8-KByte Data Cache, 8-KByte Instruction Cache, Write Buffer 200 MIPS at 180 MHz Memory Management Unit EmbeddedICE, Debug Communication Channel Support Additional Embedded Memories One 32-KByte Internal ROM, Single-cycle Access At Maximum Matrix Speed Two 4-KByte Internal SRAM, Single-cycle Access At Maximum Matrix Speed External Bus Interface (EBI) Supports SDRAM, Static Memory, ECC-enabled NANDFlash and CompactFlash USB 2.0 Full Speed (12 Mbits per second) Device Port On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-lead PQFP Package and Double Port in 217-ball LFBGA Package Single or Dual On-chip Transceivers Integrated FIFOs and Dedicated DMA Channels Ethernet MAC 10/100 Base T Media Independant Interface or Reduced Media Independant Interface 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Image Sensor Interface ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate 12-bit Data Interface for Support of High Sensibility Sensors SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format Bus Matrix Six 32-bit-layer Matrix Boot Mode Select Option, Remap Command Fully-featured System Controller, including Reset Controller, Shutdown Controller Four 32-bit Battery Backup Registers for a Total of 16 Bytes Clock Generator and Power Management Controller Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer and Real-time Timer Reset Controller (RSTC) Based on a Power-on Reset Cell, Reset Source Identification and Reset Output
3-1
6234CATARM22-Mar-07
Board Description
Control Clock Generator (CKGR) Selectable 32768Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock 3 to 20 MHz On-chip Oscillator, One up to 240 MHz PLL and One up to 130 MHz PLL Power Management Controller (PMC) Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) Individually Maskable, Eight-level Priority, Vectored Interrupt Sources Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-time Timer (RTT) 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler One 4-channel 10-bit Analog-to-Digital Converter Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC) 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Input Change Interrupt Capability on Each I/O Line Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output High-current Drive I/O Lines, Up to 16 mA Each Peripheral DMA Controller Channels (PDC) One Two-slot MultiMedia Card Interface (MCI) SDCard/SDIO and MultiMediaCard Compliant Automatic Protocol Control and Fast Automatic Data Transfers with PDC One Synchronous Serial Controller (SSC) Independent Clock and Frame Sync Signals for Each Receiver and Transmitter IS Analog Interface Support, Time Division Multiplex Support High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation, Manchester Encoding/Decoding Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Full Modem Signal Control on USART0 Two 2-wire UARTs Two Master/Slave Serial Peripheral Interfaces (SPI) 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects Synchronous Communications Two Three-channel 16-bit Timer/Counters (TC) Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
3-2
6234CATARM22-Mar-07
Board Description
High-Drive Capability on Ouputs TIOA0, TIOA1, TIOA2 One Two-wire Interface (TWI) Master, Multi-master and Slave Mode Operation General Call Supported in Slave Mode Connection to PDC Channel To Optimize Data Transfers in Master Mode Only IEEE 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: 1.65V to 1.95V for VDDBU, VDDCORE, VDDOSC and VDDPLL 3.0V to 3.6V for VDDIOP0, VDDIOP1 (Peripheral I/Os) and VDDANA (Analog to Digital Converter) Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os) Available in a 208-lead PQFP and 217-ball LFBGA Package
3-3
6234CATARM22-Mar-07
JT AG
SE
MASTER
SLAVE
BM
ARM926EJ-S Processor
ICache 8 Kbytes MMU Bus Interface DCache 8 Kbytes
I_ M IS CK I_ IS PC I_ K IS DO I_ -I V IS SY SI_ I_ N D7 HS C YN C HD HD PA M A HD PB HD M B
IS
-M CD CD MC B3 A0 CD -M B C M DA CC 3 D M A CC K
B0
CD
SPI0_, SPI1_
DD DDM P
6234CATARM22-Mar-07
3-4
Transc.
Board Description
USB OHCI
PMC PLLA PLLB OSC WDT RC OSCSEL XIN32 XOUT32 SHDN WKUP VDDBU VDDCORE NRST OSC PIT 4GPREG RTT PIOA SHDC POR POR RSTC APB PIOB PIOC ROM 32 Kbytes I
DMA
XIN XOUT
Peripheral Bridge
EBI
CompactFlash NAND Flash
SDRAM Controller PDC MCI PDC TWI PDC USART0 USART1 USART2 USART3 USART4 USART5 PDC SPI0 SPI1 TC0 TC1 TC2 TC3 TC4 TC5 PDC SSC PDC 4-channel 10-bit ADC DPRAM USB Device Static Memory Controller ECC Controller Transceiver
D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE D16-D31 NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS
Board Description
3.3
Microcontroller
! One LFBGA 217-ball fitted on board ! One LQFP 208-lead footprint To try the microcontroller in the LQFP package, the user has to unsolder MN4 and solder the PQFP208 microcontroller on the MN6 footprint.
3.4
Memory
! 32 Kbytes of Internal ROM ! Two 4-KByte Internal SRAM ! Atmel serial DataFlash ! 64 Mbytes of SDRAM memory (32-bit bus width) ! 256 Mbytes of NANDFlash memory (8-bit bus width) ! TWI serial EEPROM
3.5
Clock Circuitry
! 18.432 MHz standard crystal for the embedded oscillator ! Selectable 32768Hz Low-power external standard crystal Oscillator or Internal Low Power RC Oscillator
3.6
Reset Circuitry
! Internal reset controller with bi-directional reset pin ! External reset pushbutton
3.7
Shutdown Controller
3.8
! On-board 1.8V High Efficiency step-down charge pump regulator with shutdown control ! On-board 3.3V linear regulator with shutdown control
3.9
Remote Communication
! One serial interface (DBGU COM Port) via RS-232 DB9 male socket ! One complete modem serial interface (COM Port 0) via RS-232 DB9 male socket ! One additional serial interface (COM Port 1) with RTS/CTS handshake control via RS-232 DB9 male socket ! USB V2.0 full-speed compliant, 12 Mbits per second (UDP) ! Two(1) USB Host ports V2.0 full-speed compliant, 12 Mbits per second (UHP) ! One Ethernet 100-base TX with three status LEDs
3-5
6234CATARM22-Mar-07
Board Description
3.10
! One Atmel stereo audio DAC (AT73C213) ! One 32 Ohm/20 mW Stereo Headset output (J4) with master volume and mute controls
3.11
User Interface
! Two user input pushbuttons(2) ! One user green LED ! One yellow power LED (can be also software controlled)
3.12
Debug Interface
3.13
Expansion Slot
! One DataFlash, SD/MMC card slot ! All I/Os of the AT91SAM9260 are routed to peripheral extension connectors ! All I/Os of the AT91SAM9260 Image Sensor Interface are routed to peripheral extension connectors ! All EBI Signals of the AT91SAM9260 are routed to extension footprint connectors (J25) This allows the developer to check the integrity of the components and to extend the features of the board by adding external hardware components or boards.
Notes: 1. Only one available with the 208-lead PQFP package. 2. Not available with the 208-lead PQFP package.
3-6
6234CATARM22-Mar-07
Board Description
3.14
PIO Usage
3-7
6234CATARM22-Mar-07
Board Description
3-8
6234CATARM22-Mar-07
Board Description
3-9
6234CATARM22-Mar-07
Board Description
3-10
6234CATARM22-Mar-07
Section 4 Configuration
4.1
Jumpers
Table 4-1. Jumpers Configuration
Designation JP2 JP3 Default Setting Closed Closed 3.3V Jumper
(1)
Feature
Forces power on. To use the software shutdown control, J3 must be opened. 3V battery backup must be present and J10 jumper set in position 1-2 VDDPLL Jumper(1) Enables boot on the internal ROM Enables boot on the NCS0 Slow Clock OSCSEL 1-2: Internal RC Oscillator 2-3: External Crystal Oscillator VDDBU Jumper select (1) 1-2: Lithium 3V Battery 2-3: 1.8V from VDDCORE VDDCORE Jumper(1) Enables Ethernet Auto MDIX control
JP6 JP7
JP9
2-3
JP10
2-3
Closed Closed
1. These jumpers are provided for power consumption measurement use. By default, they are closed. To use this feature, the user has to open the strap and insert an anmeter.
4-1
6234CATARM22-Mar-07
Configuration
4.2
JTAG/ICE
Table 4-2. JTAG/ICE Configuration
Designation S1 S2 S3 R13 R14 Default Setting Opened Opened Opened Soldered Soldered Feature Disables the ICE NTRST input Selects ICE mode or JTAG mode (See Errata) Disables TCK <-> RTCK local loop. If S3 is closed, R13 must be unsoldered. Enables the ICE RTCK return. S3 must be opened Enables the ICE NRST input
4.3
Microcontroller Clock
4.4
Memory
Table 4-4. Memory Configuration
Designation SDRAM R31 R32 NANDFlash (MN6x) R36 R34 S6 Soldered Soldered Opened Enables the use of NANDFlash (MN6x) Enables the use of Ready Busy signalDisables write protect Soldered Soldered Enables MN7 Chip select access Enables MN8 Chip select access Default Setting Feature
SERIAL DATAFLASH (MN9) R40 S5 Soldered Opened Enable the use of the Serial DataFlash (MN9) Disables the write protect.
TWI SERIAL EEPROM (MN10) R46 R47 Soldered Soldered Enables SCL access Enables SDA access
4-2
6234CATARM22-Mar-07
Configuration
4.5
Ethernet
RMII is the factory default mode. To evaluate the MII mode, the user has to unsolder R49, R50, R127 and close S7 and S8. When the RMII mode is used, the user can use the specific MII signals as PIO, but the following resistors must be unsoldered (R119 to R126).
4.6
Miscellaneous
Refer to the TOP level schematic for the PIO usage. Table 4-5.
Designation R82 R72 R73 Default Setting Soldered Soldered Soldered Feature USB DEVICE: Enables the use of the USBCNX signal DBGU COM Port: Enables the use of DTXD output signalEnables the use of DRXD input RS232 COM Port 0: Enable the use of outputs signal R94 R95 R96 Soldered RTS0 TXD0 DTR0 RS232 COM Port 0: Enable the use of inputs signal R98 R101 R103 R104 R105 R106 DCD0 DSR0 RXD0 CTS0 RI0 Enables all MAX3241E outputs buffer RS232 COM Port 1: Enable the use of outputs signal R83 R85 Soldered TXD1 RTS1 RS232 COM Port 1: Enable the use of inputs signal R86 R88 TP1 TP2 TP3 TP4 TP5 TP6 Soldered N.A N.A N.A N.A N.A N.A RXD1 CTS1 GND Test point GND Test point. GND Test point. GND Test point. Reserved: do not use Reserved: do not use
Soldered
4-3
6234CATARM22-Mar-07
Configuration
4-4
6234CATARM22-Mar-07
Section 5 Schematics
5.1
Schematics
This section contains the following schematics: ! Board Layout - Top View ! Power supply and audio ! 217-ball BGA AT91SAM9260 Microcontroller ! 208-pin LQFP AT91SAM9260 Microcontroller ! Memory ! Ethernet ! Serial Interface ! Expansion and User Interface
5-1
6234CATARM22-Mar-07
POWER SUPPLY
PA[0..31]
AT91SAM9260
MEMORY
5VDC
POWERLED SHDN
PA9
PIO
D[0..31] A[0..22] SHDN RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3
D[0..31] A[0..22] A[0..14] RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE NBS1 NBS3 A16 A17 A22 A21 NANDOE NANDWE PC14 PC13 D[0..15] SPI0_MISO MCDB0 MCDB1 MCDB2 SPI0_NPCS0 MCDB3 MCCK SPI0_MOSI MCCDB SPI0_SPCK SPI0_NPCS1 PA0 PA5 PA4 PA3 PA8 PA1 PA2 PC11 NRST
D[0..31] A[0..14]
D
PC[0..15]
DAC
PCK0 TD0 TF0 TK0 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 PB[0..31] PB[0..31]
AT73C213
01 - POWER SUPPLY SERIAL INTERFACES PB15 PB14 PB4 PB5 PB26 PB27 PB24 PB22 PB23 PB25 PB6 PB7 PB28 PB29 PC[0..15]
DBGU
DTXD DRXD TXD0 RXD0 RTS0 CTS0 DTR0 DSR0 DCD0 RI0 TXD1 RXD1 RTS1 CTS1
DBGU_TXD DBGU_RXD
NANDOE NANDWE
PIO PIO
COM0
CARD READER
RS232
SDRAM
COM1
PC5
PIO
TWCK TWD
PA24 PA23
SCL SDA
03 - MEMORY
D[0..31] A[0..22]
RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE
TX_CLK TXD3 TXD2 TXD1 TXD0 TX_EN RXD3 RXD2 RXD1 RXD0 RX_CLK RX_DV TX_ER RX_ER COL CRS MDC MDIO MDINTR NRST
03 - RMII_MII ETHERNET
PA19 PA11 PA10 PA13 PA12 PA16 PA26 PA25 PA15 PA14 PA27 PA17 PA22 PA18 PA29 PA28 PA20 PA21 PA7 NRST
RAS CAS SDA10 SDWE SDCS_NCS1 SDCK SDCKE CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 CFOE_NRD NANDOE NANDWE NCS0
CFWE_NWE_NWR0
ERX3 ERX2 ERX1 ERX0 ERXCK ERXDV ETXER ERXER ECOL ECRS EMDC EMDIO PIO
CFOE_NRD
B A INIT EDIT
REV
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
MODIF.
DATE
SHEET
AT91SAM9260-EK
DIAGRAM
SCALE
1/1
1
1 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
3V3
R1 120R
REGULATED 5V ONLY
J1
5V
R3 100K
1 2
+ C1 330F
C2 10F 10V 2
POWER LED
R2 100K DS1 YELLOW R4 470K MN2 AT73C213
DOUT DIN CLK CS SMODE RSTB
CR1 5V
C3 10F
C4 10F
3
R5 Q1 IRLML2402 0R POWERLED
15 12 14 13 11 10 16 30 29 7
25 26 27 28 22 21 24 2 5 9 1
C7 10F C10 100NF C8 C9 100NF 100NF GND_DAC R6 0R
1 2
VDIG
C5 1F
C
C6 1F
Q2 6 Si1563EDH
4
5V
8 C1M 5 VIN
4 C2P VOUT 7
C11 R7 22F 150K
1V8
C1P C2M
6 31
J4 3.5 PHONEJACK STEREO 3 1 4 2 C16 + 100F 6V3
J3
FORCE POWER ON
C14 15PF
C12 10PF
C13 10F
2
R9 10K
3
R10 10K
32 4 3
C17 + 100F 6V3
FB 1 EN
MN3
10 2
R11 120K
HSR
GND 9
PG
HSL
20 17 19 18
R8 47R
SHDN
INGND
GNDB
GNDD
33
23
ADHESIVE FEET
Z3 11.1
B
Z4 11.1
Z5 11.1
Z6 11.1
B A INIT EDIT
REV
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
MODIF.
DATE
SHEET
AT91SAM9260-EK
POWER SUPPLY & AUDIO
SCALE
1/1
1
2 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
PC[0..15] PB[0..31] PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 D[0..31] A[0..22]
N16 M14 M15 M16 K14 P17 N17 M17 L16 L15 T5 P5 R5 P6 L17 K17 J17 K15 H17 J15 U5 U6 T6 R6 P7 U7 R8 U8 R9 T8 P9 P10
TO PQFP208 FOOTPRINT
TDI TMS TCK RTCK TDO NTRST JTAGSEL PLLRCA VDDPLL XOUT XIN XOUT32 XIN32 OSCSEL VDDBU WKUP TST BMS VREFP AVDD AGND VDDCORE VDDIOM VDDHISI 3V3
PA[0..31]
MN4
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31
R10 P11 T9 P12 R11 R12 T10 P13 T11 P14 R13 T12 U9 U10 U11 U12 U15 U14 U16 U13 T14 R14 T16 R15 R16 P16 P15 T17 L14 R17 N15 N14 C13 D13 E14 E15 D14 C14 J16 G17 H15 G16 J14 F16 H16 R1
SCK3/AD0/PC0 PCK0/AD1/PC1 PCK1/AD2/PC2 SPI1_NPCS3/AD3/PC3 SPI1_NPCS2/A23/PC4 SPI1_NPCS1/A24/PC5 CFCE1/TIOB2/PC6 CFCE2/TIOB1/PC7 RTS3/NCS4_CFCS0/PC8 TIOB0/NCS5_CFCS1/PC9 CTS3/A25_CFRNW/PC10 SPI0_NPCS1/NCS2/PC11 NCS7/IRQ0/PC12 NCS6/FIQ/PC13 IRQ2/NCS3_NANDCS/PC14 IRQ1/NWAIT/PC15 SPI0_NPCS2/D16/PC16 SPI0_NPCS3/D17/PC17 SPI1_NPCS1/D18/PC18 SPI1_NPCS2/D19/PC19 SPI1_NPCS3/D20/PC20 EF100/D21/PC21 TCLK5/D22/PC22 D23/PC23 D24/PC24 D25/PC25 D26/PC26 D27/PC27 D28/PC28 D29/PC29 D30/PC30 D31/PC31
TIOA3/SPI1_MISO/PB0 TIOB3/SPI1_MOSI/PB1 TIOA4/SPI1_SPCK/PB2 TIOA5/SPI1_NPCS0/PB3 TXD0/PB4 RXD0//PB5 TCLK1/TXD1/PB6 TCLK2/RXD1/PB7 TXD2/PB8 RXD2/PB9 ISI_D8/TXD3/PB10 ISI_D9/RXD3/PB11 ISI_D10/TXD5/PB12 ISI_D11/RXD5/PB13 DRXD/PB14 DTXD/PB15 TCLK3/TK0/PB16 TCLK4/TF0/PB17 TIOB4/TD0/PB18 TIOB5/RD0/PB19 ISI_D0/RK0/PB20 ISI_D1/RF0/PB21 ISI_D2/DSR0/PB22 ISI_D3/DCD0/PB23 ISI_D4/DTR0/PB24 ISI_D5/RI0/PB25 ISI_D6/RTS0/PB26 ISI_D7/CTS0/PB27 ISI_PCK/RTS1/PB28 ISI_VSYNC/CTS1/PB29 ISI_HSYNC/PCK0/PB30 ISI_MCK/PCK1/PB31
T3 T4 U3 U4 A17 A15 A16 B11 B16 C11 B12 B14 C12 B13 B15 G1 J4 J2 H1 J1 K2 K4 M4 N3 K1 L3 L2 N4 P4 R3 P3 M2
PA0/SPI0_MISO/MCDB0 PA1/SPI0_MOSI/MCCDB PA2/SPI0_SPCK PA3/SPI0_NPCS0/MCDB3 PA4/RTS2/MCDB2 PA5/CTS2/MCDB1 PA6/MCDA0 PA7/MCCDA PA8/MCCK PA9/MCDA1 PA10/MCDA2/ETX2 PA11/MCDA3/ETX3 PA12/ETX0 PA13/ETX1 PA14/ERX0 PA15/ERX1 PA16/ETXEN PA17/ERXDV PA18/ERXER PA19/ETXCK PA20/EMDC PA21/EMDIO PA22/ADTRG/ETXER PA23/TWD/ETX2 PA24/TWCK/ETX3 PA25/TCLK0/ERX2 PA26/TIOA0/ERX3 PA27/TIOA1/ERXCK PA28/TIOA2/ECRS PA29/SCK1/ECOL PA30/SCK2/RXD4 PA31/SCK0/TXD4 DDP DDM HDPA HDMA HDPB HDMB TDI TMS TCK RTCK TDO JTAGSEL NTRST N.C
N.C N.C
D15 C15
TP5 TP6
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 RAS CAS SDWE SDA10 SDCKE SDCK SDCS_NCS1 NCS0 CFOE_NRD CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 NANDOE NANDWE R16 1K BP1
B
RR1 100K
DDP DDM HDPA HDMA HDPB HDMB TDI TMS TCK RTCK TDO JTAGSEL NTRST
J5
2 4 6 8 10 12 14 16 18 20
1 3 5 7 9 11 13 15 ICE_NRST 17 19
4 3 2 1
ICE INTERFACE
ICE_NTRST S1
AT91SAM9260
ICE_RTCK R14 0R S3
NBS0/A0 NWR2/NBS2/A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0/A16 BA1/A17 A18 A19 A20 A21 A22 RAS CAS SDWE SDA10 SDCKE SDCK SDCS/NCS1 NCS0
5 6 7 8
3V3
R15
1K
PLLRCA
T1
PLLRCA CFOE/NRD CFWE/NWE/NWR0 CFIOR/NBS1/NWR1 CFIOW/NBS3/NWR3 NANDOE NANDWE NRST BMS TST XIN XOUT32 ADVREF VDDANA GNDANA
J6 1V8 VDDPLL
RESET
NRST
R17
100K
XOUT
F15 F17 U2
3V3
SMB MALE 1 2 3 4 5 J8
N1
R21
0R
VDDCORE
VDDCORE
VDDCORE
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM
VDDIOM
VDDIOM
VDDBU
WKUP
SHDN
NOT POPULATED
GNDBU
XIN32 OSCSEL
VDDIOP1
D17
VDDCORE
R4 R2
C27 100NF C28 100NF C29 10F 10V
D9
B17
E16
C17
D16
H14
M1
D11
G4
C16
U17
T13
P8
L4
J3
VDDBU
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
OSCSELF14
GND
J9
OUT
VDD
3 2 1
3 2 1
3V3 VDDCORE VDDIOM R27 0R C38 10F C39 C41 C44 100NF 100NF 100NF C40 C42 C43 C45 100NF 10F100NF 100NF 10V C46 100NF VDDHISI R28 0R
1K
R26 100K WKUP WAKE UP BP2 SHDN C32 100NF C33 C35 100NF 100NF C34 C36 100NF 100NF
C37 10F
C47 100NF
B A INIT EDIT
REV
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
MODIF.
DATE
SHEET
AT91SAM9260-EK
3V3
SCALE
1/1
1
AT91SAM9260-BGA217
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
3 8
PC[0..15] PB[0..31] PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC13 PC14 PC15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PC0 PC1 D[0..31] A[0..22]
21 22 23 26 27 28 163 164 165 166 167 168 171 172 175 176 177 178
9 10 11 12 15 16 17 18 19 20 161 162
PA[0..31]
MN6
NCS6/FIQ/PC13 IRQ2/NCS3_NANDCS/PC14 IRQ1/NWAIT/PC15 SPI0_NPCS2/D16/PC16 SPI0_NPCS3/D17/PC17 SPI1_NPCS1/D18/PC18 SPI1_NPCS2/D19/PC19 SPI1_NPCS3/D20/PC20 EF100/D21/PC21 TCLK5/D22/PC22 D23/PC23 D24/PC24 D25/PC25 D26/PC26 D27/PC27 D28/PC28 D29/PC29 D30/PC30 D31/PC31
TIOA3/SPI1_MISO/PB0 TIOB3/SPI1_MOSI/PB1 TIOA4/SPI1_SPCK/PB2 TIOA5/SPI1_NPCS0/PB3 TXD0/PB4 RXD0//PB5 TCLK1/TXD1/PB6 TCLK2/RXD1/PB7 TXD2/PB8 RXD2/PB9 ISI_D8/TXD3/PB10 ISI_D9/RXD3/PB11
DRXD/PB14 DTXD/PB15 TCLK3/TK0/PB16 TCLK4/TF0/PB17 TIOB4/TD0/PB18 TIOB5/RD0/PB19 ISI_D0/RK0/PB20 ISI_D1/RF0/PB21 ISI_D2/DSR0/PB22 ISI_D3/DCD0/PB23 ISI_D4/DTR0/PB24 ISI_D5/RI0/PB25 ISI_D6/RTS0/PB26 ISI_D7/CTS0/PB27 ISI_PCK/RTS1/PB28 ISI_VSYNC/CTS1/PB29 ISI_HSYNC/PCK0/PB30 ISI_MCK/PCK1/PB31
SCK3/AD0/PC0 PCK0/AD1/PC1
56 59 127 128 129 130 131 134 135 136 137 138 139 140 141 142 143 144 145
158 159
62 67 63 64 61 60 58 57
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29
179 180 181 182 183 184 185 186 189 190 191 192 193 194 195 196 197 198 201 202 205 206 207 208 1 2 3 4 7 8
PA0/SPI0_MISO/MCDB0 PA1/SPI0_MOSI/MCCDB PA2/SPI0_SPCK PA3/SPI0_NPCS0/MCDB3 PA4/RTS2/MCDB2 PA5/CTS2/MCDB1 PA6/MCDA0 PA7/MCCDA PA8/MCCK PA9/MCDA1 PA10/MCDA2/ETX2 PA11/MCDA3/ETX3 PA12/ETX0 PA13/ETX1 PA14/ERX0 PA15/ERX1 PA16/ETXEN PA17/ERXDV PA18/ERXER PA19/ETXCK PA20/EMDC PA21/EMDIO PA22/ADTRG/ETXER PA23/TWD/ETX2 PA24/TWCK/ETX3 PA25/TCLK0/ERX2 PA26/TIOA0/ERX3 PA27/TIOA1/ERXCK PA28/TIOA2/ECRS PA29/SCK1/ECOL
106 107 108 109 110 111 112 118 119 120 121 122 123 124 125 126 99 98 97 96 95 94 93 92 89 88 87 86 85 84 83 82 81 80 79 76 75 74 73 105 104 116 100 117 115 103 68 69 70 102 101 71 72 36 40 42 157 160 156
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 RAS CAS SDWE SDA10 SDCKE SDCK SDCS_NCS1 NCS0 CFOE_NRD CFWE_NWE_NWR0 CFIOR_NBS1_NWR1 CFIOW_NBS3_NWR3 NANDOE NANDWE NRST BMS TST VREFP AVDD C48 100NF AGND
B
55 54 51 50
AT91SAM9260
30 31 34 37 29 43 35 152
NBS0/A0 NWR2/NBS2/A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BA0/A16 BA1/A17 A18 A19 A20 A21 A22 RAS CAS SDWE SDA10 SDCKE SDCK SDCS/NCS1 NCS0
PLLRCA
B
PLLRCA CFOE/NRD VDDPLL GNDPLL VDDPLL GNDPLL XOUT BMS TST XIN XOUT32 ADVREF VDDANA GNDANA NANDOE NANDWE NRST CFWE/NWE/NWR0 CFIOR/NBS1/NWR1 CFIOW/NBS3/NWR3
VDDPLL
XOUT
150
XIN XOUT32
149 45
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOM
VDDIOM
VDDIOM
OSCSEL
OSCSEL
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
41
VDDIOM
GNDBU
VDDBU
XIN32
VDDIOP1
46
VDDCORE
147
174
203
114
132
187
199
169
C49 100NF
48
49
47
44
38
77
65
90
13
24
32
52
3V3 VDDHISI
B A INIT EDIT
C50 100NF C51 C53 C55 100NF 100NF 100NF C52 C54 100NF 100NF C56 C58 C60 C62 C64 C66 100NF 100NF 100NF 100NF 100NF 100NF C57 C59 C61 C63 C65 100NF 100NF 100NF 100NF 100NF
REV
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
MODIF.
DATE
SHEET
C67 100NF
AT91SAM9260-EK
AT91SAM9260-LQFP208
SCALE
1/1
1
4 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
A[0..14] D[0..31]
SDRAM
MN7 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 A14 SDCKE SDCK NBS0 SDA10 BA0 BA1 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 3V3 CAS RAS SDWE CAS RAS SDWE 37 38 15 39 17 18 16 19 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 3V3 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 SDA10 A13 BA0 BA1 A14 SDCKE SDCK A1 CFIOW_NBS3_NWR3 CAS RAS C68 C70 C72 C74 100NF 100NF 100NF 100NF C69 C71 C73 100NF 100NF 100NF 3V3 SDWE NBS2 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 37 38 15 39 17 18 16 19
MN8 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.C VDD VDD CKE VDD VDDQ CLK VDDQ VDDQ DQML VDDQ DQMH VSS CAS VSS RAS VSS VSSQ VSSQ WE VSSQ CS VSSQ 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 1 14 27 3 9 43 49 28 41 54 6 12 46 52 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 3V3
C75 C77 C79 C81 100NF 100NF 100NF 100NF C76 C78 C80 100NF 100NF 100NF
C
256 Mbits
R32 0R
R30 470K
256 Mbits
3V3 D[0..15]
NANDFLASH
DUAL FOOTPRINT
MN6A1 R37 470K 3V3 MN9 29 30 31 32 41 42 43 44 48 47 46 45 40 39 38 35 34 33 28 27 37 12 36 13 3V3 CLK 3V3 CMD DAT3 DAT2 3V3 D0 D1 D2 D3 D4 D5 D6 D7 8 1 2 4 R40 0R 3 SO SI SCK CS RESET VCC GND WP 6 7 5 S5 WRITE PROTECT NORMALLY OPEN
B
MN6B1 CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C
0R 0R 0R 470K 0R 1K 470K S6
16 17 8 18 9 7 19 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35
CLE ALE RE WE CE R/B WP N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C
C82 100NF
SERIAL DATAFLASH
3V3
R42 0R
DAT1 DAT0
C83 100NF
C85 100NF
8 7 6 5 4 3 2 1 9
NOT POPULATED
R44 10K R46
A
0R 0R
A0 A1 NC
1 2 3
SERIAL EEPROM
AT91SAM9260-EK
MEMORY
8 7 6 5 4 3 2
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
DATE
SHEET
SCALE
1/1
1
5 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1 OE 2 VSS
Y3
C87 100NF
C88 22PF 0R S7
Y4 25MHz
C89 22PF
SG-8002JC-50.0000M-PCB R49
C90
100NF GND_ETH
0R 0R 0R
42 17 18 19 20 21 22 26 27 28 29 34 37 16 38 36 35 24 25 32 39
3V3
REF_CLK/XT2 TXD3 TXD2 TXD1 TXD0 TX_EN TX_CLK/ISOLATE RXD3/PHYAD3 RXD2/PHYAD2 RXD1/PHYAD1 RXD0/PHYAD0 RX_CLK/10BTSER RX_DV/TESTMODE
XT1
43
15
TX+
J14 1 TD+
16
R51 49R9 1%
R52 49R9 1%
TX+
S8 R121 R122 0R 0R
4 CT TX8
VCCA
2 TD-
TX-
2
C
RXD3 RXD2 RXD1 RXD0 RX_CLK RX_DV TX_ER RX_ER 3V3 COL CRS MDC MDIO MDINTR 3V3
RX+
3 RD+ 5 CT
RX+
0R 0R 0R 0R
4
L3 742792093 VCCA R53 49R9 1% R54 49R9 1% C102 100NF
6 RD-
RX-
1 2
VCCA
75
75
7 NC
1nF
75
4 5
9 5 6 46 47
R58 6,80K 1%
75
7 8
3V3 GND_ETH
J00-0061NL
8 7 6 5
41 30 23 15 33 44
R62 0R NRST
10 40
48 31 11 12 13 14 45
3V3
1 2 3 4
B A INIT EDIT
REV
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
MODIF.
DATE
SHEET
AT91SAM9260-EK
ETHERNET
SCALE
1/1
1
6 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5V F1 500 mA F2 500 mA
C103 100NF
MN12 1 C1+
3V3 VCC
16 15 2
J16
CCUSBA-32002-30X
3V3
B1 B2 B3 B4
D
A B
A1 A2 A3 A4
3 C14 C2+
GND V+
5 C211 10 12 9
T
V-
6 14
RXD TXD
4 3
2 1
0R 0R
T R
7 13
C108 100NF
1 6 2 7 3 8 4 9 5
10
RXD RTS TXD CTS
R ADM3202ARN
J17 3V3
3V3
C114 100NF
16 15 2
C115 100NF
3 C14 C2+
GND V+
R79 100K
5 C2R82 0R USBCNX TXD1 R85 RTS1 R86 RXD1 R88 0R CTS1 0R 0R R83 0R
VT
6 14 7 13
11 10 12 9
R84 22K
T R
1 6 2 7 3 8 4 9 5
11
R75 0R
10
R ADM3202ARN MN14 3V3 R92 100K C127 100NF C121 100NF 3V3 VCC
8
J18
1 4 6 5
2 3
28
C1+
26 25 27
C122 100NF
24 1
GND C1C2+ V+
R93 100K
2 14 13 12 21 20
C2T1IN T
VT1OUT
3 9 10 11
0R 0R 0R
T2IN T T3IN T R
T2OUT
1 6 2 7 3 8 4 9 5
B
R96 DTR0
T3OUT
10
R R1OUT R1IN R98 DCD0 R101 DSR0 R103 RXD0 R104 CTS0 R105 RI0 R106 0R 0R 0R 0R 0R 0R
J20
19 18 17 16 15 23
4 5 6 7 8 22
R2OUT
R2IN
R3IN
R4IN
R5IN
EN MAX3241E
SHDN
3V3
11
11
R107 100K
B A INIT EDIT
REV
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
MODIF.
DATE
SHEET
AT91SAM9260-EK
SERIAL INTERFACES
SCALE
1/1
1
7 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
J23 PA1 PA3 PA5 PA7 PA9 PA11 PA13 PA15 PA17 PA19 PA21 PA23 PA25 PA27 PA29 PA31 PA0 PA2 PA4 PA6 PA8 PA10 PA12 PA14 PA16 PA18 PA20 PA22 PA24 PA26 PA28 PA30 PB1 PB3 PB5 PB7 PB9 PB11 PB13 PB15 PB17 PB19 PB21 PB23 PB25 PB27 PB29 PB31 3V3
J26 PB0 PB2 PB4 PB6 PB8 PB10 PB12 PB14 PB16 PB18 PB20 PB22 PB24 PB26 PB28 PB30 3V3 AVDD AGND PC1 PC3 PC5 PC7 PC9 PC11 PC13 PC15 D17 D19 D21 D23 D25 D27 D29 D31 3V3
J24 PC0 PC2 PC4 PC6 PC8 PC10 PC12 PC14 D16 D18 D20 D22 D24 D26 D28 D30 3V3 VREFP A0 NBS0_A0 A1 NWR2_NBS2_A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D0 D1 D2 D5 D6 D7 D10 D11 D12 D15 D16 D17 D20 D21 D22 D25 D26 D27 D30 D31 A0 A3 A4 A5 A8 A9 A10 A13 A14 A15 A18 A19 A20 A23 A24 A25_CFRNW NCS2 NANDCS_NCS3 CFCS0_NCS4
0R 0R 0R 0R
2 4 2 4
7 5 7 5
3V3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
8 6 8 6
1 3 1 3
0R 0R 0R 0R
3V3
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
PC5 CFCE2 PC7 CFCS1_NCS5 PC9 NCS2 PC11 NCS6 PC13 NWAIT PC15
A24
1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40
PIO A
PIO B
C130 100NF
C
1V8
3V3
C133 100NF
PIO_CNTRL1 TWCK
0R
PB19 PA23 PB31 PB29 PB30 PB28 PB20 PB22 PB24 PB26 PB10 PB12
PIO_CNTRL2 TWD ISI_MCK ISI_VSYNC ISI_HSYNC ISI_PCK ISI_DATA[0] ISI_DATA[2] ISI_DATA[4] ISI_DATA[6] ISI_DATA[8] ISI_DATA[10]
NANDOE NANDWE
SPARE2
A1 B1 C1 A2 B2 C2 A3 B3 C3 A4 B4 C4 A5 B5 C5 A6 B6 C6 A7 B7 C7 A8 B8 C8 A9 B9 C9 A10 B10 C10 A11 B11 C11 A12 B12 C12 A13 B13 C13 A14 B14 C14 A15 B15 C15 A16 B16 C16 A17 B17 C17 A18 B18 C18 A19 B19 C19 A20 B20 C20
E10 A12 D10 A11 E11 A17 D11 A16 E12 A22 D12 A21
C
E13 D13 E14 D14 E15 D15 E16 NCS6 D16 NWAIT E17 CFCE1 D17 E18 D18 E19 PB30 D19 E20 D20
SPARE1 SPARE0
NRST
EBI CONNECTORS
NOT POPULATED
3V3
Z15 J31-1
USER INTERFACE
3V3
C134 47 uF 6V3
NOT POPULATED
PA30
BP3
PA31
JPG JPG
DES.
28/08/06 17/10/05
DATE
VER. REV.
DATE
SHEET
AT91SAM9260-EK
EXPANSION & UI
8 7 6 5 4 3 2
SCALE
1/1
1
8 8
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
Schematics
5-2
6234CATARM22-Mar-07
Section 6 Errata
6.1
The silkscreen is wrong. The markings for BB and 1V8 are inverted. The marking should be: ! On J10 pin 1 (square pin): BB. ! On J10 pin 3: 1V8.
6.2
The S2 footprint must never be shorted to select a JTAG mode, otherwise the chip can be damaged. By default, the JTAGSEL input pin integrates a pull-down resistor (ICE mode). To select the JTAG mode, connect the JTAGSEL input pin at VDDBU power.
6.3
In order to use the TWI in Fast Mode (up to 400 Kbits/s), the default 10 K resistors R44 and R45 should be replaced by smaller values (e.g., 2.2 K). Note that there is no need to change the pull-up resistors if the TWI is used in Standard Mode (up to 100 Kbits/s).
6.4
AT73C213 clocking
In the present schematics (block diagram p.10 and sheet 1/8, p.26), the MCLK and BCLK sources implementation does not guarantee a correct phase relation as specified in the AT73C213 datasheet. Problem Fix/Workaround: In his own design, the user must make sure the BCLK and MCLK clocks generation implements the timing specified in the AT73C213 datasheet.
6-1
6234CATARM22-Mar-07
Errata
6-2
6234CATARM22-Mar-07
7.1
Revision History
Table 7-1.
Document 6234A 6234B Comments First issue. New Figure 2-3, AT91SAM9260-EK Block Diagram. Inserted Section 3.14, PIO Usage. Added new schematics in Section 5. Added new Section 6, Errata. Added errata Section 6.3, TWI line pullups for Fast Mode operation. Added errata Section 6.4, AT73C213 clocking 3315 Change Request Ref.
6234C
4086 4227
7-1
6234CATARM22-Mar-07
Revision History
7-2
6234CATARM22-Mar-07
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Atmel Europe
Le Krebs 8, rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Asia
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ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
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