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Code No: RR410505 Set No.

1
IV B.Tech I Semester Supplementary Examinations, March 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. Implement the following gates with p-MOS transistors only and explain its working

(a) 2 Input AND gate.


(b) 4 Input NOR gate. [8+8]

2. Define different voltage parameters of digital IC and Explain their significance.[16]

3. Explain about different spice - parameters of MOS transistor and their significance.
[16]

4. Compute the high-to-low delay of a two-input static complementary NOR gate with
minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.


(b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ.
[8+8]

5. How cross-talk appears in ICs and explain how this cross-talk can be minimized in
ICs. [16]

6. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]

7. How would you translate a register - transfer structure into a legal two - phase
latched sequential machine? [16]

8. Explain about switch - level simulation and give rules for evaluating switch - level
simulation. [16]

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Code No: RR410505 Set No. 2
IV B.Tech I Semester Supplementary Examinations, March 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with p-MOS transistors only and explain its working

(a) 3 Input NAND gate.


(b) Inverter. [8+8]

2. An p-MOS transistor is operating in the triode region with the following parameters
µn Cox = 95 µ A/V 2 W/L ( ratio) = 90 V gs = −4V, Vtn = −1.1V, Vds = −2V .
Find its drain current & drain -Source resistance. [16]

3. Explain about different spice - parameters of MOS transistor and their significance.
[16]

4. Design a layout for CMOS 2-input NOR gate. [16]

5. Explain in detail the path - delay measurement of the combinational logic circuits.
[16]

6. Design a logic gate network for full adder

(a) Using Two-level logic


(b) Using multi-level logic [8+8]

7. Explain clearly the detailed routing phase of the floor planning of the chip with
few examples by considering all constraints. [16]

8. With suitable example explain any one of the partitioning algorithm [16]

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Code No: RR410505 Set No. 3
IV B.Tech I Semester Supplementary Examinations, March 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with CMOS Logic and explain its working

(a) 3 Input NAND gate.


(b) Inverter. [8+8]

2. What are the key advantages of ICs? And explain how these advantages of ICs
translate in to advantages at the system level. [16]

3. Design a stick diagram for two-input P-MOS NAND and NOR gates. [16]

4. Compute the high-to-low delay of a two-input static complementary NOR gate with
minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.


(b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ.
[8+8]

5. Explain with suitable example how to design the layout of a gate to maximize
performance and minimize area. [16]

6. Discuss clearly about the following system Design principles.

(a) Pipelining
(b) Data-paths [8+8]

7. Clearly explain about block placement and channel definition with respect to floor
planning of the chip. [16]

8. Explain about different types in the register file based data-path. [16]

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Code No: RR410505 Set No. 4
IV B.Tech I Semester Supplementary Examinations, March 2006
VLSI SYSTEMS DESIGN
( Common to Computer Science & Engineering, Computer Science &
Systems Engineering and Electronics & Computer Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
⋆⋆⋆⋆⋆

1. Implement the following gates with p-MOS transistors only and explain its working

(a) 3 Input NAND gate.


(b) Inverter. [8+8]

2. Name different IC fabrication technologies with suitable examples. [16]

3. Explain details about level-1 modeling of MOS transistor. [16]

4. Compute the high-to-low delay of a two-input static complementary NOR gate with
minimum-sized transistor driving these loads.

(a) An inverter with minimum-sized pull up and pull down.


(b) An inverter whose pull up and pull down are both of size W = 10λ L = 10λ.
[8+8]

5. How cross-talk appears in ICs and explain how this cross-talk can be minimized in
ICs. [16]

6. Draw the Architecture of PLA and explain how different logic functions can be
implemented using PLA. [16]

7. Explain about pad design procedure to design input and output pads. [16]

8. Clearly explain about the generic integrated circuit design flow. [16]

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