FLIP FLOPS

AIM: To develop the source code for flip flops by using VHDL/VERILOG and Obtained the simulation & synthesis , place and route and implement into FPGA. ALGORITHM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis report. Step5: Verify the output by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report.

SR FLIPFLOP: LOGIC DIAGRAM:

TRUTH TABLE:

Q(t) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1

S 0 1 0 1 0 1 0 1

Q(t+1) 0 0 1 X 1 0 1 X

VHDL SOURCE CODE: --Design --Description --Author --Reg no --Version Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity srff is Port ( s : in std_logic; r : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end srff; : SR-FLIP FLOP : To implement SR-FLIP FLOP : K.Srinivasan : 3082647 : Xilinx- 7.1i

architecture Behavioral of srff is begin process(s,r,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (s='0' and r='0') then q<=q; qbar<=qbar; elsif (s='0' and r='1') then q<='0'; qbar<='1'; elsif (s='1' and r='0') then q<='1'; qbar<='0'; else q<='X'; qbar<='X'; end if; end if; end process; end Behavioral; VERILOG SOURCE CODE: Behavioral Modeling: module srflipflop(s, r, clk, rst, q, qbar); input s; input r; input clk; input rst; output q; output qbar; reg q,qbar; always @ (posedge(clk) or posedge(rst)) begin if(rst==1'b1) begin q= 1'b0;qbar= 1'b1; end else if(s==1'b0 && r==1'b0) begin q=q; qbar=qbar; end else if(s==1'b0 && r==1'b1) begin q= 1'b0; qbar= 1'b1; end else if(s==1'b1 && r==1'b0) begin q= 1'b1; qbar= 1'b0; end else begin q=1'bx;qbar=1'bx;

end end endmodule

TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT srff PORT( s : IN std_logic; r : IN std_logic; clk : IN std_logic; rst : IN std_logic; q : INOUT std_logic; qbar : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL s : std_logic := '0'; SIGNAL r : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --BiDirs SIGNAL q : std_logic; SIGNAL qbar : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: srff PORT MAP( s => s, r => r, clk => clk, rst => rst, q => q, qbar => qbar ); tb : PROCESS BEGIN clk<='0'; wait for 50ps; clk<='1'; wait for 50ps; end process;

rst<='1','0' after 200ps; tb1:process begin s<= '1' , '0' after 400ps; r<= '1' , '0' after 300ps , '1' after 500ps; wait for 1ns; END PROCESS; END;

Simulation:

JK FLIPFLOP: LOGIC DIAGRAM: Q(t) 0 0 0 0 1 1 1 1 VHDL SOURCE CODE: --Design --Description --Author --Reg no --Version Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity jkff is : JK-FLIP FLOP : To implement JK-FLIP FLOP : K.Srinivasan : 3082647 : Xilinx- 7.1i J 0 0 1 1 0 0 1 1

TRUTH TABLE: K 0 1 0 1 0 1 0 1 Q(t+1) 0 0 1 1 1 0 1 0

Port ( j : in std_logic; k : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end jkff; architecture Behavioral of jkff is begin process(j,k,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (j='0' and k='0') then q<=q; qbar<=qbar; elsif (j='0' and k='1') then q<='0'; qbar<='1'; elsif (j='1' and k='0') then q<='1'; qbar<='0'; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral;

VERILOG SOURCE CODE: Behavioral Modeling: module jkff(j, k, clk, rst, q, qbar); input j; input k; input clk; input rst; output q; output qbar; reg q; reg qbar; always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin q=1'b0; qbar=1'b1; end else if (j==1'b0 && k==1'b0) begin q=q; qbar=qbar;

end else if (j==1'b0 && k==1'b1) begin q=1'b0; qbar=1'b1; end else if (j==1'b1 && k==1'b0) begin q=1'b1; qbar=1'b0; end else begin q=~q; qbar=~qbar; end end endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT jkff PORT( j : IN std_logic; k : IN std_logic; clk : IN std_logic; rst : IN std_logic; q : INOUT std_logic; qbar : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL j : std_logic := '0'; SIGNAL k : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --BiDirs SIGNAL q : std_logic; SIGNAL qbar : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT)

uut: jkff PORT MAP( j => j, k => k, clk => clk, rst => rst, q => q, qbar => qbar ); tb : PROCESS BEGIN clk<='0'; wait for 50ps; clk<='1'; wait for 50ps; end process; rst<='1','0' after 200ps; tb1:process begin j<= '1' , '0' after 400ps; k<= '1' , '0' after 300ps , '1' after 500ps; wait for 1ns; END PROCESS; END;

Simulation output:

D FLIPFLOP: LOGIC DIAGRAM:

TRUTH TABLE: Q(t) 0 0 1 1 D 0 1 0 1 Q(t+1) 0 1 0 1

VHDL SOURCE CODE: --Design --Description --Author --Reg no --Version Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dff is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end dff; architecture Behavioral of dff is begin process(d,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (d='0') then q<='0'; qbar<='1'; else q<='1'; qbar<='0'; end if; end if; end process; end Behavioral; VERILOG SOURCE CODE: Behavioral Modeling: : D-FLIP FLOP : To implement D-FLIP FLOP : K.Srinivasan : 3082647 : Xilinx- 7.1i

module dff(d, clk, rst, q, qbar); input d; input clk; input rst; output q; output qbar; reg q; reg qbar; always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin q=1'b0; qbar=1'b1; end else if (d==1'b0) begin q=1'b0; qbar=1'b1; end else begin q=1'b1; qbar=1'b0; end end endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT dff PORT( d : IN std_logic; clk : IN std_logic; rst : IN std_logic; q : INOUT std_logic; qbar : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL d : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --BiDirs SIGNAL q : std_logic; SIGNAL qbar : std_logic;

BEGIN -- Instantiate the Unit Under Test (UUT) uut: dff PORT MAP( d => d, clk => clk, rst => rst, q => q, qbar => qbar ); tb : PROCESS BEGIN clk<='0'; wait for 50ps; clk<='1'; wait for 50ps; end process; rst<='1','0' after 200ps; tb1:process begin d<= '1' , '0' after 400ps; wait for 1ns; END PROCESS; END;

Simulation Output:

T FLIPFLOP: LOGIC DIAGRAM: Q(t) 0 0 1 1 VHDL SOURCE CODE: --Design : T-FLIP FLOP --Description : To implement T-FLIP FLOP --Author : K.Srinivasan --Reg no : 3082647 --Version : Xilinx- 7.1i Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tff is Port ( t : in std_logic; clk : in std_logic; rst : in std_logic; q : inout std_logic; qbar : inout std_logic); end tff; architecture Behavioral of tff is begin process(t,clk,rst,q,qbar) begin if (rst='1') then q<='0'; qbar<='1'; elsif (clk='1' and clk'event) then if (t='0') then q<=q; qbar<=qbar; else q<=not q; qbar<=not qbar; end if; end if; end process; end Behavioral; VERILOG SOURCE CODE: Behavioral Modeling: module tff(t, clk, rst, q, qbar);

TRUTH TABLE: T 0 1 0 1 Q(t+1) 0 1 1 0

input t; input clk; input rst; output q; output qbar; reg q,qbar; always @ (posedge(clk) or posedge(rst)) begin if(rst==1'b1) begin q= 1'b0;qbar= 1'b1; end else if (t==1'b0) begin q=q; qbar=qbar; end else begin q=~q; qbar=~qbar; end end endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT tff PORT( t : IN std_logic; clk : IN std_logic; rst : IN std_logic; q : INOUT std_logic; qbar : INOUT std_logic ); END COMPONENT; --Inputs SIGNAL t : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --BiDirs SIGNAL q : std_logic; SIGNAL qbar : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT)

uut: tff PORT MAP( t => t, clk => clk, rst => rst, q => q, qbar => qbar ); tb : PROCESS BEGIN clk<='0'; wait for 50ps; clk<='1'; wait for 50ps; end process; rst<='1','0' after 200ps; tb1:process begin t<= '1','0' after 400ps; wait for 1ns; END PROCESS; END;

Simulation output:

EXP NO: 02

DATE: 12-04-09

MULTIPLIER AND ACCUMLATOR UNIT

AIM To develop the source code for MAC unit by using VHDL/VEILOG and obtain the simulation. ALGORITHM Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis report. Step5: Verify the output by simulating the source code. Step6: Write all the possible combinations of input using test bench. BLOCK DIAGRAM:

VERILOG SOURCE CODE: Behavioral Modeling: module mac(a, b, clk, rst, acc); input [7:0] a; input [7:0] b; input clk; input rst; output [15:0] acc; reg [15:0] acc; reg [15:0] pd; reg [15:0] adder;

always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin adder=8'b00000000; end else begin pd=a*b; adder=adder+pd; end acc=adder; end endmodule

EXP NO: 10 09

DATE: 21-03-

ARITHMETIC AND LOGIC UNIT

AIM: To develop the source code for arithmetic and logic unit by using VHDL/VERILOG and obtain the simulation & synthesis.

ALGORITM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis report. Step5: Verify the output by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. LOGIC DIAGRAM:

TRUTH TABLE:

VHDL SOUCE CODE library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity alu is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; s : in std_logic_vector(3 downto 0); y : out std_logic_vector(7 downto 0)); end alu; architecture structural of alu is component arith port(a,b:in std_logic_vector(7 downto 0); c:in std_logic; s:in std_logic_vector(2 downto 0); x:out std_logic_vector(7 downto 0)); end component; component logic port(a,b:in std_logic_vector(7 downto 0); s:in std_logic_vector(2 downto 0); x:out std_logic_vector(7 downto 0)); end component; component mux1 port(a,b:in std_logic_vector(7 downto 0); s:in std_logic; x:out std_logic_vector(7 downto 0)); end component; signal x1,x2:std_logic_vector(7 downto 0); begin a1:arith port map (a(7 downto 0),b(7 downto 0),c,s(2 downto 0),x1(7 downto 0)); l1:logic port map (a(7 downto 0),b(7 downto 0),s(2 downto 0),x2(7 downto 0)); m1:mux1 port map (x1(7 downto 0),x2(7 downto 0),s(3),y(7 downto 0)); end structural; arith component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity arith is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); c : in std_logic; s : in std_logic_vector(2 downto 0); x : out std_logic_vector(7 downto 0)); end arith; architecture Behavioral of arith is begin process(a,b,c,s) begin case s is when "000" => x <= a; when "001" => x <= a+1; when "010" => x <= a-1; when "011" => x <= b; when "100" => x <= b+1; when "101" => x <= b-1;

when "110" => x <= a+b; when others => x <= a+b+c; end case; end process; end Behavioral; logic component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity logic is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); s : in std_logic_vector(2 downto 0); x : out std_logic_vector(7 downto 0)); end logic; architecture Behavioral of logic is begin process(a,b,s) begin case s is when "000" => x <= not a; when "001" => x <= not b; when "010" => x <= a and b; when "011" => x <= a nand b; when "100" => x <= a or b; when "101" => x <= a nor b; when "110" => x <= a xor b; when others => x <= a xnor b; end case; end process; end Behavioral; mux1 component source code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux1 is Port ( a : in std_logic_vector(7 downto 0); b : in std_logic_vector(7 downto 0); s : in std_logic; x : out std_logic_vector(7 downto 0)); end mux1; architecture Behavioral of mux1 is begin process(a,b,s) begin if (s='0') then x<=a; else x<=b; end if;

end process; end Behavioral;

VERILOG SOURCE CODE: Behavioral Modeling: module alu(a, b, cin, s, y); input [7:0] a; input [7:0] b; input cin; input [3:0] s; output [7:0] y; reg [7:0]y; always @ (a or b or s) begin case(s) 4'b0000: y=a; 4'b0001: y=a+1; 4'b0010: y=a-1; 4'b0011: y=b; 4'b0100: y=b+1; 4'b0101: y=b-1; 4'b0110: y=a+b; 4'b0111: y=a+b+cin; 4'b1000: y=~a; 4'b1001: y=~b; 4'b1010: y=a&b; 4'b1011: y=a|b; 4'b1100: y=~(a&b); 4'b1101: y=~(a|b); 4'b1110: y=a^b; 4'b1111: y=~(a^b); endcase end endmodule

Simulation output:

SHIFT REGISTERS
AIM: To develop the source code for shifters unit by using VHDL/VERILOG and obtain the simulation & synthesis. ALGORITM: Step1: Define the specifications and initialize the design. Step2: Declare the name of the entity and architecture by using VHDL source code. Step3: Write the source code in VERILOG. Step4: Check the syntax and debug the errors if found, obtain the synthesis report. Step5: Verify the output by simulating the source code. Step6: Write all possible combinations of input using the test bench. Step7: Obtain the place and route report. SERIAL-IN SERIAL-OUT SHIFT REGISTER: LOGIC DIAGRAM :

VHDL SOURCE CODE: --Design --Description --Author --Reg no --Version Behavioral Modeling: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity siso is Port ( d : in std_logic; clk : in std_logic; rst : in std_logic; q : out std_logic); end siso; architecture Behavioral of siso is signal x:std_logic_vector(7 downto 0); begin process(d,clk,rst) begin if (rst='1') then q<='X'; elsif (clk='1' and clk'event) then x(0)<=d; x(1)<=x(0); x(2)<=x(1); x(3)<=x(2); x(4)<=x(3); x(5)<=x(4); x(6)<=x(5); x(7)<=x(6); q<=x(7); end if; end process; end Behavioral; VERILOG SOURCE CODE: Behavioral Modeling: module siso(din, clk, rst, dout); input din; input clk; : SISO SHIFT REGISTER : To implement SISO SHIFT REGISTER : K.Srinivasan : 3082647 : Xilinx- 7.1i

input rst; output dout; reg dout; reg [7:0]x; always @ (posedge(clk) or posedge(rst)) begin if (rst==1'b1) begin dout=8'hzz; end else begin x={x[6:0],din}; dout=x[7]; end end endmodule TEST BENCH(VHDL): LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY test_vhd IS END test_vhd; ARCHITECTURE behavior OF test_vhd IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT siso PORT( d : IN std_logic; clk : IN std_logic; rst : IN std_logic; q : OUT std_logic ); END COMPONENT; --Inputs SIGNAL d : std_logic := '0'; SIGNAL clk : std_logic := '0'; SIGNAL rst : std_logic := '0'; --Outputs SIGNAL q : std_logic; BEGIN -- Instantiate the Unit Under Test (UUT) uut: siso PORT MAP( d => d, clk => clk, rst => rst, q => q );

tb : PROCESS BEGIN clk<='1'; wait for 50ps; clk<='0'; wait for 50ps; END PROCESS; rst<='1','0' after 200ps; d<='1','0' after 1 ns; END;

Simulation output