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Modular Simulation of NOC-WK-recursive: New On-Chip Interconnect Architecture

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

Abstract Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip which supports high degree of scalability and reusability. NoC, specific parameters such as hardware architecture, topology, switching methods have a huge impact on performance and the cost of the NoCs. Since the ability of the network to be efficiently, disseminate information depends largely on the topology, we especially focus on simulation of the wk-recursive topology for NoC in different Sizes and dimensions for NoC. We simulate this topology for general-purpose parallel processing applications. This paper shows that a novel network called the NOC-WK-recursive is universally efficient when adequate capacity distribution is provided and is suitable for use as an interconnection network in parallel computers. The NOC-WK-recursive resembles the fat-tree and the fat-pyramid in hardware structure, but it has its unique strengths. Index Terms Network on Chip (NoC), NOC-WK-recursive, hyper-mesh, hyper-tree, Fat-tree, Fat-pyramid, Fat-stack, augmented fat-stack (AFS).

1 INTRODUCTION
Networks-on-Chip (NoC) have been proposed as a promising solution to multi-processor on-chip communication problems. To catalyze the deployment of the NoC paradigm for many high performance computational applications, many challenging research problems of NoC design abstractions need to be addressed at all levels. The active problems in the field of NoC design include: design space exploration of NoC architecture for applications, application scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application, and optimization of communication cost, area, and power.[1] The design of the NoC system is divided into four procedural levels of abstraction, or models: i) the Application model, which includes traffic generation and monitoring; ii) the NoC framework architecture model and its components; iii) the Communication Flow model, which models communication among different NoC components; iv) Algorithm models, which model switching and routing algorithms in the NoC architecture. The Application model encompasses three main components: i) application mapping and scheduling, ii) a traffic controller iii) a monitor. The NoC framework Architecture model includes: i) the NoC Framework, which includes such

processing elements (PEs) as OR1K processors, TIMERs, UARTs, Instruction (IMEM) and data memories (DMEM), and a Network Adapter; ii) the router iii) network topology. The Communication Flow model defines the control and data flow in the NoC at the system level, the network level, and the data link level. The system level defines the flow between master to slave PEs, slave to master PEs and between master PEs. The control flow within the router is defined in network layer. The lowest level is the data link level. This level deals with encoding, decoding, and synchronizing packets or flits. The Algorithmic model defines the various switching and routing algorithms used in data and control flow. Latency and power consumption overheads of the NoC system are determined by the communication architecture (router design and topology) and the algorithmic model that is adopted.[1] processors may contain hundreds of execution units [3]. In addition to the main processors, these chips often integrate cache memories, specialized accelerators, memory controllers, and other resources. Likewise, modern systems-on-a-chip (SOCs) contain many cores, accelerators, memory channels, and interfaces. As the degree of integration increases with each technology generation, chips containing over a thousand discrete execution and storage resources will be likely in the near future. Chip-level multiprocessors (CMPs) require an efficient communication infrastructure for operand, memory, coherence, and

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control transport [4, 5, 6], motivating researchers to propose structured on-chip networks as replacements to buses and ad-hoc wiring solutions of single-core chips [7].

2 NOC FRAMEWORK
The NoC framework/system consists of five main modules: i) The processing architecture ii) the communication infrastructure iii) the communication paradigm iv) the monitor module v) the traffic generator module. The NoC processing architecture consists of several master/slave processing elements (PEs) that are connected to the communication infrastructure by means of a network adapter. The PEs can be a master PE or slave PE, depending on whether it can initiate a message transfer or only respond to a request. Only master PEs can initiate a message transfer. Slave PEs respond to the requests from master PE either by sending back the requested signals/data or by saving the received information. UART, TIMER, and Instruction/Data Memory all are considered slave PEs, whereas the master PEs used in the design are capable of performing arithmetic and logical operations. The network adapter receives signals from the PEs and generates packets to be sent to the communication infrastructure. Hence, the main function of the adapter module is to transform the data to and from the format required by underlying infrastructure. The data/message is communicated as packets. The entire message can be either generated as a single packet or the packets can be divided into flits before actually transmitted. The packet format is shown in Figure 1.

Fig.2. Fat-tree topology

3.2 Fat-Pyramid The fat-pyramid network is a good candidate as the basis for a general-purpose parallel computer, because it can efficiently simulate any network of comparable area under general conditions. The basic structure of the fatpyramid network was suggested by Charles Leiserson and Tom Cormen and is related to the fat-tree introduced by Leiserson [2].

Fig.1. Packet Format

3 SYSTEM ARCHITECTURE
Network topology determines the connectivity among nodes and is therefore a first-order determinant of network performance and energy-efficiency. Since the ability of the network to efficiently disseminate information depends largely on the topology, we especially focus on different types of Topologies:

Fig.3. Quaternary Tree and its Pyramid

3.1 fat-tree (hyper-tree) Fattrees are a particular type of a set of topologies known as multistage interconnection networks (MIN). In MINs, switches are deployed in a set of stages. Each switch can only be connected to switches belonging to their previous or to their next stage. In bidirectional MINs, cores are attached to the switches of the lowest stage. (see Figure 2).

3.3 Fat-Stack The choice of the term "fat-stack" stems from the observation that the network is a construct of identical atomic sub-network units stacked up and tapering upwards. The fat-stack is relatively simple in structure, which makes it scalable to closely represent a distributed network. [3]

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Fig.4. Topology of an augmented fat-stack (AFS)

4 WK-RECURSIVE NETWORK
4.1. Why WK-recursive network? In massively parallel MIMD systems, the topology plays a crucial role in issues such as communication performance, hardware cost, potentialities for efficient applications and fault tolerant capabilities [4]. A topology named WK-Recursive network has been proposed [5]. The topology has many attractive properties, such as high degree of regularity, symmetry and efficient communication. Particularly, for any specified number of degree, it can be expanded to an arbitrary size level without reconfiguring the edges. WK-Recursive networks have received considerable attention. Researchers have devoted themselves to various issues of WK-Recursive networks such as broadcasting algorithms [6], topological properties [7] and communication [8]. 4.2. WK-recursive structure WK-recursive network is a regular scalable network topology which can be expanded to any size very easily. Initially WK-recursive network was proposed as a network for VLSI implementation [5]. Such topology can offer high degree of regularity, scalability and symmetry. So WK-recursive network is also used to design NoC by some researchers [9] [10]. Researches in [9] [10] clearly show that the WK-recursive network is most suitable for NoC architectures. The cores can be clustered according to the particular WK-recursive network structure and then map onto NoC to speed up the cores mapping process. The network structure under consideration is the NoC architectures based on WK-recursive network. The WKrecursive network can be built hierarchically by combining basic modules. Any complete k-graph can act as the basic module. For readers convenience, we use WK(k,h) to represent a WK-recursive network of level h whose basic modules are some complete k-graph in this paper,

where k>1 and h 1. The WK-recursive networks can be clearly identified by the following formulation [7]: h = log KN Where N is the total number of nodes. We define WK(k,h) formally as follows similar to definitions in [7] [11]. Definition 1. The node set of WK(k,h) network is denoted by {ahah-1a2a1|ai [0,k-1] for 1i h}. Node ahah-1a2a1 is adjacent to ahah-1a2b where 0bk-1 and ba1. The edges between node ahah-1a2a1 and ahah-1a2b are named substituting edges. Node ahah-1a2a1 is adjacent to ahah-1 ai+1ai-1(ai)i-1 if aiai-1 and ai-1=ai-2==a2=a1, where (ai)i-1 represents i-1 consecutive ai's. The edges between node ahah-1a2a1 and ahah-1ai+1aii-1 are named flipping edges and assigned label i-1 [7]. 1(ai) Definition 2. Node ahah-1a2a1 is an i-frontier, where 1i<h, if ai==a2=a1[7]. We note that two nodes connected by an i-flipping edge are i-frontiers. And a node is an i-frontier, it is also a j-frontier for 1j<i. An embedded WK(k,t) network in WK(k,h) contains k-1 t-frontier. Definition 3. For any two nodes S and T in WK(k,h) network, it defines S=iT if they belong to the same WK(k,i) network in WK(k,h), otherwise SiT if they belong to two different WK(k,i) networks in WK(k,h) [11]. With these definitions the minimal routing algorithm can be described clearly in detail. A minimal routing path between any two nodes S and T in WK(k,h) can be built as follows [11].

Fig.5. The structures of (a) WK(4, 0), (b) WK(4, 1) , (c) WK(4, 2) ,

and (d) WK(4, 3)

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A WK-Recursive network with amplitude W and level L, denoted by a WK(W,L), can be recursively constructed. A WK(W,0) is a vertex with W free edges. A WK(W,1) is a W-vertex complete graph that is denoted by a KW. Each vertex has one free edge and W-1 edges that are used for connecting to the other vertices. Clearly, a WK(W,1) has W vertices and W free edges. A WK(W,H) consists of W copies of WK(W,H-1) as super vertices and the W super vertices are connected as a KW, where 2HL. By induction, it is easy to see that a WK(W,L) has WL vertices and W free edges. Consequently, for any specified number of degree W, WK-Recursive networks can be expanded to an arbitrary level L without reconfiguring the edges. The outline graph of WK(4,3) and comparison between WK(4,3) and WK(4,2) is shown in Figure 5.

5. NOC-WK-RECURSIVE TOPOLOGY
In [5], a VLSI implementation of the WK-recursive networks is described, and a routing algorithm is developed. This algorithm defines the physical channels which must be traversed, but does not address the use of virtual channels. The NoC framework with WK-recursive topology is shown in Figure 7.

4.3. Addressing scheme for a WK(W,L) In Fig. 6, the structures of a WK(4,0), a WK(4,1), a WK(4,2) and a WK(4,3) are illustrated. The following addressing scheme for a WK(W,L) is described in [12]. After fixing an origin and an orientation (clockwise or counterclockwise), for each WK(W,1) subnetwork, every vertex is labeled with an index digit d1{0,1, ... ,W-1}. Likewise, for each WK(W,H) subnetwork, every WK(W,H-1) sub-network is labeled with an index dH{0,1, ... ,W-1}, where 2HL.

Fig.7. NoC Framework with WK Topology.

6. RELATED WORK
To the best of our knowledge, no related work has been proposed on the problem of mapping on the WKrecursive network based NoC architectures. The grid-pyramid networks were first introduced in [13] as a generalized pyramid topology. Various topological properties of these networks were studied in [13]. The Pyramid network is a desirable network topology used as both software data-structure and hardware architecture. Contrary to the conventional pyramid network in which the nodes in each level form a mesh, the connections between these nodes may also be according to other gridbased topologies such as the torus, hyper-mesh or WKrecursive. Such pyramid networks form a wide class of interconnection networks that possess rich topological properties [14]. The ability of the network to efficiently disseminate information depends largely on the topology. Also, application mapping and routing protocol are dependent mainly on the topology. Linear, Mesh, and Torus [15] are the most widely used homogenous topologies; however, Spidergon [16] and WK-recursive topologies [5,10] are gaining greater importance.

7. SIMULATION METHODOLOGY
Fig.6. The structures of (a) WK(4,0), (b) WK(4,1), (c) WK(4,2)

and (d) WK(4,3).

In this section, simulation of Wk-recursive on-chip interconnects is done by using a simulator developed in [17]. This discrete event driven simulator is based on ns2 [18] that provides many facilities to describe network topology, transmission protocols, routing algorithms, and traf-

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fics generation. The main objective of using ns2 is to rapidly explore and evaluate the performance metrics as well as the energy consumption of on-chip interconnects.

8.1. NOC-WK-recursive (4,2)

7.1. Simulation Details The top most shared component in simulation is the NoC node, in which PE (Processing Element) and router are the main components. The PE is a module that injects/ejects the generated/receiving packets based on a traffic model like uniform, hotspot, etc. Routers receive packets on their input channels and after routing a packet based on the routing algorithm and destination address, the packet is sent to the selected output channel. When a specific topology like mesh or WK-recursive is supposed to be modeled by such components, a top-level wrapper module is implemented that connects several nodes of this type to each other based on the structure of the specified topology. Ns-2 [19] is a discrete event network simulator designed for simulation of ordinary networks of computers. As many models of network components are provided, the user can simulate at a high abstraction level. Yet, it is possible to implement new components in the network model. ns-2 has support for local area networks, mobile networks and even satellite networks. Two computer languages are used in ns-2, namely C++ and OTcl. All of the topology parameters can be described as a script file; in Tcl. A part of the ns-2 script file about constructing the topology is shown below: #=-----------ReSources--------------= for {set k 1} {$k <= $n} {incr k} { set x 1 ; for {set kt 1} {$kt < $k} {incr kt} { set x [expr ($x*2)] } set z 1 ; for {set kt 1} {$kt < $k} {incr kt} { set z [expr ($z*10)] } for {set i 1} {$i <= $x} {incr i} { for {set j 1} {$j <= $x} {incr j} { set Res([expr ($k*$z+$i*$x+$j)]) [$ns node] $Res([expr ($k*$z+$i*$x+$j)]) label Res[expr ($k*$z+$i*$x+$j)] $Res([expr ($k*$z+$i*$x+$j)]) shape square
#Create links (switches-Resources) $ns duplex-link $sw([expr ($k*$z+$i*$x+$j)]) $Res([expr ($k*$z+$i*$x+$j)]) 1Mb 10ms DropTail }}}

(a)

(b)

8. SIMULATION RESULTS
In this section, we present the Simulation of NoC with different levels with the topology NOC-WK-recursive and we survey the ability and flexibility of ns2 in NOCWK-recursive (network-on-chip-WK-recursive) simulations. Figures 8 to 10, show different views of NOC-WKrecursive.

(c)
Fig.8. NOC-WK-recursive (4,2)

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8.2. NOC-WK-recursive (4,3)

(c) Fig.9. NOC-WK-recursive (4,3) (a)

8.3. NOC-WK-recursive (4,4)

(b)

(a)

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(b) Fig.10. NOC-WK-recursive (4,4)

9. SIMULATION METHODOLOGY
Mapping an application, which is described by a parameterized task graph, on to NoC is a key research problem in NoC design. Mesh topology has been used in a variety of interconnection network applications especially for NoC design. However, the WK-recursive network has not been studied yet as the underlying topology for NoCs. In this paper, we show how to simulate a new topology (WK-recursive) for network on chip. Our next objective is to develop different network topologies for NoCs and validating them under different working conditions.

REFERENCES
[1] J. Suseela, V. Muthukumar, "Performance Analysis of WK-Recursive and Torus Routing", In Proceedings of the International Conference on Embedded Systems and Applications. July 2011. [2] C. E. Leiserson. "Fat-trees: Universal networks for hardware-efficient supercomputing", IEEE Trans.Computers, C-34(10):892{901, Oct. 1985. [3] Kevin F. Chen, Edwin Hsing-Mean Sha, Bin Xiao, "Universal Routing in Distributed Networks", In 11th International Conference on Parallel and Distributed Systems (ICPADS 2005), Fuduoka, Japan, pp. 555-559, IEEE Computer Society, July 2005. [4] F.T. Leighton, "Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes, Mogran Kaufmann", California, 1992. [5] G. D. Vecchia and C. Sanges, A Recursively Scalable Network VLSI Implementation, Future Generation Computing Systems, 1988, 4(3), pp. 235-243.

[6] G.D. Vecchia, C. Sanges, "An optimal broadcasting technique for WK-Recursive topologies", Future Generat. Comput. Syst. 5 (4) (1989/90) 353357. [7] A.I. Mahdaly, H.T. Mouftah, N.N. Hanna, Topological properties of WK-recursive networks, Distributed Computing Systems, pp.374 380, 1990. [8] J.F. Fang, G.J. Lai, Y.C. Liu, S.T. Fang. "A novel broadcasting scheme for WK-recursive networks", in: Proceedings of the 2003 IEEE Pacic Rim Conference on Communications, Computers and signal Processing, 2, 2003, pp. 10281031. [9] S. Suboh, M. Bakhouya, and T. El-Ghazawi, Simulation and Evaluation of On-Chip Interconnect Architectures: 2D mesh, Spidergon, and WK-recursive network, NOCS, Pages 205-206, 2008. [10] D. Rahmati, A. E. Kiasari, S. Hessabi, H. SarbaziAzad, A Performance and Power Analysis of WKRecursive and Mesh Networks for Network-onChips, Computer Design, 2006. ICCD 2006. International Conference on Oct. 2007, pp 142 147. [11] R. V. Boppana and S. Chalasani, A framework for designing deadlock-free wormhole routing algorithms, IEEE Transactions on Parallel and Distributed Systems (TPDS), 7(2): 169-183, 1996. [12] G.D. Vecchia, C. Sanges, "Recursively scalable network for message passing architecture", in: Proceeding of the International Conference Parallel Processing and Applications, 1, 1987, pp. 3340. [13] M. HoseinyFarahabady, H. Sarbazi-Azad, The gridpyramid: A generalized pyramid network, Journal of Supercomputing, Vol. 37, pp. 23-45, 2006. [14] S. Bakhshi, M. Bakhshi, and H. Sarbazi-Azad, "Efficient VLSI Layout of Grid Pyramid Networks", 1st International Conference on Contemporary Computing (ICCC 2008), India, New Delhi, 7-9 August, 2008. [15] J. Duato, et. al. Interconnection Networks: An Engineering Approach. Morgan Kaufmann, 2002 .. [16] Mahmoud Moadeli, Ali Shahrabi, Wim Vanderbauwhede, Mohamed Ould-Khaoua. An Analytical Performance Model for the Spidergon NOC, Advanced Information Networking and Applications, 2007. AINA '07. 21st International Conference, May 2007, pp 1014 1021 [17] Y. R. Sun, S. Kumar, and A. Jantsch, "Simulation and Evaluation of a Network On Chip Architecture Using ns2", Proc. The IEEE NorChip Conference, 2002. [18] NS, Network Simulator, NS2, http://www.isi.edu/nsnam/ns, accessed June 2008. [19] Breslau L., Estrin D., Fall K., S. Floyd, J. Heidemann, A. Helmy, P. Huang, S. McCanne, K. Varadhan, Ya Xu, and Haobo Yu. "Advances in network simulation", IEEE Computer, 33(5):59{ 67, May 2000.

Reza Kourdy received his B.Sc. degree in Computer Engineering and his M.Sc. degree in Computer Architecture both from Azad University of Arak, Iran, in 2002 and 2007, respectively. His research interests include Network-OnChip Architecture and Fault-tolerance.

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Mohammad Reza Nouri Rad received his B.Sc. Degree in Computer Engineering Software from Azad University of Najafabad, Iran, in 2001, and his M.Sc. Degree in Computer Software from Azad University of Arak, Iran, in 2010. His research interests include NetworkOn-Chip Architecture and Network Security. He is Program Committee of following conferences : WICT 2011 CSNT 2011 CICN 2011 SocProS 2011 CSNT 2012 CICN 2012 BIC-TA 2012