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1. GENERAL DESCRIPTION
1.1 MT1389D
The MT1389D Progressive Scan DVD-Player Combo Chip is a single-chip MPEG video decoding chip that integrates audio/video stream data processing, TV encoder, four video DACs with Macrovision. copy protection, DVD system navigation, system control and housekeeping functions. The features of this chip can be listed as follows: General Features: Progressive scan DVD-player combo chip Integrated NTSC/PAL encoder. Built-in progressive video output DVD-Video, VCD 1.1, 2.0, and SVCD Unified track buffer and A/V decoding buffer. Direct interface of 32-bit SDRAM. Servo controller and data channel processing.
Video Related Features: Macrovision 7.1 for NTSC/PAL interlaced video. Simultaneous composite video and S-video outputs, or composite and YUV outputs, or composite and RGB outputs. 8-bit CCIR 601 YUV 4:2:2 output. Decodes MPEG video and MPEG2 main profile at main level. Maximum input bit rate of 15Mbits/sec
Audio Related Features: Dolby Digital (AC-3) and Dolby Pro Logic. Dolby Digital S/PDIF digital audio output. High-Definition Compatible Digital. (HDCD) decoding. Dolby Digital Class A and HDCD certified. CD-DA. MP3.
1.2 MEMORY
1.2.1 SDRAM Memory Interface The MT1389D provides a glueless 16-bit interface to DRAM memory devices used as OSD, MPEG stream and video buffer memory for a DVD player. The maximum amount of memory supported is 16 MB of Synchronous DRAM (SDRAM). The memory interface is configurable in depth to support 110-Mb addressing. The memory interface controls access to both external SDRAM memories, which can be the sole unified external read/write memory acting as program and data memory as well as various decoding and display buffers.
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2.1 SYSTEM BLOCK DIAGRAM A sample system block diagram for the MT1389D DVD player board design is shown in the following figure:
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3. AUDIO OUTPUT
The MT1389D supports two-channel and six-channel analog audio output. In a system configuration with six analog outputs, the front left and right channels can be configured to provide the stereo (2 channel) outputs and Dolby Surround, or the left and right front channels for a 5.1 channel surround system. The MT1389D also provides digital output in S/PDIF format. The board supports both optical and coaxial SPDIF outputs.
4. AUDIO DACS
The MT1389D supports several variations of an I S type bus, varying the order of the data bits (leading or no leading zero bit, left or right alignment within frame, and MSB or LSB first) is 2 possible using the MT1389D internal configuration registers. The I S format uses four stereo data 2 lines and three clock lines. The I S data and clock lines can be connected directly to one or more audio DAC to generate analog audio output. The two-channel DAC is internal. The six channel DAC is PCM1606. The outputs of the DACs are not differential. The buffer circuits use National LM833 op-amps to perform the low-pass filtering and the buffering.
5 .VIDEO INTERFACE
5.1 Video Display Output The video output section controls the transfer of video frames stored in memory to the internal TV encoder of the MT1389D. The output section consists of a programmable CRT controller capable of operating either in Master or Slave mode. The video output section features internal line buffers which allow the outgoing luminance and chrominance data to match the internal clock rates with external pixel clock rates, easily facilitating YUV4: 2:2 to YUV4: 2:0 component and sample conversion. A polyphase filter achieves arbitrary horizontal decimation and interpolation. Video Bus The video bus has 8 YUV data pins that transfer luminance and chrominance (YUV) pixels in CCIR601 pixel format (4:2:2). In this format, there are half as many chrominance (U or V) pixels per line as luminance (Y) pixels; there are as many chrominance lines as luminance. Video Post-Processing The MT1389D video post-processing circuitry provides support for the color conversion, scaling, and filtering functions through a combination of special hardware and software. Horizontal upsampling and filtering is done with a programmable, 7-tap polyphase filter bank for accurate non-integer interpolations. Vertical scaling is achieved by repeating and dropping lines in accordance with the applicable scaling ratio. Video Timing The video bus can be clocked either by double pixel clock and clock qualifier or by a single pixel clock. The double clock typically is used for TV displays, the single for computer displays.
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6. FLASH MEMORY
The decoder board supports 70ns Flash memories. FLASH_512K_8b The MT1389D permits 8- bit common memory I/O accesses.
AND
PLL COMPONENT
The MT1389D audio mode configuration is selectable, allowing it to interface directly with 2 low-cost audio DACs and ADCs. The audio port provides a standard I S interface input and 2 output and S/PDIF (IEC958) audio output. Stereo mode is in I S format while six channels Dolby Digital (5.1 channel) audio output can be channeled through the S/PDIF. The S/PDIF interface 2 consists of a bi-phase mark encoder, which has low skew. The transmit I S interface supports the 112, 128, 192, 256, 384, and 512 sampling frequency formats, where sampling frequency Fs is 2 usually 32 kHz, 44.1 kHz, 48 kHz, 96 kHz, or 192 kHz. The audio samples for the I S transmit interface can be 16, 18, 20, 24, and 32-bit samples. For Linear PCM audio stream format, the MT1389D supports 48 kHz and 96 kHz. Dolby Digital audio only supports 48 kHz. The MT1389D incorporates a built-in programmable analog PLL in the device architecture in order to generate a master audio clock. The MCLK pin is for the audio DAC clock and can either be an output from or an input to the MT1389D. Audio data out (TSD) and audio frame sync (TWS) are clocked out of the MT1389D based on the audio transmit bit clock (TBCK). Audio receive bit clock (RBCK) is used to clock in audio data in (RSD) and audio receive frame sync (RWS).
9. FRONT PANEL
9.1 VFD CONTROLLER
The VFD controller is PTC16311. This controller is not a processor, but does include a simple state machine which scans the VFD and reads the front panel button matrix. The 16311 also includes RAM so it can store the current state of all the VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD status changes and when the button status is read. The MT1389D can control this chip directly using PIO pins or can allow the front panel PIC to control the VFD.
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10. CONNECTORS
10.1 SCART CONNECTORS
Pinout of the scart connector: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Audio Right Out Audio Right In Audio Left / Monu Out Audio Gnd Blue Gnd Audio Left / Mono In Blue Control Voltage Green Gnd Comms Data 2 Green Comms Data 1 Red Gnd Comms Data Gnd Red Fast Blanking Video Gnd Fast Blanking Gnd Composite Video In Composite Video Out Shield
Some cheaper SCART cables use unshielded wires, which is just about acceptable for short cable lengths. For longer lengths, shielded co-ax cable become essential.
Scart Signals:
Audio signals 0.5V RMS, <1K output impedance, >10K input impedance. Red, Green, Blue 0.7Vpp 2dB, 75R input and output impedance. Note that the Red connection (pin 20) can alternatively carry the S-Video Chrominance signal, which is 0.3V. Composite Video / CSync 1Vpp including sync, 2dB, 75R input and output impedance.Bandwidth = 25Hz to 4.8MHz for normal TV Video de-emphasis to CCIR 405.1 (625-line TV) Fast Blanking 75R input and output impedance. This control voltage allows devices to over-ride the composite video input with RGB inputs, for example when inserting closed caption text. It is called fast because this can be done at the same speeds as other video signals, which is why it requires the same 75R impedances.
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composite to 0V
1V to 3V: the TV is driven by the signals Red, Green, Blue and composite sync. The latter is sent to the TV on pin 19. This signal is useful when using a TV to display the RGB output of devices such as home computers with TV-compatible frame rates. Tying the signal to 5V via 100R forms a potential divider with the 75R termination, holding the signal at around 2V. Alternatively, if a TTL level (0 to 5V) negative sync pulse is available, this will be high during the display periods, so this can drive the blanking signal via a suitable resistor. Control Voltage 0 to 2V = TV, Normal. 5 to 8V = TV wide screen 9.5 to 12V = AV mode
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LED red in stand-by mode and green when the device is on. When entering stand-by mode, pin 48 goes HIGH (+5V) and controls the transistor Q2 on the power board. Vacuum fluorescent display is specially designed for DVD. The scanned keys are transmitted via PTC 16311 pin 5 and 6 to the mainboard. IR remote control receiver module (TSOP1836) sends the commands from the remote control directly to mainboard. Socket PL3 carries the VFD filament voltage and 22 Volts.
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SOFTWARE UPDATE
Universal Service Password
The Universal Service Password for Parental Level is 1369.
First 6 lines contain current VERSION information. The first 5 lines (Version, Macrovision FW. V., Servo, Risc and DSP) are for factory use only and the 6th line (Build No) is for customer use. 7th line contains Region Code (Management ). The 6th line (Build No) has both the hardware option (example: C6KN1) and the software build version (example: 6027-13F) information. Hardware option part is also used as the CD update file name. Press DISPLAY key to exit from Version Page.
CD Update Procedure
1. Any Player can be updated automatically with Update CD which contains proper files 2. Burn up CD within proper files (There should be no Volume Name for CD)
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3. 4. 5. 6. 7. 8. 9.
Open Tray and place update CD You can see "Upgrade File Detected. Press Play to start" OSD message Press Play button to start upgrade You can see "File copying" OSD message for a few second Tray is open automatically No need for CD in tray; Take it from tray. During upgrade procedure "CD upgrade start, Please wait.." indicator at OSD, and "UPG" indicator at VFD 10. Upgrade procedure takes about a few minutes, please wait if tray is open. 11. When CD update is finished tray is closed, screen is refreshed, update is finished. 12. To see Version Page: Press DISPLAY key. Setup Menu is displayed. Press 1-3-5-7 in Setup Menu when Video Setup Page is selected. Version Page is displayed. The 6th line (Build No) has both the hardware option (example: C6KN1) and the software build version (example: 6027-13F) information. Press DISPLAY key to exit from Version Page.
Region Management
In Version Page by using Up and Down arrow keys the region code can be adjusted.
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89D_KHM310_FAIRCHILD_V1
MT1389D (LQFP216) DVD Demo Board for KHM310 with FAN8025 Motor Driver
Mainboard
1 INDEX & POWER, RESET 2 RF, SERVO & MPEG - MT1389D 3 MEMORY - SDRAM, FLASH/EEPROM 4 VIDEO OUT 5 AUDIO DAC
D
NAME VCC DV33 RFV33 LDO_AV33 AVCC V18 SD33 +12V -12V AVDD DVDD
TYPE Digital 5V Digital 3.3V Servo 3.3V Laser Diode 3.3V RF 5V Digital 1.8V Digital 3.3V Audio +12V Audio -12V Audio 5V Audio 3V3
PICKUP HEADER MT1389E SDRAM OP AMP. OP AMP. Audio DAC Audio DAC
CON1
URST# [ 2 ] V18 DV33 VCC AVCC +12V [2] [ 2,3,4,5 ] [ 2,3,4,5 ] [2]
GND
0.1uF
1
L6 PV33 L7 FB V33
VCC_AUDIO
+P5V
FB
CB6
+ CE5
0.1uF
220uF/16V
AVCC
VCC
FB
VCC
A
+P5V
FB
CB9
+ CE9
0.1uF
220uF/16V
20
L1 DV33 DV33 FB CB1 0.1uF V33 +12V L4 FB CB3 C 0.1uF 220uF/16V 0.1uF 220uF/16V RT9164CG/AZ1117H-ADJ SOT223/SMD + CE3 R1 R CB4 + CE4 C1 FB CB5 0.1uF 3 IN OUT 2 V18 U1 L5 V18 220uF/16V + CE1 V33 R2 R
8 7 6 5 4 3 2 1
-12V GND
PWR, 8P,PITCH=2.54M/M
L2
-12V
L3
-P12V
+P12V
FB
FB
CB2
CE2
220uF/16V
DV33
D1 1N4148
R3 10k
URST#
V33 CE6 +
L9
V33
FB CB7 0.1uF
Regulator
Fix regulator Adj regulator
R1 0 ohm 300 1%
R2
47uF/16V
OFF
680 1%
L10
FB
MediaTek Incorporation
89D_KHM310_FAICHILD_V1
Document Number
INDEX
Wednesday, January 05, 2005
1
Rev 1 Sheet 1 of 5
L13 RFV33 RFVDD3 JITFO C2 JITFN L14 CB10 0.1uF 10uF/25v DACVDD3 CB11 FB + CE11 + CE10 DV33 R5 750k 390pF
APLLVDD3
R4 0
L12 FB
DV33
C4 0.1uF/N.C
C8
14
L16 2.7u, DIP U2A 1
C9
XI XO
R8 1000pF
R10 150k
R11
14
V1P4
C13
C14 2200pF
680k
C16
0 0
R20
0.1uF
0.033uF
0.047uF
RFVDD3
RFVDD3
0.1uF
SPSP+ LIMIT + C19 6800PF XI FS VREF R21 C28 C26 22p 2K C27 22p 0.1uF R23 4.7k V18 VCC XO CE13 1000uF/16v 0.1uF Y1 1 C27MHz 2
R19 1k R0603/SMD
C20
C23
AL
AR ADACVDD3
APLLVDD3 Y6 Y5
Y4 DACVDD3
DACVDD3 Y3
DV33 V2P8 V20 CB14 0.1uF 47uF/16v 0.1uF 47uF/16v V1P4 CB15 CB13 0.1uF 47uF/16v
L17 C31 C34 C C33 1uF R24 R25 R26 0 0 0 TROUT TRIN LIMIT 1uF
C29
AVDD3 IREF RFGC OSN OSP RFGND CRTPLP HRFZC RFRPAC RFRPDC RFVDD3 ADCVSS ADCVDD3 LPFOP LPFIN LPFIP LPFON PLLVDD3 IDACEXLP PLLVSS JITFN JITFO XTALI XTALO RFVDD18 RFGND18 ADACGND AL VCM AR ADACVDD3 APLLVSS APLLCAP APLLVDD3 R B DACVSSA G DACVDDA DACVSSB DACVDDB CVBS DACVSSC FS VREF DACVDDC SPDIF MC_DATA DVDD3 ASDATA3 ASDATA2 ASDATA1 ASDATA0 ALRCK
V18
FB
RFV18 CB16
0.1uF
216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163
R22
10k
+ CE14
+ CE15
+ CE16
C21 C25
1 2 3 4 5 6 C24 0.1uF
PLLVDD3
SLSL+
C B A D RFO
R15
J1
ADACVDD3
C3
1 RFVDD3 CB17 0.1uF IOA TP28 TP30 TP31 TP32 C36 0.1uF C37 V1P4 C R R34 FEO TEO TEZISLV V2P8 V20 V1P4 TP2 TP1 RFOP RFON MA2 MA1 MA0 MA10
E2
2N3904
AVCC
R29
10k
R28
100k
MT1389D
V1.7
R30
10k
Q1 SOT23/SMD
R31
100k
2SK3018
Q2 2SK3018
Q3 2SK3018
AVCC
TOP
IOA18 DVSS IOA19 DVDD3 IOWR# A16 DVDD3 HIGHA7 HIGHA6 HIGHA5 HIGHA4 HIGHA3 HIGHA2 HIGHA1 IOA20 IOCS# DVSS IOA1 IOOE# DVSS AD0 AD1 AD2 AD3 AD4 AD5 AD6 IOA21 ALE DVDD18 AD7 A17 DVDD3 IOA0 UWR# URD# UP1_2 UP1_3 GPIO6 UP1_4 UP1_5 UP1_6 DVSS UP1_7 UP3_0 UP3_1 UP3_4 UP3_5 GPIO7 ICE PRST# IR INT0# DVDD3
PCE#
A0
PWR# A16
SDA
URST# IR
R36
4.7
LDO_AV33
AD7 A17
CE19 47uF/16v
A1 PRD#
10uH V18 + CE20 47uF/16v MO_VCC MO_VCC U4 LOADLOAD+ R40 FOSO GND R47 FTTRSO R54 20k R41 10k TROPEN TRCLOSE 10k R44 10k SPSP+ SLSL+ FMSO DMSO R43 R45 GND 30 G2 G1 29 V1P4 STBY F+ T+ 4K2 8K2 15 16 17 18 19 20 21 VOTK+ VOTKVOLD+ VOLDVCC VNFTK PVCC2 VOFC+ VOFCVOSL+ VOSLPGND PVCC1 VCC 14 13 12 11 10 9 8 DV33 R39 R42 10k 10k LOADLOAD+ TROUT TRIN 1 2 3 4 5 5x1 W/HOUSING Pitch2.0mm LDO1 DV33 J3 CB24 0.1uF R38 10k TP35
R37
4.7
Q5
2SB1132
21
V18 STBY V18 R35 A2 0 TRO FOO ADIN FS0 FS1 2
R32
R33
L18
FB
HA1
100 100
C38 0.1uF
CE18 100uF/16v
GND LD-DVD
TP33
TP5
TP12
TP13
TP21 TP22
TP34 TP19
TP14
L19
C C
A18 A19 LDO2 DV33
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 IR BA1 BA0 CS# RAS# CAS# WE# DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM0 AGND DVDA DVDB DVDC DVDD DVDRFIP DVDRFIN MA MB MC MD SA SB SC SD CDFON CDFOP TNI TPI MDI1 MDI2 LDO2 LDO1 SVDD3 CSO/RFOP RFLVL/RFON SGND V2REFO V20 VREFO FEO TEO TEZISLV OP_OUT OP_INN OP_INP DMO FMO TROPENPWM PWMOUT1/ADIN0 TRO FOO FG/ADIN1 GPIO0 GPIO1 GPIO2 IOA2 DVDD18 IOA3 IOA4 IOA5 IOA6 IOA7 HIGHA0 ACLK ABCK DVSS GPIO5 GPIO4 GPIO3 DVDD18 RA4 RA5 RA6 RA7 DVDD3 RA8 RA9 RA11 CKE RCLK DVSS RA3 DVSS RA2 RA1 RA0 RA10 DVDD3 BA1 BA0 RCS# RAS# DVDD18 CAS# RWE# DVSS DQM1 RD8 RD9 RD10 RD11 RD12 DVDD3 RD13 RD14 DVSS RD15 RD0 RD1 RD2 DVSS RD3 RD4 RD5 RD6 RD7 DQM0 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
10uH
E3
2SB1132
Q4
2SB1132
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
TP20 TP8 TP9 TP11 TP15 CB18 TP10 TP7 0.1uF TP3 TP4 TP16 TP17 L20
R49 10k FR52 R53 R55 R56 CE21 + 0.1uF 0.1uF 100UF CB34 CB35 1 1 1 1 T-
FOSO TRSO FMSO DMSO C39 150p 20K C40 150p CB33 0.1uF C41 C42 330pF 330pF C43 0.1uF C44
22 23 24 25 26 27 28 PREGND VINLD CTK2 CTK1 VINTK BIAS STBY VNFFC VOSL VINSLVINSL+ CF2 CF1 VINFC
7 6 5 4 3 2 1
FAIRCHILD8025
20pF
0.47uF/N.C
R6
680k
OPO L15
R7
ADIN
0.1uF
0.01uF
2200pF
100k
0.1uF
C3
2200pF
FB C5 C6 C7
V1P4
RFV33
XTALI C18 C
R16
R201 10 R27 J2
C35 100pF
10 + CE17 100uF/16V
6 5 4 3 2 1
MUTE_DAC URST# Y[3..6] VIDEO INTERFACE A[0..19] AD[0..7] PRD# PWR# PCE# A[0..19] AD[0..7] PRD# PWR# PCE# FLASH MA[0..10] MA[0..10] DQ[0..15] BA[0..1]
U3 MT1389D
[3] [3] [3] [3] [3] [3] DQ[0..15] BA[0..1] DQM[0..1] DCLK LQFP216/SMD DCKE CAS# RAS# WE# CS# V18 DQM[0..1] DCLK DCKE CAS# RAS# WE# CS# MEMORY CB19 0.1uF CB20 0.1uF CB21 0.1uF CB22 0.1uF CB23 0.1uF SCL SDA DV33 IIC CB25 0.1uF CB26 0.1uF CB27 0.1uF CB28 0.1uF CB29 0.1uF ASDAT[0..2] AUDIO_RST VSDA ASTB VSCK DV33 ALRCK ACLK ABCK ASPDIF ASDAT[0..2] AUDIO_RST VSDA ASTB VSCK ALRCK ACLK ABCK ASPDIF [5] [5] [5] [5] [5] [5] [5] [5] [4] SCL SDA [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3]
B
CB30 0.1uF
CB31 0.1uF
CB32 0.1uF
AUDIO INTERFACE
A
0.015uF V1P4 TP27 TP26 TP25 TP24 VCC L21 FB MO_VCC RxD TxD DV33 1 2 3 4 4x1 W/HOUSING Pitch2.54mm Title J4
MediaTek Incorporation
89D_KHM310_FAICHILD_V1
RS-232
3 2
Size C Date:
Document Number
RF&MEPG
Wednesday, January 05, 2005
1
Rev 1 Sheet 2 of 5
U5
U6
DV33 SD33
L22
FB
SD33
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 DBA0 21 22 23 24 27 28 29 30 31 32 20 19 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA/A11 SD33 CLK CKE + CE22 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 220uF/16V SD33 CB42 0.1uF 0.1uF CB47 0.1uF 0.1uF 0.1uF CB43 0.1uF CB45 CB44 CB46 [2] DQ[0..15] CB36 CB38 CB39 CB37 CB40 CB41 VCC VCC SD33 VCCQ VCCQ VCCQ VCCQ + CE23 220uF/16V 7 13 38 44 1 25 35 34 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SDCLK SDCKE 2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49
21 22 23 24 27 28 29 30 31 32 20 19
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 BA/A11
MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 DBA0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SD33
SDCLK SDCKE
35 34
CLK CKE DBA1 DRAS# DCAS# DWE# 18 17 16 15 CS RAS CAS WE DQML DQMH NC NC VSS VSS VSSQ VSSQ VSSQ VSSQ 4 10 41 47 14 36 33 37 26 50 DQM0 DQM1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
2 3 5 6 8 9 11 12 39 40 42 43 45 46 48 49
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 SD33
18 17 16 15
CS RAS CAS WE
VCC VCC
1 25
SD33
DQM0 DQM1
14 36
DQML DQMH
33 37
7 13 38 44
NC NC
DQ[0..15]
26 50
VSS VSS
4 10 41 47
HY57V161610ET-7
HY57V161610ET-7
MA[0..10] BA[0..1] DQM[0..1] DCLK DCKE CAS# RAS# WE# CS# DRAM
RN1 DCS# DRAS# DCAS# DWE# 1 3 5 7 33x4 DBA0 DBA1 SDCKE SDCLK VCC L23 FLASH_VCC L24 CB48 0.1uF FB + CE24 47uF/16V R63 DV33 U8 CB50 0.1uF 680 NO_USE DV33 R57 R58 R59 R60 33 33 33 33 BA0 BA1 DCKE DCLK [2] [2] SCL SDA IIC GND DV33 VCC GND DV33 VCC [ 1,2,3,4,5 ] [1] [1] DV33 SCL SDA
B
22
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 10k FLASH_VCC WP/ACC BYTE VCC CB49 0.1uF GND1 GND2 27 46 37 47 14 R61 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45
4 3
2 4 6 8
U7
FLASH_VCC
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19
R62
25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 9 10
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
R64 680
10k
26 28 11
CE OE WE
FLASH_VCC
12
RESET
STM29W800/MX29LV400(800)
1 2 3 4
TSOP 48 pin
NC NC NC GND
8 7 6 5
SCL SDA
4M 8M FLASH
MediaTek Incorporation
89D_KHM310_FAICHILD_V1 Document Number
SDRAM&FLASH
Wednesday, January 05, 2005 Sheet
1
Rev 1 3 of 5
3906 C
+5VV R65 75,1% R CVBS J5
R66
Y3 Q6 3906 1 D2 1N4148 [2] ASPDIF Y[3..6] GND VCC R68 75,1% R CVBS_ST CVBS 2 1 +12V -12V FS0 FS1 RGB_SWITCH FR FL 3 +5VV
R67 NC
C45
C46
NC
NCP
L25 NC
ASPDIF Y[3..6] [2] [1] GND VCC +12V -12V [1] [1] [1] FS0 FS1 RGB_SWITCH FR FL [1] [1] [4] [4] [4]
CVBS_ST R/V G/Y B/U GND C_RGB_SWITCH C_FS GND FL FR VCC 1 2 3 4 5 6 7 8 9 10 11 SCART, 11P, PITCH=2.540M/M
+5VV
R212 0
R69
Y3
L26 1.8uH,DIP
Q7 3906 +5VV ASPDIF 3 5 C67 110 P3 VCC R155 22 4 R156 OPTICAL 5 C69 CE31 + 10uF/16V G/Y +5VV 3 D19 V33 1N4148 R74 +5VV 27pF 0.1uF P4 RCA+SPDIF CB55 22 100pF R149 3 0.1uF D18 1N4148 100pF C66 100 75 R144 R145 CB54 1
S-VIDEO + RCA 4
C47
C48
R70 150,1%
47P
47P
R71 75,1% R
R72
RGB_SWITCH Q10
+P12V R81 1K
R82
Y5
L30 1.8uH,DIP
FS1 3 R85 1K
2N3904
C51
C52
Q14
C53
C54
47P
47P
23
Q8 3906
Y4 1
L27 1.8uH,DIP
SCART CONTROL
R73 150,1%
C49
C50
47P
47P
10k 1 Q9
6 7 8
3 2 1
+5VV
47P
47P
FS0 R87 1K
+ CE25 47uF/16V
A2
R90
L31 1.8uH,DIP
A
Title
MediaTek Incorporation
89D_KHM310_FAICHILD_V1 Size Document Number Custom Date:
Rev 1 Sheet 4 of 5
VCC R197 C55 R94 NC EC1 R97 R98 R99 100k [2] [2] SCL SDA R101 100 FL SCL SDA -12V 220p R93 DV33 180k 0 R194 DAC_FL
+P12V
AL
R92
20k
R95
R96
4
U9A 1 LM833 A_MUTE Q18 2N3904 C87 47p [2] [ 1,2,3,5 ] GND AUDIO_RST 47uF/16V EC2 R104 NC 47uF/16V R198 R109 0 R211 NC +12V [2] [2] [2] [2] [2] 270p ASPDIF ASDAT[0..2] ACLK ABCK ALRCK C58 NC +12V NC NC R105 R106 0 2 + 3 NC 2200P C56 10k 5.1k C57
1N4148 2
R102
D14
-12V +12V DV33 VCC GND AUDIO_RST ASPDIF ASDAT[0..2] ACLK ABCK ALRCK MUTE_DAC
1N4148 1 0.1uF 100uF/16V A_MUTE R110 0 R111 10,0805 AR R209 C59 R114 NC EC3 R117 R118 R119 100k -12V 220p R113 R195 180k 0 DAC_FR 100uF/16V A_AVDD CB53 0.1uF + CE30 R112 20k A_AVDD Q19 3906
22k
470uF/16V
R103
R108
470
+ CE29
D15 1
1N4148 2
100uF/16V
VCC
R115
R116
4.7k
100k
Q21 3906
R120 10K
47uF/16V
D17 1
INT_ADAC 1800P
+
NC NC R131 0 R210 NC R141 20k R203 R142 -12V R146 R147 R148 180k NC EC5 100k R143 C63 220p NC +12V 270p C62 +12V NC
180P 220P
R208
30K 20K
47uF/16V
EXT_ADAC
2200P
A_AVDD
R 0 0 R
1 2 3 4 5 6 7 8 9 10
IF use PCM1606,EC?=10uF 47uF/16V EC6 R151 NC 47uF/16V R202 R154 0 NC NC NC C68 270p R152 R153 DEMP0 DEMP1 Audio Interface LOUT2 NC 2200P 0 2 3 C64 10k 5.1k C65
DAC_SL
PCM1606 -
4 1 + LM833 A_MUTE SL FR 7 1
HARDWARE MODE
+
FMT0 LOW LOW HIGH HIGH OFF 44.1KHz 48KHz 32KHz LOW HIGH LOW HIGH
FMT1
FORMAT
C85 47p
SL SR
R159 R158 180k A_AVDD DAC_SR NC EC7 100k R160 0 R165 NC R170 MUTE1 R199 R171 1 R207 R173 NC 180k DAC_CENT EC9 100k R175 R176 R177 R174 C74 220p NC R172 20k 0 47uF/16V C71 NC R161 10k R166 NC R168 0 C72 2200P R162
ROUT1 DAC_FR LOUT2 DAC_SL ROUT2 DAC_SR LOUT3 DAC_CENT ROUT3 DAC_LFE
44 43 42 41 40 39 38 37 36 35 34
R163 100
SR A_MUTE
MUTE1
C84 47p
+12V
B
CB56 0.1uF
CB57 0.1uF
11
R2200
10
DATA1 SCKI DATA2 BCK DATA3 LRCK FMT1 DEMP1 FMT0 DEMP0 ZEROA VCC AGND VCOM OUT5 OUT4 OUT6 OUT3 OUT1 OUT2
20 19 18 17 16 15 14 13 12 11
DVSS SDTI1 SDTI2 SDTI3 LRCK SMUTE CCLK CDTI CSN DFS0 CKS0
VCC_AUDIO
1 2 3 4 5 6 7 8 9 10 11 AVDD VREFH DZFR2 DZFL3 DZFR3 DZFE DIF2 DIF1 DIF0 CKS2 CKS1
LOUT1LOUT1+ DZFL2 DZFR1 DZFL1 CAD0 CAD1 PDN BLCK MCLK DVDD
AK4356
33 32 31 30 29 28 27 26 25 24 23
12 13 14 15 16 17 18 19 20 21 22
R180
R181
LOUT3
NC
NC
R182 0
NC
C77 270p
A_AVDD
R183 20k R205 DAC_FL DAC_FR DAC_SL DAC_SR R184 NC 180k DAC_LFE EC11 100k R186 R187 R188 R185 C78 220p -12V
A
U14
U13B NC EC12 ROUT3 R190 R191 2200P R192 5 47uF/16V 0 C79 10k C80 5.1k 6 7
R189 100 +
R84
NC
AUDIO_RST
SCL SDA
LM833
A_MUTE
R107
1 2 3 4 5 6 7 8 9 10 11 12 13 14 MUTEC1 AOUTA1 AOUTB1 MUTEC2 AOUTA2 AOUTB2 VA GND AOUTA3 AOUTB3 MUTEC3 VQ FILT+ M2
R88
VLS SDIN1 SDIN2 SDIN3 SCLK LRCK MCLK VD GND RSTB DIF1 DIF0 M1 VLC
28 27 26 25 24 23 22 21 20 19 18 17 16 15
47uF/16V R204 NC
NC
NC
R193 0
NC
C81 270p
+12V
CB62
CB63
CS4360-KZ
0.1u
0.1u
NC
2200P
C75
10k
C76
5.1k
Q22 2N3904 -12V U13A 1 LM833 +12V A_MUTE R178 100 CENT Q25 2N3904 LFE Q26 2N3904 C83 47p
MUTE_DAC
0 6
C61
R122 100
[ 2 ] MUTE_DAC VSCK [2] VSDA [2] ASTB [2] FR FL ACLK ALRCK ABCK C86 47p R121 R123 R124 ASDAT0 R129 ASDAT1 R130 ASDAT2 R132 AL AR
33 33 33 33 33 33 AL AR
24
CB58 0.1uF
-12V
CB60 0.1uF
CB61 0.1uF
MediaTek Incorporation
89D_KHM310_FAICHILD_V1 Document Number
Rev 4 Sheet 5 of 5
6 1 2 3 4 5
PL1
ST_BY 10k 10k R29 R31 +5V Q1 BC548B
+5V
C11
220p 50V
1
L1
PL2
Front Panel:
1u
D6 K 2
C4
10k R33 Q2 BC548B
R32 2k2 C3
+5V
OUT
R5 56K
1 2 3
IC3 TSOP1836
50V 47u
-22V
GND VS
C9
R6 100R
C5
R19 10R
R18 10R
R17 10R
44
43
42
41
40
39
38
37
36
35
34
R9 1k
100n 50V C2
GR1
47u 50V
GR2
GR3
GR4
OSC
LED1
LED2
LED3
LED4
GND2
VDD2
R12 1k
1 SW1
R13 1k
R14 10R
IC4 PT6312
SG13/GR10 28
25
R15 10R
8 CLK 9 STB 10 K1 11 K2
-22V
SG1/KS1
SG2/KS2
SG3/KS3
SG4/KS4
SG5/KS5
SG6/KS6
SG7
SG8
VDD1 14
K3 12
+5V
K4 13 15 16 17 18 19 20
21
22
S1
1 2 R3 10k R4 10k 3 4 5 6 7 8 9
HUV-08SS52T
FL1
MD1
SKIP+
1N4148 D2
12FP3060V
SW2 TSW_HOR. SW5 TSW_HOR. ST-BY STOP
DvD4500 12/2005
SW6 TSW_HOR.
E&O
1N4148 D4
FL2
29 F_POS_1 30 F_POS_2
SW3 TSW_HOR.