PFCM Design Guide

PFCM Design Guide with Analog PFC IC

HP SPM & System Engineering Group FAIRCHILD SEMICONDUCTOR

82-3, Dodang-Dong, Wonmi-ku, Puchon, Kyonggi-Do, KOREA Tel) 82-32-680-1834, Fax) 82-32-680-1823

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PFCM Design Guide

Contents
1. 2. System Configurations.......................................................................... 3 Protection Circuits ................................................................................. 3
Over Current Protection (OCP).............................................................................................................. 3 Over Voltage Protection......................................................................................................................... 4 Under Voltage Protection....................................................................................................................... 4

3.

Design Example (PFCM DEMO BOARD) .............................................. 5

Operating conditions of PFCM demo board:........................................................................................... 5 Output capacitance and Inductance design ............................................................................................ 5 Output Voltage Ripple & Output Capacitance ...................................................................................... 5 Inductance & Input Current Ripple ....................................................................................................... 6 Open Loop Response................................................................................................................................ 6 Current Loop Amplifier .......................................................................................................................... 7 Voltage Loop Amplifier .......................................................................................................................... 7 Control Loop Implementation ................................................................................................................ 8 Current Loop........................................................................................................................................... 8 Voltage Loop........................................................................................................................................... 9 Other Parameters ................................................................................................................................. 10 Over Current Protection....................................................................................................................... 12 Over Voltage Protection....................................................................................................................... 13 DC-link Voltage Control........................................................................................................................... 14

4.

Experimental Results........................................................................... 15

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PFCM Design Guide

1. System Configurations

Vac N/ F

Relay

VTH RTH S R
NTC Thermistor

PR

SPM
IN(S) IN(R)

LVIC
Shunt Resistor

VAC-

NSENSE

Control IC

Fig.1 Typical block diagram of PFCM system

An inrush-current prevention circuit is required due to the large DC link capacitance as shown in Fig. 1. The relay of the circuit should be closed after DC link capacitor is charged far enough. PFCM, mini-SPM and control IC can share single GND stage. Usually, this GND and the NSENSE terminal of PFCM should have the same potential. Large surge voltage is easily produced between P and N terminals by large current switching. To reduce surge voltage it is important to shorten the DC link bus wiring between PFCM and DC link capacitor. In addition, good high frequency characteristic capacitor, such as polypropylene film capacitor should be mounted near to P and N terminals as a snubber.

2. Protection Circuits
Following Fig. 2 shows the timing chart of protection function. There are two kind of protection level for both OCP and OVP. Generally, PFC control ICs have its own OCP and OVP function. Also, user can make the PFCM stop and output the FO signal under preset OC, OV condition using its Csc input.
Over Current Protection (OCP)

[OCP Level1 PFCM] PFCM can protect from over current situation. When OC(over current) situation happens, the PFCM stops operating and generates fault out signal during fault-out duration time(set by CFOD). And then after the duration, it works again according to the input command. Its total propagation delay time may depend on outer op-amp speed. We recommend using a low cost slow op-amp solution with fast protection. It is the OCP level2 protection described in next paragraph. [OCP Level2 (SCP) PFC control IC] By the peak current limit function of PFC control IC, the system is protected from SC(Short Circuit) situation. The recommended current limit of OCP level 2 is higher than

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PFCM Design Guide

that of OCP level 1. It doesnt generate the fault out signal but its response is very fast. It will protect the system from short circuit situation during the propagation delay time of OCP level1.

Over Voltage Protection

OV (Over Voltage) protection can be also implemented by dual protection. The DC-link voltage changes slowly because of its large capacitance. So OVP does not need fast response. Therefore it is optional to activate the OVP of PFC controller. [OVP Level 1 - PFC controller] OVP level 1 suppresses voltage overshoot in transient situation. It doesnt generate fault out signal. [OVP Level 2 PFCM] The voltage level of OVP level 2 is higher than that of OVP level 1. When OV situation happens, the PFCM stops operating and generates fault out signal during fault-out duration time(set by CFOD). And then it works again.

Under Voltage Protection

IGBT gate will be interrupted when control voltage drops below UV trip level, and the protection will be realeased automatically if the control voltage recovers to the UV reset level.

Fig.2 Timing chart of protection function

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PFCM Design Guide

3. Design Example (PFCM DEMO BOARD)

A general PFC example is implemented for 5[kW] air-conditioning applications whose input voltage is 187~276[V].

Operating conditions of PFCM demo board:

Table 1. The operating conditions.

Item 1 2 3 4 5 6 7 8 9 11 Switching Frequency Minimum Input Voltage Nominal Input Voltage Maximum Input Voltage Output Max. Power Minimum Output Voltage Nominal Output Voltage OVP level 1 OVP level 2 OCP Level1

Symbol Fsw Vimin Vinom Vimax Po Vomin Vonom VOV1 VOV2 Iripple Iocp1 Iocp2 Rsh Cout

Value 40 176 220 264 5000 350 380 420 440 5 40 50 2 940

Unit KHz Vac Vac Vac W Vdc Vdc V V A A A MOhm uF

10 Peak Ripple Current 12 OCP Level2 (SCP) 13 Shunt Resistor 14 DC Capacitor

Output capacitance and Inductance design

Output Voltage Ripple & Output Capacitance

Voltage ripple of VDC can be reduced by employing large COUT. In demo board, COUT is set to 940[uF] (470[uF] x 2)

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PFCM Design Guide

Inductance & Input Current Ripple

where:

ILp-p : Peak to peak current of PFC inductor VIN : Input AC voltage VOUTDC : DC link Voltage f : Switching frequency L : Inductance of PFC inductor

I L P P =

V IN (VOUTDC V IN ) fLVOUTDC

(I LP P ) MAX =

VOUTDC 4 fL

( V IN =

1 VOUTDC ) 2

(I LP P ) MAX = 5 A

L=

VOUTDC 380 = = 475[ H ] (fs=40kHz) 20 f 20 40000

Current ripple is decided by switching frequency and inductance. To reduce current ripple, high switching frequency and large inductance value is required. It means that employing higher switching frequency can reduce inductor size. But the power losses will increase and it requires more efficient heat sink structure.

Open Loop Response

Fig.3 Block diagram of PFC control IC

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PFCM Design Guide

The following is the block diagram of PFC controller ucc3818. The average current mode control is composed of two types of loops- voltage loop and current loop. The voltage loop controls the output DC-Link voltage. It regulates the output voltage. There is a 120[Hz] ripple voltage in the output DC-Link, which is caused by the 60[Hz] ac input current. Hence, the voltage loop must be designed to be slow enough to reject the 120[Hz] ripple voltage. In general CCM (Continuous Current Mode) PFC IC, there is a multiplier. It multiplies VEA(the output of voltage loop) by IAC(reference of input ac current shape) and then divides it by VRMS(reference of rms input voltage). The output( I MO = K

VEA I AC VRMS
2

) of a multiplier is the reference of the PFCs input current(IAC).

The difference between the voltage of IMO pin(output of the multiplier) and the voltage of the current sensing resister is amplified by the current loop. The VEA(output of the current loop) is the reference voltage to the comparameter that generates the gating signal. Current loop should be fast enough to catch up with the 120[Hz] input ac current. But too fast speed can distort the current shape due to the switching noise. Therefore, the current loop must be designed to be fast enough to catch up with the 120[Hz] rectified input current, but not too fast for switching noise immunity.
Current Loop Amplifier

Eq. 1 shows the open loop response of power stage. (Refer to UCC3818 datasheet)

G PST =
where:

VS ( s ) V R = DC SH (UCC3818) V IAOUT ( s ) 4 sL
VS : Voltage of shunt resistor VIAOUT : Voltage of RMO VDC : DC link Voltage

(Eq.1)

RSH : Shunt resistance for current sensing (2mohm) L : PFC inductance s:

Voltage Loop Amplifier

j(= j2f)

Eq. 2 shows the open loop response of power stage. (Refer to UCC3818 datasheet)

GV .O.L. =
where:

PIN sCOUT VOUTDC VEAOUT

PIN : Input power

(UCC3818)

(Eq.2)

COUT : DC link capacitance VOUTDC : DC link voltage VEAOUT : Error amplifier output difference (5V) s: j(= j2f)

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PFCM Design Guide Control Loop Implementation

Current Loop

[Step 1] Crossover frequency Theoretical crossover frequency is given by following equation.

fC =

fS 6.7 kHz 6
fC = 3.3kHz , f P = 6 f Z = 20kHz 2

(Eq.3)

[Step 2] Fz and Fp decision

fZ =

[Step 3] Rz, Cp, Cz decision Ri is same to RMO. (Refer to other parameters in page 10) Ri = 470[], In Eq.1, G PST
f C = 6.6 kHz

V DC RSH V R = DC SH = 0.0103 = 39.8dB 4sL 4(2f C ) L

Therefore it requires 40dB boosting at fc(=6.6kHz). Rz is given by Eq.7.

G dB = 20 log

Rz = 40dB Ri
Cz = 1[nF]

Rz = 47[k],

From Eq.4 ,Eq.5, Cp and Cz is given. Cp = 180[pF],

fz =
fp =

1 2R z C z
Cz + C p 2R z C z C p

(Eq.4)

(Eq.5)

Rz Cp IARi RMO IA+ CAOUT Cz

Fig.4 Current loop circuit

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PFCM Design Guide

FZ=3.3kHz FC=6.7kHz FP=20kHz

Fig.5 Desired current error amplifier response

[1] [2] [3]

G dB = 20 log G dB = 20 log
G dB = 20 log

1 2fRi C z Rz Ri
1 2fRi C p

(Eq.6) (Eq.7) (Eq.8)

Voltage Loop

GV .O. L.

PIN sC OUT VOUTDC V EAOUT

5000 419 = 2f 0.001 380 5 f

A resistor(RVD) is added between E/A input and sensing resistor. By virtue of large RVD, CVF can be replaced by small SMD type capacitor.

RVD = 120k (>RVS)

RVF = 8 RVD 1M (>RVD) f CV = 1 2RVD CVF << 120

CVF=1uF

( f CV

= 1.3Hz )

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PFCM Design Guide

R VF

Vdc

R VL

C VF R VD EAV re f EAOUT

R VS

Fig.6 Voltage loop circuit

Other Parameters

RT, CT: Switching frequency decision

f =

0.6 RT CT

RT = 15[k] CT = 1[nF] Fs = 40[kHz] RMO: (Refer to fig.4)

RMO =

I AC _ peak Rsense I GMMAX

50 2 0.002 = 471 470[] 300 10 6

(Assuming the input current is 50ARMS @ VAC = 100VRMS) RMO = 470[] Rsense = 0.002[]( small resistance can cause distortions at low level current) RAC & Optocoupler circuit: Optocuopler: TLP180

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PFCM Design Guide

RAX VCC 1 4 Optocoupler

3 RAC ISIN E RL RFF CFF Rc1 CL VFF UCC3818

Rc2

Fig.7 Input AC voltage sensing circuit

RAX and RL depend on optocoupler :

R AX =

VRMS _ max 2 I LINEAR _ max

270 2 = 64[k] 6 10 3

18 + 18 + 18 + 18[k](0.5 4 = 2W ) RAC = VRL _ PEAK I AC _ max = 9 = 18[k] 0.5 10 3

R L = 390[]
RC1 , RC2 , CL, and an op-amp VFF: ISINE off-set compensation CL = 1[uF], RC1 = 0[], RC2 = 150[],

VFF = 1.4[V ] (when, input voltage VAC = 90[VAC])

RFF = 33[k], CFF = 100[uF]

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PFCM Design Guide

Over Current Protection

+ R 19 R 40
VAC-

O C POUT

R 37 R38
VREF(7.5V)

R 18
PKLIMIT

PFCM

UCC3818

Fig.8 Over current protection circuit

The actual protection level can be slightly different from the calculated value. It depends on PCB layout pattern. About demo board, the designed values are: R18 = R40 = 1.2[k], R19 = R37 = 82[k], R38 = 1.5[k] And the expected OC levels are: 1) OCP level 1

( R + R40 )V REF RSH I PK R19 R38 V I PK = REF V REF = 18 R18 + R19 + R40 RSH R19 R37
I PK 40[ A]
2) OCP level 2

R R18 + R40 38 (R18 + R19 + R40 ) R37

R19 + R40 R18V REF V = REF I PK = R18 RSH I PK RSH (R19 + R40 ) I PK 50[ A]

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PFCM Design Guide

Over Voltage Protection

Vdc RZ OVP1 RY OVP2 RX

Fig.9 Over voltage protection circuit

About demo board, the designed values are: RX = 15 [k], RY = 1.8 [k], RZ = 870 (270+270+330) [k] And the expected OC levels are: 1) OVP level 1

VREF _ OV R + RY + RZ R X + RY 886.8 = V DC _ PK = X V REF _ OV = 8 = 422[V ] R X + RY + RZ VDC _ PK R X + RY 16.8

2) OVP level 2

R + RY + RZ RX V 886.8 = REF VDC _ PK = X VREF = 7.5 = 443[V ] 15 RX R X + RY + RZ VDC _ PK

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PFCM Design Guide DC-link Voltage Control

Vdc R VF C VF R VD EA V ref EA OUT

R VL

R VS1

R VS2

Outer OP-AMP

R D1

R D2

V SIG

Fig.10 DC link voltage control circuit

The relation between VDC and parameters is:

RVD RVL RVD 1 1 RVD 1 V DC = 7.5 RVL R R + R + R + R + 1 R RVD + RVL + R VF VS 1 VF VF VS 1 VF VS 1

R V EA VL RVS1

R D1 R +R D2 D1

V SIG

The variable VDC voltage is available by just changing VSIG voltage. VEA, the output of voltage error amplifier changes from 0 to 5.5V as its load current. In no load condition, VEA value is almost zero. And the voltage of VDC will be the highest value. The next graph shows VSIG and VDC voltage. The voltage of VDC in low load condition is higher than that of max. load condition.

VDC [V] Min. load

Max. load VSIG [V] Fig.11. DC link voltage vs. control voltage

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PFCM Design Guide

4. Experimental Results
Fig. 12 shows the overall schematics of implemented PFC converter. Table 2 shows the components that are used for the implemented hardware. Fig. 13 shows the input ac current and DC-link voltage waveforms. These figures details are shown in table 3.
NOTE: 1. C8 and C9 should be close as possible!
VCC 1 P VTR-250 C9 104 1 2 3 4 5 6 7 8 C11 333 Csc TP C14 104 VCC R46 0 U8A 1 1 KA224 1 1 9 10 11 12 13 14 15 16 17 18 19 20 2 VCC 1 VREF C27 104 R37 82K 1 4 U8B 7 KA224 1 Ipk TP 2 2 1 TP5 TP 2 U4 Vcc COM(L) NC IN(R) IN(S) VFO CFOD CSC NC NC NC NC NC NC NC NC NC NC RTH VTH NC NSENSE NR/VAC23 22 21 DCP PR 1 1 2 R7 270K 3216 F 2 R45 270K 3216 F 2 R6 270K 3216 F R44 270K 3216 F R55 270K 3216 F OVP1 TP OVP1 DCN 1 VAO TP 1 1 1 2 1 R9 15K 2012 F 2 1 R29 3.9K 2012 F 1 R43 15K 2012 F 1 C29 104 1 2 JP2 2 C38 104 8 2 27 2 1

Vin TP 1 R13 10 2 PWIN Vfo TP VCC 1 ENA VSIG -FAULT 1 2 C10 101

+ C8 33uF/35V

CNT2 1 2 3 4 5 6 7 HEADER 7

26

+ 2 C12 224/630V

25

R54 330K 3216 F 1

C4 470uF/450V

C5 470uF/450V

C13 101 OVP R32 TP 20K 1 1

R31 20K

24

R10 1.8k 2012 F 2 OVP2 TP OVP2

OVP1

+ -

VREF

11

C30 101

C31 104

SPM27-GA

N VTR-250

JUMPER

VCC

5 6 C35 101

+ 11

PKLIMIT R38 1.5K

C34 104 1

U7 7812 OUT COM IN R21 1 470 VCC

VREF 2

3 2 1

12V

R19 82K PKLIMIT R47 56 C40 183 1 2

2 1 4

PCFN-112 3 K1 Q1 BSS133 3

D1 US1J

C44 105

2 R18 1 1.2K 2 R20 470 1 2 C36 152

R52

C39 821

R40 1.2K 1 2 3 4 5 6

U5 UC3818 GND PKLMT CAOUT CAI MOUT IAC VAOUT VFF DRVOUT VCC CT SS RT VSENSE OVP/EN VREF

470K 3216 R1 470K 3216 2 R23 10K

16 15 14 13 12 11 10 9

C17 102 PWIN VCC C24 105 R25 15K C21 104 2 VCC

RY TP 1

2 1 4

PCFN-112 3 K2

R24 10K

C1 105

R2 47K C16 181

7 R17 47K 1 2 8 R26 33K 1 1 Vff TP

1 2 1 RV1 SVC471D 2 1

2 C2 224/275V 2 1

2 2

C19 105 R27 1M

1 2

470K 5025

R42 120K

AC2 VTR-250

F1 220V/30A

470K 5025 R3 1

R53

R22 1

18K

AC1 VTR-250

RT1 NTC

Iac TP

Vref TP Q2 KRC102

2 1

2 1

J1 VTR-250

J6 VTR-250

CAO TP 1

+ C23 33uF/25V

C26 101

C18 102

VREF

2 3 2

C25 1 2 1 2

J5 VTR-250 R4 1 + 4 2 18K 3216 3 2 4 1 R51 2 18K 3216 VCC 1 5

J2 VTR-250

105

FAN SUPLY
VCC

1 D5 DF08S

ISO1 TLP181 R49 1 2 18K 3216 1 R50 2 18K 3216 1 12V R11 0 JP1 FAN 1 2 3

2 -

Vac TP

R5 390 Offset TP 11 U8D KA224 13 12 2

12V 1

12V TP

C15 105

R48 150 4

VCC

Fig.12. Schematic diagram of the implemented PFC converter.

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Title Size C Date:

<Title> Document Number <Doc> Thursday, September 08, 2005 Sheet 1 of Rev <RevCode> 1

FAIRCHILD SEMICONDUCTOR System Engineering Group 15

R34 20K

11

U8C KA224 9 10 1 R28 1M 2

VSIG

R30 1M

VCC

10K R41 ENA D12 Zener 5.6V C37 104

PFC SW SW SPDT - 1

D8

R8

LED

4.7k

GND TP

Vcc TP

VCC

PFCM Design Guide

Table 2. BOM of PFCM demo board. Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Part C-Ceramic : 101 2012 C-Ceramic : 102 2012 C-Ceramic : 104 2012 C-Ceramic : 105 2012 C-Ceramic : 152 2012 C-Ceramic : 183 2012 C-Ceramic : 221 2012 C-Ceramic : 333 2012 C-Ceramic : 821 2012 C-Elec : 220uF 35V C-ELEC : 33uF 35V C-ELEC : 470uF 450V C-Elec : 47uF 35V C-FILM : 105 630V C-FILM : 220nF AC275V Connector : 7-pin, 2.54mm pitch DIODE : US1J FAN connector : 3-pin, 2.54mm pitch FPS : KA5M02659RN Fuse : 220V/20A JUMPER : 2-pin, 2.54mm pitch LED Main Relay : PCFN-112 Mosfet : BSS138 NTC : 6D-22 Op-Amp : KA224 Opto-coupler : TLP180 Opto-coupler : TLP181 PFC IC : UC3818 PFCM : FPDB30PH60 R-Chip : 0ohm, 1/8W, J, 2012 R-Chip : 1.2Kohm, 1/8W, J, 2012 R-Chip : 1.5Kohm, 1/8W, J, 2012 R-Chip : 1.8kohm, 1/8W, F, 2012 R-Chip : 1.8kohm, 1/8W, J, 2012 Reference C10,C13,C26,C30,C35 C17,C18 SC2,SC4,C9,C14,C21,C27,C29,C31,C34,C37,C38 C1,C15,C19,C24,C25,C44,SC6 C36 C40 C16 C11,SC7 C39 SC5 C8,C23 C4,C5 SC3 C12 C2 CNT2 D1,SD2,SD3,SD4 JP1 U10 F1 JP2 D8 K1,K2 Q1 RT1 U8 ISO1 ISO2 U5 U4 R11,R46 R40,R18 R38 SR6,R10 SR2 Quantity 5 2 11 7 1 1 1 2 1 1 2 2 1 1 1 1 4 1 1 1 1 1 2 1 1 1 1 1 1 1 2 2 1 2 1

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PFCM Design Guide

36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 R-Chip : 100kohm, 1/2W, J, 5025 R-Chip : 10Kohm, 1/8W, J, 2012 R-Chip : 10ohm, 1/8W, J, 2012 R-Chip : 10ohm, 1/8W, J, 2012 R-Chip : 120Kohm, 1/8W, J, 2012 R-Chip : 150ohm, 1/8W, J, 2012 R-Chip : 15Kohm, 1/8W, J, 2012 R-Chip : 18Kohm, 1/4W, J, 3216 R-Chip : 18Kohm, 1/8W, J, 2012 R-Chip : 1Mohm, 1/8W, J, 2012 R-Chip : 20Kohm, 1/8W, J, 2012 R-Chip : 270Kohm, 1/4W, F, 3216 R-Chip : 3.3kohm, 1/8W, J, 2012 R-Chip : 3.9Kohm, 1/8W, J, 2012 R-Chip : 33Kohm, 1/8W, J, 2012 R-Chip : 330Kohm, 1/4W, F, 3216 R-Chip : 390ohm, 1/8W, J, 2012 R-Chip : 4.7Kohm, 1/8W, J, 2012 R-Chip : 470Kohm, 1/4W, F, 3216 R-Chip : 470ohm, 1/8W, J, 2012 R-Chip : 47Kohm, 1/8W, J, 2012 R-Chip : 56ohm, 1/8W, J, 2012 R-Chip : 82Kohm, 1/8W, J, 2012 R-Chip : 9kohm, 1/8W, F, 2012 Regulator : KA78M12 Switch : SW SPDT - 1 Terminal : VTR-250 TR : KRC102 Transformer : EI-1916 TVS : SMBJ170 Varistor : SVC471D Voltage detector : KA431A Zener Diode : 1N4734A, 5.6V Bridge Diode : DF08S SR7,SR8 SR4,R23,R24,R41 R13 SR1 R42 R48 R9,R25,R43 R4,R49,R50,R51 R22 R27,R28,R30 R31,R32,R34 R6,R7,R44,R45,R55 SR3 R29 R26 R54 R5 R8 R1,R3,R52,R53 R20,R21 R2,R17 R47 R19,R37 SR5 U7 PFC SW J1,J2,J5,J6,AC1,AC2,P,N Q2 T1 SD1 RV1 SD5 D12 D5 2 4 1 1 1 1 3 4 1 3 3 5 1 1 1 1 1 1 4 2 2 1 2 1 1 1 8 1 1 1 1 1 1 1

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PFCM Design Guide

VDC (50V/div)

IIN (10A/div)

Fig. 13. Full load test results (IIN = 15ARMS)

Table 3.

Power factor and input power measurement.

VAC [V] Fig.13 * VAC and IAC are RMS values 220

IAC [A] 15

Power [kW] 3.3

Power Factor [%] 99

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