Map Mapping is performed by the MAP program.

During the map phase the SIMPRIM primitives from an NGD netlist are mapped on specific device resources: LUTs, flip-flops, BRAMs and other. The output of the MAP program is stored in the NCD format. In contains precise information about switching delays, but no information about propagation delays (since the layout hasn't been processed yet. Place and route Placement and routing is performed by the PAR program. Place and route is the most important and time consuming step of the implementation. It defines how device resources are located and interconnected inside an FPGA. Placement is even more important than routing, because bad placement would make good routing impossible. In order to provide possibility for FPGA designers to tweak placement, PAR has a "starting cost table" option. PAR accounts for timing constraints set up by the FPGA designer. If at least one constraint can't be met, PAR returns an error. The output of the PAR program is also stored in the NCD format. Timing Constrains In order to ensure that no timing violation (like period, setup or hold violation) will occur in the working design, timing constraints must be specified. Basic timing constraints that should be defined include frequency (period) specification and setup/hold times for input and output pads. The first is done with the PERIOD constraint, the second - with the OFFSET constraint.

Timing constraints for the FPGA project are defined in the UCF file. Instead of editing the UCF file directly, an FPGA designer may prefer to use an appropriate GUI tool. However, the first approach is more powerful [17].

APPENDIX B
The 24 -bits Vedic Multiplier is designed using four 12- bit Vedic multiplier and 12-bit Vedic Multipliers are constructed using four 6- bit Vedic Multiplier and 6-bit Vedic Multipliers are constructed using four 3-bit Array Multipliers. The designs of 12 x 12 Vedic Multiplier and 3 x3 Array Multiplier is shown below in Fig.B1.a and Fig.B1.b

(a) 12-bit Vedic Multiplier design GA0, GA1, GB1 & GB0 represent equally sized groups of inputs and A & B. P1, P2, P3 & P4 represent partial products of size 12 bit length. C1, C2 & C3 represents the carry propagating from one RCA to another RCA. R represents the outputs.

The design of 6 x 6 bits Vedic Multiplier is structurally similar to that of 12 x 12 bits Multiplier with 6 bit RCA s. The design of 6 x 6 bits Multiplier is designed using 3 x 3 Multiplier which is as shown in the Fig.B2 (b) and Fig.B2 (c) gives 3 x 3 bits Multiplication P11 P02 P10 P01 A0 B0
H A H A

P12
F A F A

P20

P22
F A F A

P21

(b)

3 x 3 Array Multiplier

A[2] A[1] A[0] X B[2] B[1] B[0]

P02 P12 P22 P21 P11 P20 R3

P01 P10

P00

PIJ[I][J]=BIAJ

R5 R4

R2

R1

R0

(c) 3 x 3 bits Multiplication Figure B2 12-bit Vedic Multiplier

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1.

Sumit Vaidya, Deepak Dandekar, Delay-Power Performance Comparison Of Multipliers In Vlsi Circuit Design, International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4, July 2010.

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M. M. Mano, Computer System Architecture. Englewood Cliffs, NJ:Prentice-Hall, 1982. GensukeGoto,High Speed Digital Parallel Multiplier, United States Patent-5,465,226, November 7 1995. 4. A.D. Booth, A Signed Binary Multiplication Technique, Qrt. J. Mech.App. Math.,, vol. 4, no. 2, pp. 236240, 1951. 5. A.D. Booth, A Signed Binary Multiplication Technique, Qrt. J. Mech.App. Math.,, vol. 4, no. 2, pp. 236240, 1951. 6. James E. Stine, Digital Computer Arithmetic Data path Design Using Verilog HDL,Kluwer Academic Publishers ,2007 3rd edition . 7. Honey DurgaTiwari, GanzorigGankhuyag,Multiplier design based on Ancient Indian Vedic Mathematics,2008 International SoC Design Conference, II-65-68. 8. Jagadguru Swami Sri Bharath, KrsnaTirathji, Vedic Mathematics or Sixteen Simple Sutras From The Vedas, MotilalBanarsidas,Varanasi(India),1986. 9. ShamimAkhter, VHDL Implementation of Fast NXN Multiplier Based on Vedic Mathematics,Jaypee Institute of Information Technology University, Noida, 201307 UP, INDIA, 2007 IEEE. 10. A.P.Godse ,D.A.Godse,Computer Organization and Architecture,Technical Publications ,2010 . 11. Steven W. Smith The Scientist and Engineer's Guide toDigital Signal Processing,California Technical PublishingSan Diego, California,1999,2nd edition. 12. Michael L. Overton ,Computer Representation of numbers,copyright @1996. 13. David Goldberg, What Every Computer Scientist Should Know about Floating point Arithmetic, published in March 1991 issues of computing surveys.

14. 15.

16.

H. Thapliyal, M. B. Srinivas and H. R. Arabnia , Design And Analysis of a VLSI Based High Performance Low Power Parallel Square Architecture, in Proc. Int. Conf. Algo. Math. Comp. Sc., Las Vegas, June 2005, pp. 7276. HimanshuThapliyal and Hamid R. Arabnia, A Time-Area- Power Efficient Multiplier andSquare Architecture Based On Ancient Indian Vedic Mathematics, Department of ComputerScience, The University of Georgia, 415 Graduate Studies Research Center Athens, Georgia30602-7404, U.S.A. www.fpga-central.com