Modeling of a three phase SPWM multilevel VSI with low THD using Matlab/Simulink

Ilhami Colak*, Ersan Kabalci**, Ramazan Bayindir*, and Gngr Bal* Gazi Electrical Machines and Energy Control (GEMEC) Group * Department of Electrical Education, Faculty of Technical Education, Gazi University, Besevler, Ankara 06500, Turkey Tel.:+90 / (312) - 202.85.38. Fax: +90 / (312) - 212.00.59. ** Department of Technical Programs, Vocational Collage of Haci Bektas, Nevsehir University, Hacibektas, Nevsehir-Turkey Tel.:+90 / (384) - 441.34.32. Fax: +90 / (384) - 441.34.41. icolak@gazi.edu.tr, ekabalci@gazi.edu.tr, bayindir@gazi.edu.tr, gbal@gazi.edu.tr

Keywords
SPWM, Multilevel Inverter (MLI), Simulink modeling, Cascaded H-bridge,

Abstract
Researches done based on basic inverter topologies show that multilevel inverters (MLIs) have many advantages, such as low power dissipation on power switches, low dv/dt ratios, low harmonic and low electromagnetic interference (EMI) outputs. The most common MLI topologies have been studied to define the most appropriate structure for Sinusoidal Pulse Width Modulation (SPWM) strategy. It is seen that cascaded H-bridges are the most convenient solution. The cascaded H-bridge cells have been constituted by IGBT semiconductors, and switched by the proposed 24-channel SPWM modulator to obtain 5-level output at the back-end of the 3-phase voltage source inverter (VSI). A modified 24 channels SPWM modulator that reduces output harmonics has been presented in this study to switch cascaded H-bridge cells of multilevel VSI. The designed multilevel VSI has a THDi ratio around at 0.1% and a strong switching bandwidth up to 40 kHz, owing to its well designed modulator. The modeling operations are also examined in Matlab/Simulink to obtain a practical solution for threephase SPWM modulator. Various design steps and configurations have been considered to model the modulator and the success of modulator has been tested under several conditions such as increased modulation indexes and switching frequencies

Introduction
MLIs have gained much attention in the field of medium voltage and high power applications due to their many advantages, such as low harmonic distortions, good electromagnetic compatibility, reduced switching losses, low voltage stress on power semiconductor and improved reliability on fault tolerance. Therefore, the MLIs also have lower dv/dt ratios to prevent induction or discharge failures on the loads. Since multi-level inverter principle of operation is based on energy conversion using small voltage steps, their output waveforms contain less harmonic distortion. Several topologies of multilevel converters have been also presented for low voltage applications. The main categories are defined as Diode Clamped Inverters, Flying Capacitor Inverters, and Cascaded Inverters. Among these, the cascaded converter can be conveniently used with a battery supply system, because it is relatively easy to split the supply in several electrically separated sources. [1]-[8]. The diode clamped inverters Total Harmonic Distortion (THD) ratio is higher than other topologies. The flying capacitor inverters are based on balancing capacitors on phase buses. Among the three types of multilevel inverters, the cascaded inverter has the least components for a given number of

levels. The cascaded MLIs consist of a series of H-bridge cells to synthesize a desired voltage from several separated DC sources (SDCSs) which may be obtained from batteries or fuel cells [9]-[10]. All these properties of cascaded inverters allow using various Pulse Width Modulation (PWM) strategies to control the inverter accurately [11]-[16]. Different types of feed-forward and feed-back PWM control schemes have been developed to control the Voltage Source Inverters (VSIs). SPWM technique is one of the most popular modulation techniques among the others such as Selective Harmonic Elimination PWM (SHE-PWM) and Third Harmonic Injection PWM (THI-PWM) applied in power switching inverters. In SPWM, a sinusoidal reference voltage waveform is compared with a triangular carrier waveform to generate driving signals for the switches of inverter [17]. The objective of this paper is to develop a well designed inverter block with mathematical model for SPWM modulator to minimize current THD ratios by using Simulink and compare to other conventional models. To achieve this, a 24-channels SPWM modulator has been designed that reduces output harmonics and used to drive cascaded H-bridge cells of multilevel VSI. The inverter output values have been discussed for various switching frequencies and modulation indexes applied to the modulator. The results obtained from simulation of Simulink show that the harmonic contents are reduced by using optimized SPWM modulator.

Design of a multilevel inverter and modulation strategies

Multilevel VSIs are widely used in AC motor drives, AC uninterruptible power supplies (UPS), and AC power supplies with batteries, fuel cells, active harmonic filters. The semi converter, half bridge and full bridge inverters were employed for high power applications in 1990s, but recently many researchers have paid much attention to MLIs for high power and medium voltage applications [1720]. The cascaded H-bridge multilevel topology is the most convenient model comparing to other topologies according to required switching devices. The main disadvantage of this topology is the requirement of separate DC sources for each H-bridge that is an advantage for applications such as renewable or alternative energy sources. The main H-bridge cell of one inverter used to implement the multilevel inverter is illustrated in Fig. 1. The full bridge inverter module includes four power switches and four clamping diodes to form an H-bridge. A multilevel inverter consists of a number of H-bridge cells that connected series per phase and each module requires a separate DC source to generate voltage levels at the output of inverter. The switching inputs shown as In1..4 in the Fig. 1 will allow obtaining output voltages of each H-bridge as follows;
+V dc V out = 0V dc V dc In 1, In 4 on In 1, In 3 on In 2, In 3 on

(1)

Fig. 1: Three-level full bridge model in Simulink

The different types of modulation methods implemented for MLIs are based on PWM techniques. Among the various control schemes, SPWM is the most commonly used control scheme for MLIs. A sinusoidal reference signal is compared to a triangular waveform to generate switching signals of inverter block in SPWM modulation technique. The sinusoidal waveform is known as modulating signal and also utilized to define line frequency at 50 or 60 Hz. The triangular waveform is generated in a high frequency according to modulating signal to be compared as carrier of modulation. The modulation technique of conventional PWM and SPWM is a process of sampling and quantification. The success of modulator is depended on eliminating harmonic contents with a specified modulation index and switching frequency conditions. The resolution of pulse width has many effects on harmonics. In a real time working system, the resolution of SPWM affects the harmonic contents of the output current mostly in low voltage and low frequency. All the PWM methods create load voltage harmonics, which produce current harmonics and additional harmonic losses. To minimize the harmonic contents of the output voltage of a cascaded inverter, the switching angle and intervals for each H-bridge inverter need to be calculated accurately. Each switching angle (Ssw(t)) of the inverter is calculated by Fourier series to eliminate selected harmonics as in Eq. 2;
S sw (t ) = a0 + (an cos(nt ) +bn sin(nt )) 2 n =1

(2)

where a0 is the average DC value of the switching signal. The Fourier coefficients a0, an, and bn are given by Eq. 3, 4 and 5:
a0 = S

sw

(t )dt

(3) (4) (5)

an =

sw

(t ) cos(nt )dt

bn =

sw

(t ) sin(n t )dt

The coefficient cn of the nth harmonic component of the signal Ssw(t) is given by (6);

cn = an + jbn

(6)

Design of the VSI proposed is based on the topology includes dual H-bridge cells per phase to generate a 5-level output voltage as shown in Fig. 1. Fig. 2 depicts proposed modulation block of VSI containing 8 modulated SPWM outputs per phase. Each phase includes dual H-bridge that is requiring 4 separate SPWM control signals as seen in Fig.1. The main topological calculations which are performed initially indicate the requirements of modulator and inverter blocks, and allow obtaining a well prepared modulation algorithm to increase the performance of inverter while decreasing the THD contents. The proposed inverter includes 6 Hbridges and 4 SPWM switching signals to control each bridge respectively. The modulation algorithm based on Eq. 3, 4 and 5 is performed in SPWM modulator to generate 24 separate SPWM pulses for H-bridges. It is difficult to accurately control the switching angles of inverter switches without these calculations, thus reducing the response speed increases harmonic contents in conventional designs.

Modeling MLI system

Most of controllers are based on the use of FFT analysis enabled processors; therefore a complex method is required to compensate errors by using iterative calculations and approximations of discrete data. The proposed inverter block which consists of dual H-bridge cells per phase as generating A, B and C voltage outputs has been modeled with IGBT semiconductors. The cascaded H-bridge cells

have been switched using a 24-channel SPWM modulator to obtain 5-level output at the back-end of the 3-phase VSI. The H-bridge cells have 3 different switching options to generate +2VDC, 0VDC and 2VDC voltage levels at the output and the switching orders form a 5-level output.

Fig. 2: The modulator block of phase A bridges The proposed VSI design is based on serially connected topology which includes dual H-bridge cells as shown in Fig. 1 per phase to generate a 5-level output voltage. The main topological calculations which are performed initially indicate the requirements of modulator and inverter blocks, and allow obtaining a well prepared modulation algorithm to increase the performance of inverter. The complete model of SPWM controlled multilevel VSI is shown in Fig. 3. The modulation index of SPWM generator is defined utilizing sinusoidal waveform generator block and the switching frequency is adjusted by modulator block that compares obtained sine waves and triangular signals inside it. The SPWM modulator model has been constituted with both sine wave

Fig. 3: Block diagram of implemented Simulink model

generator and triangular wave generator. Modulated switching signals have been applied to inverter block that contains 6 H-bridge cells as seen on the right hand side of Fig. 3.

Modeling the SPWM modulator block

The line-to-line voltage rates of inverter are determined according to modulation index (mi) that is defined as the ratio of reference sinusoidal signal to carrier triangular signal as shown in Eq. 7.The working ranges are defined as linear modulation (mi 1) or over-modulation (mi>1) ranges.

Vtri The modulator block has been modeled according to harmonic elimination concepts of SPWM technique as seen in (8) that are based on preventing the spectral errors like dead-time and on-off intervals,
mV VO (t ) = a dc cos(r t ) 2 2Vdc + J 0 k.ma 2 sin k. 2 cos(k.c t ) k =1 Jn k .ma 2Vdc 2 sin (k + l ). cos(k .c t + l.r t ) + l1 k k =1 = 2

mi =

Vref

(7)

(8)

where, ma= amplitude of modulation ratio, Vdc= dc supply voltage, r= sinusoidal reference frequency, c= triangular reference frequency, J 0 , J n = Bessel function. The output periodic voltage waveform, V0(t), consists of three major terms to eliminate possible harmonic contents in generated AC output. The first part of the equation defines modulation index while second part depicts the amplitude of the harmonics at the carrier frequency and the multiples of carrier. The last term indicates the amplitudes of the harmonics in the sidebands around each multiples of the carrier frequency. The equation has been calculated in Simulink model of modulator in each switching cycle in order to obtain the most accurate switching sequences. Fig. 4 depicts the control parameters of modulator as referring Fig.2. Fig. 4 (a) is prepared to adjust control parameters of sinusoidal waveform generator in Fig. 3. The sinusoidal parameters are defined as modulation index ratio or reference voltage by assuming the value of triangular carrier is 1 V. The switching frequency

Fig. 4: Control parameters of modulator block (a) modulation index and line frequency of modulating signal (b) switching frequency of carrier signal

of inverter block is fixed by adjusting frequency of carrier signal as shown in Fig. 4 (b). Modulating signals have been generated by sinusoidal waveform generator with 30 electrical phase difference, while carrier signals generated at the ratio of [0 1 -1 0] and intervals of [0 (1/fs)/4 (1/fs)*3/4 1/fs]

Modeling the inverter block

The power block of VSI is constituted using IGBT semiconductors. Each phase waveforms are generated with serially connected dual H-bridge cells. The SDCSs have been used to model any renewable energy source to analyze performance of VSI and the model may be evaluated according to alternative sources in future studies. The ratio of DC voltage source naturally affects the output levels of a cascade multilevel inverter. The considered full bridge module generates 3-level output voltage itself as given in Eq. 1. The Fourier series expansion of the general multilevel stepped output voltage is shown in Eq. 9 and the transform is applied for an H-bridge cell in Eq. 10, where n is the harmonic number of the output voltage of inverter.
V ( t ) = 4Vdc

4Vdc

n =1,3,5,...

[cos(n ) + cos(n
1 1

) + ... + cos( n 5 ) ]

sin( nt ) n

(9)

V ( t ) =

n =1,3,5,...

sin( nt ) [cos(n ) + cos(n )] n

2

(10)

The inverter block has been controlled with 24 switching signals that are generated in modulator block with phase difference to switch each H-bridge cells. Multilevel structure of VSI has been illustrated in Fig. 5 (a) and 5-level line-to-line output voltage of inverter obtained at 1 kHz switching frequency has been seen in Fig. 5(b).

(a)

(b) Fig. 5: Multilevel inverter (a) block diagram of H-bridges (b) 5-level line-to-line output voltage of inverter obtained at 1 kHz switching frequency

The design parameters were as follows; DC Voltage (VDC) =300V Modulation Index (mi) =0.6< mi<1.4 Switching frequency (fsw) =1 kHz<fsw<10 kHz Load Resistance (RL) =5 Load Inductance (L) =5 mH

Simulation Results
The line-to-line voltages are limited to ( 3Vd 2 ) of DC voltage in linear modulation range and to (4/).( 3Vd 2 ) in over- modulation range. The SPWM modulator has switching bandwidth between 040 kHz to control H-bridges. Fig. 6 shows the current analysis obtained at 5 kHz switching conditions while mi= 1. The increased switching frequency has allowed minimizing current THD (THDi) by carrying the harmonic contents to higher frequencies. Fig. 6 represents the FFT analysis of THDi obtained in Simulink. The switching frequency of SPWM modulator has been limited to 1-10 kHz, and modulation indexes are selected in 0.6 mi 1.4 ranges to analyze the effect of fsw and mi on THD of inverter. It has been observed by the performed tests that reducing the THD of current and voltage depends on increasing the switching frequency in linear modulation range as shown in Fig.8. The lowest THD for current has been measured as 0.1% during 10 kHz switching frequency and mi= 0.8 conditions. The THD for voltage has been measured as 0.66% under same conditions. The mathematical model of SPWM modulator has been developed in Simulink and the success on harmonic reduction has been compared to the conventional models given in references [4],[5],[10],[11],[14],[21]-[22].

(a) (b) Fig. 6: THD analysis of the proposed model (a) Current THD of inverter is 1.34% of inverter while fsw= 5 kHz (b) Voltage THD of inverter is 23.60% Fig. 7 shows the lowest and the highest harmonic contents while modulation index was defined as 1. The lowest current harmonic has been measured as 0.73% for 10 kHz switching frequency and the highest harmonic has been seen as 9.80% for 1 kHz switching frequency. The harmonic ratios have been increased independently on modulation index in over-modulation range. Fig. 8 shows the analysis results of current THD for various modulation index and switching frequency conditions. The most appropriate mi value has been determined as 0.8 according to all switching frequencies. The higher switching frequency has also provided to eliminate triplen

(a)

(b)

Fig. 7: THD current analysis while mi=1 (a) THD for current is 0.00% at 10 KHz switching frequency (b) THD for current is 9.81 % at 1 KHz switching frequency harmonics in the output current and voltage. The triplen harmonics have been completely eliminated at the switching frequencies over 2 kHz, while the current values were lower than 1% in 1 kHz switching states. The harmonic contents have been increased rapidly in the over-modulation due to modulating signal exceeds the carrier triangular waveform. The modulator cannot compare the modulating and carrier signal properly in this case and spectral errors such dead-time and on-off intervals dominate the SPWM control signal. The highest increment of THD has been seen in the 1.2 value of mi.

Fig. 8: Current THD analysis of inverter at various switching frequencies and modulation indexes

Conclusion
In this paper, a three-phase 5-level cascaded multilevel inverter with SPWM control has been modeled, achieving output signals with high quality and very low THD owing to robustly designed

mathematical model of modulator using Matlab/Simulink. The DC level of H-bridges has been intended to construct output levels and dual DC supply at each phases have been constituted 5-level output voltage as order of +2VDC, 0 VDC and -2VDC. The success of proposed model has been tested and compared with its precedent conventional models for THD rates and switching bandwidth. The switching bandwidth has been increased up to 40 kHz using modeled SPWM control block. The harmonic contents have been eliminated easily owing to appropriate timing conditions of modulator block. The switching bandwidth between 5-10 kHz was enough to prevent the most effective harmonic orders from fundamental to 50th. The THD of line voltages were 94.43% at 1 kHz switching frequency, 23.36% at 5 kHz switching frequency, and 1.35% at 10 kHz switching frequency while modulation index was 1. The measurement results have presented serious outcomes on THD elimination. It has been realized that reducing the THD of current and voltage is depended on increasing the switching frequency in linear modulation range. The modulation indexes in over modulation range have caused non linear changes in THD values of output current and voltages but on the other hand, the THD of output current and voltages have seen less than 5% in linear modulation range according to IEEE 519-1992 [23]. It is also seen that the switching frequency is directly effective on THD. The increment in switching frequency has showed its reducer effect on THD of output current and voltages. In addition, the measured harmonic contents have seen as fundamental (50 Hz, 1st), 96th and 98th harmonics in 5 kHz and 10 kHz switching conditions of linear modulation area (mi1). The harmonic contents of current, which have measured by using the modulation at 2 kHz and over, have seen as lower order harmonics and the magnitudes of harmonic have measured lower than 0.2 A. The THD of output voltage has been measured lower than 24% in linear modulation band, and the most effective harmonic contents except fundamental wave have seen at 96th and 98th as in analysis of output current.

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