CONVERSION DECO

ASIC DESIGN

Project Supervisor
Mr. Fahad Islam
Members
Anum Zaheer Khan (EE-11)
Arooj Kanwal (EE-13)
Department
Electrical VII B
January 25, 2011

ACKNOWLEDGEMENT
We are deeply thankful to All Mighty ALLAH for giving us
strength and courage to commence this project.
We are grateful to our instructor and Project supervisor Mr.
Fahad Islam for allowing us to work on this project and with his
incessant guidance and motivation we are able to complete this
task.
Furthermore we have to thank all our colleagues and friends who
always came up with useful ideas whenever we got trapped.
In last but not least thanks to the members of the group for there
selfless-effort and hard work.

DEDICATION
Dedicated to our parents and teachers for their gifts of
Time Wisdom Guidance & Heart

TABLE OF CONTENTS
Abstract
Statement of Purpose
Introduction
Scope

..

Objective

Final schematic diagram

...

Code.

9
10

Test bench and Simulation Results

ABSTRACT

12

The report to be discussed here is about Design and Construction

of Conversion Decoder. It is a binary-hexadecimal, binarydecimal, hexadecimal-decimal and hexadecimal-binary based
system convertor.
This project report is brief and consists of maximum 10 pages
which show that it is not complicated but is very comprehensive.
The project we have made provides basic information about the
software XILINX to understand the working of the commands and
tools. The purpose of this project is to make ourselves capable to
use this XILINX software very efficiently and effectively.
To ensure the successful completion of the project, the task as a
whole had been broken up into various sub-tasks. These sub-tasks
were chosen after evaluating the problem and finding crucial
steps that could be followed to completion.

STATEMENT OF PURPOSE

The statement of the project is to perform 4 types of conversion

via 4-to-16 bit Decoder.

INTRODUCTION

"Coversion Deco" is basically a 4-to-16 bits decoder. In this a 4 bit

digits input and displaying it on 7 segment display.

SCOPE
The scope of this project is to discuss and analyze the
working and processing of the XILINX Softwares tools.

OBJECTIVE

The learning objectives for this project are:

1

2
3

4
5

An introduction to concepts of XILINX Software.

Fuction of decoder.
Basic concepts of design and experience developing a simple
program to a complex project.
Develop troubleshooting skills.
Provide a tool for the student to use for the remainder of their
education.

FINAL SCHEMATIC DIAGRAM

CODE
module
decoder(out,out2,out3,out4,in,clk,en
1,en2,en3,en4);
output reg [8:0]out=9'b000000000;
output reg
[9:0]out2=10'b0000000000;
output reg
[10:0]out3=11'b00000000000;
output reg
[11:0]out4=12'b0000000000000;
input [3:0]in;
input clk,en1,en2,en3,en4;
always@(posedge clk)
begin
if(en1==1) ///binary to decimal
begin
case(in)
4'b0000: out=9'b100111111;//0
4'b0001: out=9'b100000110;//1
4'b0010: out=9'b101011011;//2
4'b0011: out=9'b101001111;//3
4'b0100: out=9'b101100110;//4
4'b0101: out=9'b101101101;//5
4'b0110: out=9'b101111101;//6
4'b0111: out=9'b100000111;//7
4'b1000: out=9'b101111111;//8
4'b1001: out=9'b101101111;//9
endcase
end
/////binary to hex
else if(en2==1)
begin
case(in)
4'b0000: out=9'b100111111;//0
4'b0001: out=9'b100000110;//1
4'b0010: out=9'b101011011;//2
4'b0011: out=9'b101001111;//3
4'b0100: out=9'b101100110;//4
4'b0101: out=9'b101101101;//5
4'b0110: out=9'b101111101;//6
4'b0111: out=9'b100000111;//7
4'b1000: out=9'b101111111;//8
4'b1001: out=9'b101101111;//9
4'b1010: out=9'b101110111;//A
4'b1011: out=9'b101111111;//B
4'b1100: out=9'b100111001;//C
4'b1101: out=9'b100111111;//D
4'b1110: out=9'b101111001;//E
4'b1111: out=9'b101110001;//F
endcase
end
//hex to decimal
else if(en3==1)
begin
case(in)
4'b0000: out=9'b100111111;//0
4'b0001: out=9'b100000110;//1
4'b0010: out=9'b101011011;//2
4'b0011: out=9'b101001111;//3
4'b0100: out=9'b101100110;//4

4'b0101: out=9'b101101101;//5
4'b0110: out=9'b101111101;//6
4'b0111: out=9'b100000111;//7
4'b1000: out=9'b101111111;//8
4'b001: out=9'b101101111;//9
4'b1010:
begin
out=9'b100000110;
out2=10'b100111111;
end//A to 10
4'b1011:
begin
out=9'b100000110;
out2=10'b1100000110;
end//B to 11
4'b1100:
begin
out=9'b100000110;
out2=10'b1101011011;
end//C to 12
4'b1101:
begin
out=9'b100000110;
out2=10'b1101001111;
end//D to 13
4'b1110:
begin
out=9'b100000110;
out2=10'b1101100110;
end//E to 14
4'b1111:
begin
out=9'b100000110;
out2=10'b1101101101;
end//F to 15
endcase
end
//always@(en4)
// hex to binary
else if(en4==1)
begin
case(in)
4'b0000:
begin
out=9'b100111111;//0
out2=10'b1100111111;//0
out3=11'b11100111111;//0
out4=12'b111100111111;//0
end
4'b0001:
begin
out=9'b100111111;//0
out2=10'b1100111111;//0
out3=11'b11100111111;//0
out4=12'b111100000110;//1

end
4'b0010:
begin

10

out=9'b100111111;//0
out2=10'b1100111111;//0
out3=11'b11100000110;//1
out4=12'b111100111111;//0
out=9'b100000110;//1
out2=10'b1100111111;//0
out3=11'b11100111111;//0
out4=12'b111100000110;//1
end
4'b1010:
begin
out=9'b100000110;//0
out2=10'b1100000110;//1
out3=11'b11100000110;//1
out4=12'b111100111111;//0
end
4'b1011:
begin
out=9'b100000110;//1
out2=10'b1100111111;//0
out3=11'b11100000110;//1
out4=12'b111100000110;//1
end
4'b1100:
begin
out=9'b100000110;//1
out2=10'b1100000110;//1
out3=11'b11100111111;//0
out4=12'b111100111111;//0
end
4'b1101:
begin
out=9'b100000110;//1
out2=10'b1100000110;//1
out3=11'b11100111111;//0
out4=12'b111100000110;//1
end
4'b1110:
begin
out=9'b100000110;//1
out2=10'b1100000110;//1
out3=11'b11100000110;//1
out4=12'b111100111111;//0
end
4'b1111:
begin
out=9'b100000110;//1
out2=10'b1100000110;//1
out3=11'b11100000110;//1
out4=12'b111100000110;//1
end
endcase
end
end
endmodule

end
4'b0011:
begin
out=9'b100111111;//0
out2=10'b1100111111;//0
out3=11'b11100000110;//1
out4=12'b111100000110;//1
end
4'b0100:
begin
out=9'b100111111;//0
out2=10'b1100000110;//1
out3=11'b11100111111;//0
out4=12'b111100111111;//0
end
4'b0101:
begin
out=9'b100111111;//0
out2=10'b1100000110;//1
out3=11'b11100111111;//0
out4=12'b111100000110;//1
end
4'b0110:
begin
out=9'b100111111;//0
out2=10'b1100000110;//1
out3=11'b11100000110;//1
out4=12'b111100111111;//0
end
4'b0111:
begin
out=9'b100111111;//0
out2=10'b1100000110;//1
out3=11'b11100000110;//1
out4=12'b111100000110;//1
end
4'b1000:
begin
out=9'b100000110;//1
out2=10'b1100111111;//0
out3=11'b11100111111;//0
out4=12'b111100111111;//0
end
4'b1001:

begin

11

TEST BENCH
module
decoder_decdertt_v_tf();
reg [3:0] in;
reg clk;
reg en1;
reg en2;
reg en3;
reg en4;
wire [8:0] out;
wire [9:0] out2;
wire [10:0] out3;
wire [11:0] out4;
decoder uut
(out,out2,out3,out4,in,clk,e
n1,en2,en3,en4);
initial begin
in = 4'b0000;
clk = 0;

begin
#25 in =
4'b0000;
#25 in =
4'b0001;
#25 in =
4'b0010;
#25 in =
4'b0011;
#25 in =
4'b0100;
#25 in =
4'b0101;
#25 in =
4'b0110;
#25 in =
4'b0111;
#25 in =
4'b1000;
#25 in =

en1 = 0;
en2 = 0;
en3 = 0;
en4 = 0;
end
always
begin
#30 en1 =
~en1;
#30 en2 = ~en2;
#30 en3 = ~en3;
#30 en4 = ~en4;
end
always
#50
clk=~clk;
always

4'b1001;
#25 in =
4'b1010;
#25 in =
4'b1011;
#25 in =
4'b1100;
#25 in =
4'b1101;
#25 in =
4'b1110;
#25 in =
4'b1111;
end
endmodule

SIMULATION RESULTS

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