IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO.

8, AUGUST 2009 3153

Dual-Buck Full-Bridge Inverter With
Hysteresis Current Control
Zhilei Yao, Lan Xiao, Member, IEEE, and Yangguang Yan
AbstractThis paper presents a dual-buck full-bridge inverter
(DBFBI) to solve the shoot-through problem in conventional
bridge-type inverters and reduce the voltage stress of the power
device in the dual-buck half-bridge inverter (DBHBI). Hysteresis
current control is used in the DBFBI. All switches and diodes
operate at each half line cycle, and the freewheeling current
ows through the independent freewheeling diodes instead of the
body diodes of the switches, so the efciency can be increased
potentially. As the shoot-through problem does not exist in the
DBFBI, dead time between the switches need not be set. The input-
voltage utilization rate of the DBFBI is twice that of the DBHBI
under the same output-voltage condition, i.e., the voltage stress
of the power device in DBFBI is half that in the DBHBI. The
operating principle, stability and relative stability analyses, and
design guidelines and example are provided. Experimental results
of a 1-kVADBFBI verify the theoretical analysis. The comparisons
among other inverters and the DBFBI show that the proposed in-
verter is very promising in 220240-V
rms
output-voltage and high-
reliability applications, such as uninterruptible power supplies
and grid-connected inverters.
Index TermsBuck converter, full-bridge, half-bridge, hystere-
sis current control, inverters.
I. INTRODUCTION
F
OSSIL fuel reserve availability and environmental con-
cerns are now the driving forces behind the use of new
clean and renewable energy sources, such as photovoltaic en-
ergy, wind energy, and fuel cell, which are the input sources of
distributed generation systems [1]. Moreover, the inverter plays
an important role in distributed generation systems [1][11].
However, a shoot-through problem exists in a conventional
bridge-type voltage-source inverter [12][15], which is a major
killer of the reliability of the inverter. Dead time to block the
upper and lower devices of each phase leg has to be provided
in the voltage-source inverter. A dual-buck half-bridge inverter
Manuscript received October 23, 2008; revised April 21, 2009. First pub-
lished May 15, 2009; current version published July 24, 2009. This work
was supported in part by the Aviation Science and Technology Supporting
Foundation under Grant 05C52006, by the Jiangsu Province High-School
Science-Technology Achievement Promoting Foundation under Grant JHB06-
02, by the National Basic Research Program of China (973 Program) under
Grant 2007CB210303, and by the Natural Science Foundation of Jiangsu
Province under Grant 08KJB470004.
Z. Yao is with the Aero-Power SciTech Center, College of Automation
Engineering, Nanjing University of Aeronautics and Astronautics, Nanjing
210016, China, and also with the School of Electrical Engineering, Yancheng
Institute of Technology, Yancheng 224051, China (e-mail: nhyzl@163.com).
L. Xiao and Y. Yan are with the Aero-Power SciTech Center, College of
Automation Engineering, Nanjing University of Aeronautics and Astronau-
tics, Nanjing 210016, China (e-mail: xiaolan@nuaa.edu.cn; yangguang@nuaa.
edu.cn).
Color versions of one or more of the gures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identier 10.1109/TIE.2009.2022072
(DBHBI) [3], [16] has been proposed to solve the shoot-through
problem. However, the input-voltage utilization rate of the
DBHBI is just half that of the full-bridge inverter. When the
output voltage is 220 V
rms
, the input voltage of the DBHBI
must be about 700 V, so the voltage stresses of the switches
should be higher than 800 V, and it is difcult to select them.
In order to solve the aforementioned problems, a dual-buck
full-bridge inverter (DBFBI) with hysteresis current control is
proposed in this paper. The shoot-through problem does not
exist in the proposed inverter. The DBFBI has the same input-
voltage utilization rate as the full-bridge inverter, and thus, the
voltage stress of the power device in the DBFBI is half that in
the DBHBI. The freewheeling current ows through the inde-
pendent freewheeling diodes instead of the body diodes of the
switches, so the freewheeling diodes can be designed optimally.
Hysteresis current control [17][25] of voltage-source in-
verter offers an unsurpassed transient response in comparison
with other current controllers. Furthermore, it is easy to im-
plement and has robust current performance against load and
source parameter changes. Therefore, it is very suitable for
nonbiased current control, by which the lter inductors, the
switches, and the diodes operate at each half line cycle. Thus,
the efciency can be improved.
The operating principle is described in Section II. The
stability and relative stability of the proposed inverter are
analyzed in Section III. Design guidelines and example are
presented in Section IV. The experimental results froma 1-kVA
DBFBI conrm the theoretical analysis in Section V. Com-
parison among other inverters and the DBFBI is provided in
Section VI. Finally, concluding remarks are given in
Section VII.
II. OPERATING PRINCIPLE
Fig. 1 shows the DBFBI based upon hysteresis current
control, where u
ref
is the reference voltage, u
of
is the output
feedback voltage, i
o
is the load current, and i
L1
i
L4
are the
currents through lter inductors L
1
L
4
, respectively.
To commence with the analysis, assumptions are made as
follows.
1) All the switches and diodes are ideal.
2) All the inductors and capacitors are ideal.
3) The output voltage (u
o
) and the reference current (i
ref
)
are constant in one switching cycle.
4) The input voltage (U
in
) is larger than the maximum
output voltage.
5) L
1
= L
2
= L
3
= L
4
= L.
6) i
L1
= i
L4
and i
L2
= i
L3
.
0278-0046/$26.00 2009 IEEE
3154 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
Fig. 1. DBFBI-based hysteresis current control.
Fig. 2. Key waveforms of the DBFBI.
Fig. 2 shows the key waveforms of the DBFBI, where h is
the hysteresis band, i
Lf1
and i
Lf2
are the feedback currents of
L
1
and L
2
, and u
ds1
u
ds4
are the voltages across the drain and
source of S
1
S
4
, respectively. There are two switching modes
at each half line cycle, and a set of corresponding equivalent
circuits is shown in Fig. 3 to aid in understanding each mode.
Fig. 3. Equivalent circuits of switching modes at i
ref
> 0. (a) Mode 1.
(b) Mode 2.
A. i
ref
> 0
As can be seen from Figs. 1 and 2, S
2
and S
3
are always
turned off at this half line cycle, and thus, i
L2
and i
L3
are equal
to zero. The voltages across L
2
and L
3
equal to zero, so u
ds2
=
u
ds3
= (U
in
+u
o
)/2, and the voltages across D
2
and D
3
are
equivalent to (U
in
u
o
)/2. S
1
and S
4
are controlled to operate
synchronously.
1) Mode 1 [i
Lf1
< i
ref
h/2] [Refer to Fig. 3(a)]: S
1
and
S
4
are gated on. The voltages across D
1
and D
4
are equal to
U
in
. The currents i
L1
and i
L4
increase linearly. In this mode
2L
di
L1
dt
= U
in
u
o
. (1)
2) Mode 2 [i
Lf1
> i
ref
+h/2] [Refer to Fig. 3(b)]: S
1
and
S
4
are gated off, and D
1
and D
4
are forward biased, so u
ds1
and
u
ds4
are equal to U
in
. The currents i
L1
and i
L4
decay linearly.
In this mode
2L
di
L1
dt
= U
in
u
o
. (2)
The relationship of u
o
with U
in
can be obtained by using (1)
and (2)
u
o
= (2d
1
1)U
in
(3)
where d
1
is the duty ratio of S
1
. However, the relationship of
the output voltage and the input voltage in the DBHBI [16] is
u
o
= (2d
1
1)U
in
/2. (4)
YAO et al.: DUAL-BUCK FULL-BRIDGE INVERTER WITH HYSTERESIS CURRENT CONTROL 3155
Therefore, the input-voltage utilization rate in the DBFBI
doubles that in the DBHBI under the same output-voltage
condition, i.e., the voltage stress of the power device in the
DBFBI is half that in the DBHBI.
B. i
ref
< 0
The operating principle at this half line cycle is similar to that
at i
ref
> 0.
III. STABILITY AND RELATIVE STABILITY ANALYSES
A. Stability Analysis
According to Section II, L
1
and L
4
operate synchronously, so
the two lter inductors can be simplied to one lter inductor.
In addition, L
2
and L
3
can also be equivalent to one lter
inductor. Therefore, the system can be reduced to a third-
order system from a fth-order system. On the other hand,
L
1
and L
2
function asynchronously, i.e., only one of the two
inductors operates with the lter capacitor C
f
at any time.
Thus, the system is further decreased to a second-order system,
and the large-signal model can be deduced, similar to the buck
converter. The small-signal transfer function could be derived
from the large-signal model.
1) i
ref
> 0: According to the state-space averaging method
[26] and Section II, the averaged state-space equation can be
derived as
2L
di
L1
dt
=(2d
1
1)U
in
u
o
(5)
C
f
du
o
dt
=i
L1

u
o
R
L
. (6)
In hysteresis current control, the average value of i
Lf1
is
controlled tightly by the reference current, so it can be as-
sumed that the average inductor current equals i
ref
(t)/K
1
[17], [18], i.e.,
i
L1
(t) = i
ref
(t)/K
1
(7)
where K
1
is the feedback coefcient of the lter inductor
current.
By substituting (7) into (6), the large-signal model of the
proposed inverter can be expressed as
C
f
du
o
dt
+
u
o
R
L
= i
ref
(t)/K
1
. (8)
Equation (8) shows that, under hysteresis current control, the
proposed inverter becomes a rst-order linear system, and the
output voltage is independent of the input voltage. Therefore,
the large-signal model of the DBFBI at i
ref
> 0 can be ob-
tained, as shown in Fig. 4.
2) i
ref
< 0: A similar conclusion can also be gained at
i
ref
< 0, so the large-signal model of the whole inverter is
shown as Fig. 5, where R
L
is the load and i
L
is the sum of
i
L1
and i
L2
.
Fig. 4. Large-signal model of the DBFBI at i
ref
> 0.
Fig. 5. Large-signal model of the proposed inverter.
Fig. 6. Small-signal control block diagram.
The small-signal transfer function can be derived from (8) as
u
o
(s) =
R
L
i
ref
(s)
(1 +sR
L
C
f
)K
1
. (9)
According to Fig. 1 and (9), the small-signal control block
diagram of the proposed inverter can be shown as Fig. 6, where
K
2
is the feedback coefcient of the output voltage, and G
o
(s)
is the transfer function of the load and the lter capacitor
impedance of the proposed inverter.
At no load, the closed-loop transfer function

(s) can be
derived from Fig. 6
G
o
(s) =
1
C
f
s
(10)

(s) =
K
P
s +K
I
K
1
C
f
s
2
+K
P
K
2
s +K
I
K
2
(11)
where K
I
and K
P
represent the integral and proportional
coefcients of the output-voltage regulator, respectively.
At load condition, G
o
(s) and
Z
(s) can be calculated as
G
o
(s) =
Z(s)
1 +C
f
Z(s)s
(12)

Z
(s) =
K
P
s +K
I
K
1
C
f
s
2
+
_
K
P
K
2
+
K
1
Z(s)
_
s +K
I
K
2
(13)
where Z(s) is the transfer function of the load impedance of the
proposed inverter.
It can be seen from (11) and (13) that the closed-loop
transfer function of the proposed inverter is stable, according
to conventional control theory.
3156 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
B. Relative Stability Analysis
The relative stability of the system is often judged by the
phase margin for the rst- and second-order systems. Re-
sistive load is taken as an example to analyze the relative
stability.
The open-loop transfer function of the proposed inverter can
be gained as
G(s)H(s) =
_
K
P
+
K
I
s
_
G
o
(s)K
2
/K
1
. (14)
The parameters are as follows: K
1
= 0.6, K
2
= 0.0125,
R
L
= 48.4 , and C
f
= 4.4 F (which will be designed in
the next section). The phase margin should be larger than 76

so that the output voltage has no overshoot when the inverter

is turned on or has a sudden load change [27]. Therefore,
the parameters of the output voltage regulator are designed
as follows: K
P
= 5.1 and K
I
= 30 000. By substituting (10)
and (12) into (14), the phase margin can be gained as 76.7

at no load and 83.6

at full load. Both of them are larger

than 76

.
IV. DESIGN GUIDELINES AND EXAMPLE
In this section, a design procedure and an example to deter-
mine the component values of the proposed inverter are given.
A. Specications
The output voltage of the proposed inverter is 220 V
rms
with
50 Hz, and the inverter is designed to provide 1000 VA.
B. Selecting the Input Voltage
The voltage U
in
must be larger than the maximum output
voltage. Under such a condition, U
in
is selected as 360 V, which
is provided by the front-end dcdc converter.
C. Switching Frequency Range
The instantaneous switching frequency can be deduced from
(1) and (2)
f
s
=
U
2
in
u
2
o
4Lh

U
in
(15)
where h

= h/K
1
.
According to (15), the maximum and minimum switching
frequencies happen at u
o
= 0 and u
o
=

2U
o
, respectively,
which are given by
f
s max
=
U
in
4Lh

(16)
f
s min
=
U
2
in
2U
2
o
4Lh

U
in
(17)
where U
o
is the root mean square (rms) of the output voltage.
Fig. 7. Variation of the switching frequency with time.
The average switching frequency can be obtained as
f
sav
=
U
2
in
U
2
o
4Lh

U
in
. (18)
The maximum switching frequency f
s max
cannot be too
large; otherwise, a large switching loss may break the switches.
As MOSFETs are adopted as the switches, f
s max
is opted for
75 kHz.
D. Hysteresis-Band Selection
As can be seen from (16), when U
in
and f
s max
are xed
on, h

cannot be too small; if not, the lter inductor value will

be large. It cannot also be too large, or else, the ripple current
will be large, and thus, the losses of the switches, diodes, and
lter inductors will be high, and the tracking accuracy will be
reduced with i
ref
. In this way, h

is chosen to be 50% of the

rated load current, i.e.,
h

=
0.5S
o
U
o
=
0.5 1000
220
= 2.27 A (19)
where S
o
is the apparent power of the inverter. Therefore, h

is
chosen as 2.3 A.
E. Filter Inductor Design
When U
in
, f
s max
, and h

are xed on, the lter inductance

can be calculated as
L =
U
in
4h

f
s max
=
360
4 2.3 75 10
3
= 521.74 H. (20)
Thus, the lter inductor value is selected as 530 H.
Fig. 7 shows the variation of instantaneous switching fre-
quency with time. As shown in Fig. 7, f
s max
is 73.83 kHz. By
using (17) and (18), f
s min
and f
sav
can be calculated as 18.69
and 46.26 kHz, respectively.
F. Filter Capacitor Design
The lter capacitor is designed by the corner frequency of
the LC lter, which should be larger by 1020 times of f
o
and
lower by 1/201/10 of f
sav
[28], so the corner frequency of the
LC lter should be higher than 500 Hz and lower than 4.6 kHz.
YAO et al.: DUAL-BUCK FULL-BRIDGE INVERTER WITH HYSTERESIS CURRENT CONTROL 3157
Halfway in between is 2.55 kHz as the corner frequency of the
LC lter. The lter capacitance can be calculated as
C
f
=
1
2(2f)
2
L
=
1
2(23.142550)
2
53010
6
= 3.68 F. (21)
Thus, the lter capacitor is chosen to be two 2.2-F
250-VAC capacitors connected in parallel.
G. Selection of the MOSFET
Based on the analysis in Section II, the peak current through
the MOSFET can be estimated as
I
Sp
=I
Lp
=

2
_
S
o
U
o
_
2
+ 2(C
f
U
o
)
2
=

2
_
1000
220
_
2
+ 2 (314 4.4 10
6
220)
2
=6.428 A (22)
where I
Lp
is the peak current through the lter inductor.
The rms switch current can be expressed as
I
srms
=

_
1
T
T/2
_
0
(i
s1
(t))
2
dt =

_
1
T
T/2
_
0
(d
1
i
L1
(t))
2
dt

I
Lp

2
_
1
8
+
M
2
32
+
(M cos )
2
16
+
2M cos
3
(23)
where M is equal to

2U
o
/U
in
and cos is the displacement
factor. Therefore, the maximum value of I
srms
is calculated as
2.802 A.
The voltage stress of the MOSFET is
U
Sp
= U
in
= 360 V. (24)
An International Rectier IRFP460 power MOSFET was
used in the proposed inverter. The power MOSFET has a
drainsource breakdown voltage of 500 V, maximum continu-
ous drain currents of 20 A at the case temperature T
C
= 25

C
and 13 A at T
C
= 100

C, and a maximum reverse recovery
time of the body diode of 860 ns.
H. Selection of the Freewheeling Diode
The average current through the freewheeling diode can be
expressed as
I
dav
=
1
T
T/2
_
0
|i
d1
(t)| dt =
I
Lp
2
_
1

M cos
4
_
. (25)
Therefore, the maximum value of I
dav
is chosen as 0.329 A.
Fig. 8. Experimental results at resistive load. (a) Full load. (b) No load to
full load.
The voltage stress of the freewheeling diode is
U
Dp
= U
in
= 360 V. (26)
A fast recovery epitaxial diode DSEI8-06A was adopted. The
diode has a breakdown voltage of 600 V, a current rating of 8 A,
and a maximum reverse recovery time of 50 ns, which is
far less than the reverse recovery time of the body diode
of the MOSFET. Therefore, the reverse recovery loss can be
reduced.
V. EXPERIMENTAL RESULTS
A 1-kVA DBFBI has been constructed to verify the theoreti-
cal analysis with the parameters shown in Section IV.
Fig. 8(a) shows the experimental results at full resistive load.
It can be seen from Fig. 8(a) that the switches and the lter
inductors operate at each half line cycle. The total harmonic
distortion (THD) of the output voltage is 1.7%. The experimen-
tal results from no load to full load are shown in Fig. 8(b). As
can be seen from Fig. 8(b), the output voltage has no overshoot
during the load change.
Fig. 9(a) shows the experimental results at full rectier load.
The THD of the output voltage is 2.7%, so the waveform
3158 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
Fig. 9. Experimental results at rectier load. (a) Full load. (b) No load to full
load.
quality of the output voltage is also good at nonlinear load.
The experimental results from no load to full load are shown
in Fig. 9(b). As can be seen from Fig. 9(b), the output voltage
has no overshoot during the load change.
Fig. 10 shows the switching frequency range of the proposed
inverter at full resistive load. From Fig. 10, when u
o
=

2U
o
,
f
s min
is 17.86 kHz, which very approximates to the calculated
value. When u
o
= 0, f
s max
is 40 kHz. The main reason why
f
s max
has a considerable difference with the calculated value
is that, when u
o
equals zero, the lower limit of the reference
current (i
ref
h/2) is negative, but i
L1
cannot go negative.
When i
L1
decreases to zero, the lter inductors and the output
capacitors of the switches begin to become resonant, and the
time reaching to the lower limit of the reference current is
longer than calculated value. Therefore, the efciency can be
improved with the lower maximum switching frequency.
Fig. 11 shows the efciency of the proposed inverter at
resistive load. The efciency is high from light load to full
load, and the efciency is 98.85% at full resistive load. The
main reasons for the high efciency are as follows: 1) All
switches, diodes, and lter inductors operate at each half line
cycle, so the switching loss is low; 2) the load current is in
phase with the output voltage at resistive load, and the switching
frequency reduces with the increase in the absolute value of the
Fig. 10. Switching frequency range at full resistive load. (a) u
o
=

2U
o
.
(b) u
o
= 0.
Fig. 11. Efciency of the proposed inverter at resistive load.
output voltage, so the switching loss is low; and 3) according
to Section IV, the reverse recovery loss of the independent
freewheeling diodes is lower than that of the body diodes of
the switches.
VI. COMPARISON AMONG OTHER INVERTERS AND DBFBI
In this section, the DBFBI and other inverters are compared
with the parameters shown in Section IV.
YAO et al.: DUAL-BUCK FULL-BRIDGE INVERTER WITH HYSTERESIS CURRENT CONTROL 3159
TABLE I
COMPARISON AMONG OTHER INVERTERS AND DBFBI
A. Total SDP Comparison
In an inverter system, the total switching device power
(SDP) is a measure of the total semiconductor device require-
ment, which is thus an important cost indicator of an inverter
system [29].
Based upon the aforementioned analysis and the design
guidelines in Section IV, the component comparison among the
proposed inverter and other inverters is illustrated in Table I. As
shown by Table I, the total SDP of the DBHBI is equal to that
of the proposed inverter in average and rms values, respectively.
However, the voltage stress of the switches in the DBHBI is
720 V, so the switches in the DBHBI are very difcult to
choose, and thus, the DBHBI is just suitable for the following
applications: aeronautical power supply, uninterruptible power
supply (UPS), and grid-connected inverter, whose output volt-
ages are within the range of 110127 V
rms
. Under the 220-V
rms
output-voltage condition, although the number of switches and
freewheeling diodes in the proposed inverter doubles that in the
DBHBI, their voltage stress in the DBFBI is only half that in
the DBHBI, i.e., 360 V, so it is easy to select the switches.
In addition, the total SDP of the DBFBI is a little less than
that of the full-bridge inverter, and the voltage stress of the
switches in the DBFBI is the same as that in the full-bridge
inverter. Although the proposed inverter has four independent
freewheeling diodes more than the full-bridge inverter, the
shoot-through problem, which is sometimes the main killer
of the reliability of the full-bridge inverter, does not exist in
the DBFBI. Consequently, the DBFBI may be used in high-
reliability applications. Moreover, the freewheeling current
does not ow through the body diodes of the switches in the
DBFBI, and the independent freewheeling diodes with lower
reverse recovery time, as shown in Section IV, can be selected
to reduce the reverse recovery loss in the DBFBI.
B. Requirement of Passive Component Comparison
Passive components, namely, inductors and capacitors, are
also important parts in determining the inverter cost and vol-
ume. The lter inductors and the lter capacitor can be calcu-
lated by Section IV. The passive component comparison among
the DBFBI and other inverters is described in Table I. As can be
seen from Table I, the number of lter inductors in the proposed
inverter is two times that in the DBHBI, but the value of lter
inductors in the DBFBI is half that in the DBHBI. Thus, the
required lter inductors in the proposed inverter are almost
similar to that in the DBHBI. The lter capacitor in the DBFBI
is as good as that in the DBHBI. Furthermore, the input-divided
capacitors, which play a large part in the volume of the inverter,
do not exist in the DBFBI.
Moreover, the number of lter inductors in the proposed
inverter is four times that in the full-bridge inverter, but the
value and average absolute current of the lter inductors in the
DBFBI are half that in the full-bridge inverter. The rms current
of lter inductors in the full-bridge inverter is

2 times that in
the DBFBI. Thus, the required lter inductors in the proposed
inverter are a little larger than that in the full-bridge inverter.
The lter capacitor in the DBFBI is the same as that in the full-
bridge inverter.
From the aforementioned analysis, the comparisons show
that the proposed inverter is very promising in 220240-V
rms
output-voltage and high-reliability applications, such as UPS
and grid-connected inverters.
VII. CONCLUSION
This paper has proposed a DBFBI topology. A 1-kVA
DBFBI has been built to verify the theoretical analysis. The
proposed inverter has the following characteristics.
1) In contrast to the DBHBI, the input-voltage utilization
rate doubles, and the voltage stress of the power device
is half that in the DBHBI at the same output voltage.
2) Compared with the DBHBI, the input-divided capacitors
do not exist in the DBFBI.
3) In comparison with the full-bridge inverter, the shoot-
through problem does not exist.
4) Compared to the full-bridge inverter, the freewheel-
ing current ows through the independent freewheeling
diodes instead of the body diodes of the switches, so the
efciency can be increased potentially.
5) All switches, diodes, and lter inductors operate at each
half line cycle, so the efciency can be improved.
The comparisons among other inverters and the DBFBI
demonstrated that the proposed inverter is more attractive
than other inverters in 220240-V
rms
output-voltage and
high-reliability applications, such as UPS and grid-connected
inverters.
3160 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 56, NO. 8, AUGUST 2009
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Zhilei Yao was born in Jiangsu, China, in 1981.
He received the B.S. and M.S. degrees in electrical
engineering from Nanjing University of Aeronautics
and Astronautics, Nanjing, China, in 2003 and 2006,
respectively, where he is currently working toward
the Ph.D. degree in electrical engineering at the
Aero-Power SciTech Center, College of Automa-
tion Engineering.
He is also with the School of Electrical Engineer-
ing, Yancheng Institute of Technology, Yancheng,
China. He is the holder of three patents, and he is
the author or coauthor of more than 20 technical papers. His current research
interests include dcdc converters, inverters, and distributed power generation.
Lan Xiao (M06) was born in Zhejiang, China,
in 1971. She received the B.S. and Ph.D. degrees
in electrical engineering from Nanjing University
of Aeronautics and Astronautics (NUAA), Nanjing,
China, in 1993 and 1998, respectively.
In 1999, she joined the faculty of the College
of Automation Engineering, NUAA, where she is
currently a Professor with the Aero-Power SciTech
Center. She is the author or coauthor of over 50 tech-
nical papers in journals and conferences. Her current
research interests include soft-switching dc/dc con-
verters, soft-switching inverters, and renewable energy generation systems.
Yangguang Yan was born in Zhejiang, China, in
1935. He received the B.S. degree in electrical
engineering from Nanjing Aeronautical Institute,
Nanjing, China, in 1958.
He is currently a Professor with the College
of Automation Engineering, Nanjing University of
Aeronautics and Astronautics, Nanjing, and he is
the Founder of the Aero-Power SciTech Center,
College of Automation Engineering, a national en-
gineering research center in China. He is the au-
thor or coauthor of over 100 technical papers and
three books. His current research interests include aeronautical power supply
systems and secondary power supplies for aircraft.