B.E. 7th Semester (E.C.E.

)
VLSI Design
NOTE:-Attempt any five questions in all by selecting at least two from each part.. [Max. Marks: 100]

PART-A

Q1. (a) How NMOS fabrication process is done with the help of diagrams
explain the various steps. (10) (b) How the enhancement mode of transistor works for Vgs>Vt & Vds=0V, Vgs>vt & Vds<Vgs-Vt & Vgs>Vt & Vgs-Vt. with the help of sketch diagrams illustrate. (10) Q2. (a) Compare the merits of three different forms of pull up for an inverter circuit. What is the best choice for realization in NMOS & CMOS technology? (12) (b) Determine Zpu/Zpd for nMOS inverter driven by another nMOS inverter. (8) Q3. Draw the stick diagram & mask layout for an 8:1 two I/P CMOS NOR gate & inverter circuits. Both the i/p & o/p points should be on polysilicon layer. (20) Q4. (a) Consider a CMOS inverter circuit with the following parameters. VDD=3.3V , VTO,n=0.6V, VTO,P= -0.7V Kn=200 A/v2 , KP=80 A/v2. Calculate the noise margins of the circuit. The cmos inverter being considered here has KR=2.5 & VTO,n|VTO,p|. Hence it is not a symmetric inverter. (b) How the VIL & VIH are Obtained for a resistive load inverter.

PART-B
Q5. (a) Discuss the charge sharing problem in VLSI circuits. Explain various circuits techniques used in CMOS circuits for solving charge sharing problems. State as many as you know. (b) Does the inverter with lower VOL Always have the shorter high to low switching time? Justify your answer. (c) Design a scaled chain of N inverters such that the delay time b/w the logic gate & the load capacitance node minimized. Q6. (a) What are the design strategies for a test & what is the need of testing? (10) (b) Discuss some chip level testing techniques. What are the various CMOS design options? (10) Q7. Using the tanner tools & wind how the characteristics of three i/p CMOS NAND gate is obtained. (20) Q8. (a) In VLSI process, what is the role of CAD tools? (10) (b) An off chip capacitance load of 5Pf is to be driven from CMOS & nmos inverters. Set out suitable arrangements giving appropriate channel L: W ratios & dimensions. Calculate the no. of inverter stages required & the delay exhibited by the overall arrangement driving the 5Pf load. (10)

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