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Application Note AN121B Jan 30, 1998

QPSK Transmitter and Receiver Simulation using Ideal Components

by Stephen H. Kratzet

Introduction This is the first of a series of three application notes. The purpose of this note is to show how SystemView, by Elanix, may be used to simulate quadrature phase shift keying (QPSK) modulation and demodulation in a communication system with ideal components. In this application note, the following subjects or areas of design are covered:

In AN121 only the standard (core) SystemView libraries are used. In application note AN123 many of the standard library tokens will be replaced with tokens from the RF library. The parameters will be set to values representative of RF chip sets that are presently available. Also, narrower filter bandwidths with their appropriate losses will be used in the system. A Typical Quadrature Modulator and Demodulator Block Diagram An example of a digital radio transmitter and receiver system with its component layout and frequency plan is shown in Figure 1. The frequency extremes of this system are a 270.833 kHz data rate, and a 1018.5 MHz local oscillator (LO). To handle the 1018.5 MHz frequency, SystemViews sample rate would need to be about 3 to 5 times higher than the highest frequency, or around 3 GHz to 5 GHz. This would cause a huge number of samples (and simulation time) to be spent on representing the 270.833 kHz data signals. To create a useful simulation a new frequency plan was developed for use in SystemView. Closer Spaced Frequencies for Faster Simulation In Figure 2 the frequencies of each stage have been set to be closer to each other, while keeping the original 270.833 kHz data frequency. This will allow the simulation to take less time. This was done by starting at the receivers output and working towards its input. There are no absolute rules, but as shown in following items (a) through (g), the multiply factor used is between 3 and 5. (a) The demodulator and its preceding filter are set to 1.3 MHz. This is approximately 5 x 280 kHz. (b) The 2nd LO, preceding the demodulator, is set to 3.9 MHz. (3 x 1.3 MHz) (c) The frequencies in (a) and (b) cause the input filter to the receiver's 2nd mixer to be centered at 5.2 MHz. (1.3 MHz + 3.9 MHz).

The starting point is a typical block diagram for a digital radio. The transmitter has a quadrature modulator and one up-conversion stage. The receiver has two down-conversions and a quadrature demodulator. To speed up the software running time, the wide spaced frequencies (270.833 kHz to 1018.5 MHz) will be changed to closer spaced frequencies (270.833 kHz to 20.8 MHz). How to determine the sample rate that should be used in SystemView. A mixer with a gain-of-one and that has minimum spectral growth be will described. It will exhibit minimum side band harmonics in SystemView. A QPSK system will be shown using ideal parts (no saturation effects), all components will have unity gain, and use simple wide band filters for minimum signal distortion. In this system, the phase of the demodulator frequency will be set manually. A 4-phase Costas loop will be added to the demodulator to allow it to automatically lock in to the received signal. Application note AN122 baseband input processing. is previewed showing


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(d). The receiver's 1st LO is set to 15.6 MHz. (3 x 5.2 MHz) (e) The frequencies in (c) and (d) cause the receiver's input filters to be centered at 20.8 MHz. (15.6 MHz + 5.2 MHz) (f) In Figure 1, the modulators' frequency is twice that of the receivers' 2nd LO. Consequently, the new modulator frequency is set to 7.8 MHz. (2 x 3.9 MHz) (g) The frequencies in (e) and (f) cause the transmitter's LO to be 13.0 MHz. (20.8 MHz - 7.8 MHz). Determining the sample rate that should be used in SystemView The highest frequency in the system in Figure 2 is 20.8 MHz. Therefore, SystemViews' sample rate will be set to 102.4 e6 samples/sec. (~ 5 x 20.8 MHz) Even the unused sum output of the mixer, 20.8 MHz + 15.6 MHz = 36.4 MHz, meets the Nyquist requirement of sampling at a rate of at least twice the highest frequency of interest. Using 8192 samples and a sample rate of 102.4 MHz yields a frequency resolution of 12.5 kHz. When testing the gains and losses of the various elements in a system, using a round number (12.5 e3) for the frequency resolution will yield more accurate amplitude plots. A frequency resolution number such as 12.51234 e3 will cause FFT bin-splitting effects that in turn will reduce the plotted amplitude of the signals. A SystemView Mixer that has Minimum Harmonics A modulator or mixer can be made by using a multiplier token fed by a sine wave LO. Use a value of 2.0 v for the amplitude parameter in the Sinusoid Source. This will cause the mixer (multiplier) to have unity gain (0 dB) when it is followed by a single side band (SSB) filter. Additionally, the multiplier's other input can be preceded by an RF amplifier. This will cause the gain, noise figure, 1dB compression point, etc., of the mixer to be determined by the parameters of the RF amplifier. The RF amplifier will be discussed in AN123. A Quadrature Modulator and Demodulator System with Unity Gain Components and Minimum Filtering The SystemView version of the block diagram in Figure 2 is shown in Figures 3 through 8. In Figure 3, the transmitter signal flow is from digital I and Q input signals, through a pair of 10 MHz filters, into a metasystem (Figure 4) that contains the following items:

The transmitter's quadrature modulator. The transmitter upconverter. A path loss of 0 dB The receiver's 1st downconversion. The receiver's 2nd downconversion. The receiver's quadrature demodulator.

(Figure 5) (Figure 6) (Figure 7) (Figure 8) (Figure 9)

In Figure 3, the 10 MHz filters are really just place holders since they have almost no effect on the 270.833 kHz I and Q signals. The input I and Q data signals may be observed at the two sinks. The two delay tokens compensate for delays through the receiver's filters. The compensation delays produce a better looking display when the input and output plots are overlaid. The two decimate-by-16 tokens reduce the number of points plotted. The quadrature modulator (metasystem) is shown in Figure 5. The upconverter (metasystem) is shown in Figure 6. For simplicity and minimum signal distortion, 3-pole Bessel bandpass filters are used at the carrier and intermediate frequencies. A 3 dB bandwidth of 2 MHz is used for most of the filters in the simulation. Near the end of the receiver chain a 1 MHz bandwidth is used. Since this is a unity gain simulation, no amplifiers are used in the transmitter or receiver. The gain token in Figure 4 is used to simulate the path loss. Since it is set to zero dB gain, it is just a place holder in this simulation. The receiver is comprised of three metasystems, the 1st downconverter (Figure 7), 2nd downconverter (Figure 8), and the quadrature demodulator (Figure 9). At the front end of the 1st downconverter, thermal noise is added to the input signal to simulate input noise. For more information on this subject, please refer to the thermal noise section of AN110B. In Figure 8, after the 2nd down conversion, the center frequency is 1.3 MHz. This is quite low compared to the sample rate used for this simulation, 102.4 e6 samples/sec. A decimator token, set to decimate by 4, reduces the 102.4 e6 sample rate to 25.6 e6 samples/sec for tokens on the down stream side of the decimator. 25.60 e6 / 1.30 e6 = 19.7 This approximately 20:1 ratio of sample rate vs. filter frequency is a good upper operating ratio for filters in SystemView. However, the simulation will run just fine without the decimation at the 1.3 to 104.2 ratio. There is another reason for using the decimator. The next stage is a demodulator. Usually this function is done by a digital signal processor (DSP) that has a relatively low sample rate.


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Figure 1. A block diagram of a digital radio system using quadrature modulation and demodulation. Typical frequencies are shown.

Figure 2. Compared to Figure 1, this system has closer spaced frequencies to permit a faster simulation time. Also, the filters are simplified, and there are no amplifiers.
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Figure 3. The SystemView version of the block diagram in Figure 2.

Figure 4. A view inside the QTxRx1.mta metasystem reveals the quadrature transmitter and receiver systems.


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Figure 5. The quadrature modulator.

Figure 6. The transmitter's upconverter.


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Figure 7. The receiver's 1st downconverter, with input noise.

Figure 8. The receiver's 2nd downconverter.


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Quadrature Demodulator with a Fixed LO The receiver's demodulator is shown in Figure 9. The multipliers require that each of their inputs be at the same sample rate. Therefore, the LO requires a decimate-by-4 token on its I and Q outputs because of the decimation that occurred in the previous downconverter metasystem. There are a couple of 300 kHz, 2-pole, Bessel low pass filters to remove the sum term from the demodulator's I and Q outputs. To get a clean demodulated output it is necessary for the frequency and phase of the LO to be set correctly. Since the transmit and receive filters affect the phase of the signal, a trial and error method is used to determine the LO's phase parameter. Temporarily setting the Q input to a zero amplitude is helpful while searching for the best phase parameter. 4-Phase Costas Loop Demodulator A different quadrature demodulator is shown in Figure 10. It is a 4-phase Costas loop (Ref. 1). Using a voltage controlled oscillator (FM token or VCO), it locks onto the incoming signal in a manner similar to a 2-phase Costas loop or phase locked loop (PLL). As with a 2-phase Costas loop, this demodulator may lock in with the I or Q output inverted. Therefore, in the overall system it is necessary to use a known preamble sequence or differential phase encoded data signals. Notice that the decimate-by-4 tokens are not necessary in the 4-phase Costas loop. This is because SystemView automatically takes care of decimation in closed loop systems that are downstream from an earlier decimation. The hard limiters in the 4-phase Costas loop clamp the signals to +/- 1.0 Volts. The LaPlace loop filter operates as an integrating opamp PLL filter and is set as follows: Num 1 = (-8e-6)s1 + -1 Den 1 = ( 2e-6)s1 The two negatives in the numerator produce the inverting op-amp function. The ratio of the numerator and denominator s1 terms are set to produce a maximum loss of 12.04 dB. The absolute values of the two s1 terms are set to produce a gain of 0 dB at 2.05 kHz. Both of these values can be seen in the Bode plot of the LaPlace loop filter. The frequency of the VCO is 1.3013 MHz. This is a generous difference of 1000 parts per million (PPM) relative to the transmitter. An inexpensive crystal reference has an accuracy of 100 PPM. To avoid an inverted output when the loop locks in, the VCO has an 80 degree phase offset. Notice that the Rx and Tx

frequency difference of 1.30 kHz is less than the 2.05 kHz Bode plot value of the loop filter. 1.3013 MHz - 1.3000 MHz = 1.30 kHz With the values shown, the demodulator locks in when the "path loss" token is varied over the range of at least +25 dB to -25 dB. The first (fixed LO) demodulator is used in the example file QTxRx1.suv and its metasystem, QTxRx1.mta. The second (4-phase Costas loop) demodulator is used in the file QTxRx2.svu and its metasystem, QTxRx2.mta. These four example files are the same except for the demodulator metasystems. Results of the Simulation The two quadrature demodulators produce almost identical output plots. The I and Q output plots are shown in Figures 11 and 12. Notice that the I and Q outputs are twice the amplitude of the overlaid input signals, even though unity gain components are used throughout the system. This was very puzzling at first. While using SystemView's probe, the factor of 2 gain was found to occur at the output of the transmitter's modulator. As in many IC chip sets, there is no filter between the quadrature modulator and the upconverter. Remember, the model of the mixer has unity gain (0 dB) when it is followed by a single side band (SSB) filter. In this system, the upconverting mixer sees both the sum and difference output of the quadrature modulator, producing a gain of two. Figure 13 is an overlay of the I output and the I samp output. The I samp output has one sample per data bit. Since the overlay is almost perfect, a two-color plot is necessary to identify the two plots. Figure 14 is an eye diagram (Time Slice) of the Q output data. The number of system time samples has been increased to 32,768 to give more transitions in the plot. To avoid the startup glitch, the start time of the time slice is 11.0 e-6 seconds. The length of the slice is entered as: 4/270.833e3 (1.47692489467679E-05) Figure 15 is a zoomed-in view of the time plot of the transmitter's output. Figure 16 is the spectrum of the transmitter's output. To obtain the fine resolution in this plot, the number of system time samples has been set to 32,768. Figure 17 is a scatter plot of the I output vs. the Q output. The outputs spend most of their time at the four dark locations while the thin dotted traces indicate the time during signal transitions. Figure 18 is a scatter plot of the I samp output vs. the Q samp output.
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Figure 9. The receiver's quadrature demodulator, with a manually set VCO.

Figure 10. The 4-phase Costas loop used to automatically lock in on the I and Q quadrature data.


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For repeatability, a Fixed Random Seed of 12345 is used for all of the plots in this application note. Also, to avoid the startup glitches, the data plots in Figures 11, 12, and 13 are displayed using extracted data over the range of 11.0 e-6 to 78.0 e-6 seconds. The data plots in Figures 17 and 18 are displayed using extracted data over the range of 11.0 e-6 to 314.0 e-6 seconds. The example files QTxRx1.svu, QTxRx2.svu, and QTxRx3.svu, do not have the extracted data feature enabled. Time Delay Parameter Selection Four time delay tokens are used to align the waveforms in time, two in the input and two in the output path of the system. The 1st pair of delay tokens are used before the input sink tokens to compensate for the propagation delay through the system filters. The 2nd pair of delay tokens are used near the end of the receiver chain to align the output sampling points to the mid-bit position of the data bits. With all four delays set to zero, run the system. View the I in sink overlaid with the I out sink. Using the Dx,Dy plot tool, the I out plot delay measures approximately 2.6 e-6 sec. Run the system again with the 1st pair of delays set to the measured value. This time, overlay the following 2 plots with the plot connected points feature enabled: I out I samp out"

The lower cutoff frequency of the output filters require that the time delays at the input be set to 2.70 e-6 seconds. The time delays at the output are set to 0.10 e6 seconds. This input baseband processing version is saved as QTxRx3.suv. The effect of this baseband processing is shown in Figures 19 through 26. The same system rates, number of samples, and data extraction are used in Figures 19 through 26 as in the previous eight figures. Since most of the transmitted energy is contained in the center lobe, the 190 kHz filtering in the transmitter has only a small effect on the receiver's output. Productivity The time to run the QTxRx2.svu file using the 32-bit version 2.0-11 Build 001 of SystemView by ELANIX, Inc. (speed optimized) and Windows 95 is summarized below. The run times for a 166 MHz non-MMX Pentium are shown in Table 1. Run times for a 233 MHz MMX Pentium are shown in Table 2.

System samples 8,192 131,072

Data bits 21 346

SysVu Time 166 14.7 Sec. 3.9 Min.

Number of Loops 1 1

Table 1.
System samples 8,192 131,072 Data bits 21 346 SysVu Time 233 MMX 8.3 Sec. 2.3 Min. Number of Loops 1 1

Now the I in and I out plots will be aligned in time but the I out and I samp out plots are not aligned. Measure the offset time, and add this value (2.85 e-6 sec) to the initial measurement of the 1st pair of delays and to the zero value of the 2nd pair of delays. When the system is run again, all the samples will occur at the correct time. Several runs may be necessary to establish the optimum time parameters for the delays. A Preview of Baseband Input Processing In most communication systems, it is necessary to limit the bandwidth of the transmitted signal. A baseband processor, not the quadrature modulator, is responsible for filtering the I and Q input signals to achieve the narrow bandwidth. This subject will be covered in the next application note in this series, AN122. For a preview of baseband processing, do the following: In Figure 1, change both low pass filters from 10 MHz to 190 kHz. The 190 kHz value is obtained from a 0.7 factor. 270.833 kHz x 0.7 = 190 kHz

Table 2.

More Information For more information on SystemView simulation software please contact: ELANIX, Inc. 5655 Lindero Canyon Road, Suite 721, Westlake Village CA 91362. Tel: (818) 597-1414 Fax: (818) 597-1427 or visit our web home page (http://www.elanix.com) to down load an evaluation version of the software that can run this simulation as well as other user entered designs. References 1. Rob Howald, Communications Systems Design (magazine, Miller Freeman Inc.) October 1997, pages 20, 22, 24, and 26, Scary Synchronizers.


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Figure 11. I input vs. I output.

Figure 14. Eye diagram of the Q output data.

Figure 12. Q input vs. Q output.

Figure 15. Time plot of the transmitter output.

Figure 13. I output vs. I samp output.

Figure 16. Frequency plot of the transmitter output.

Figure 17. A scatter plot of the I and Q outputs.

Figure 18. A plot of the I samp and Q samp outputs.

Figures 11 through 18: 10 MHz input filters are used for minimum signal distortion.


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Figure 19. I input vs. I output.

Figure 22. Eye diagram of the Q output data.

Figure 20. Q input vs. Q output.

Figure 23. Time plot of the transmitter output.

Figure 21. I output vs. I samp output.

Figure 24. Frequency plot of the transmitter output.

Figure 25. A scatter plot of the I and Q outputs.

Figure 26. A plot of the I samp and Q samp outputs.

Figures 19 through 26: 190 kHz input filters are used for minimum RF signal bandwidth.


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