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# CMOS Digital Logic Circuits

http://fourier.eng.hmc.edu/e84/lectures/ch4/node15.html

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## CMOS Digital Logic Circuits

Either a p-channel MOSFET (pMOS or PFET) or an n-channel MOSFET (nMOS or NFET) can be treated as a switch between its drain and source controlled by the voltage between gate and source . When (e.g., ) for nMOS and (e.g., ) for pMOS, the

circuit is a short-circuit because of the low resistance between and ; otherwise, the circuit is an open-circuit due to the large resistance between and . A circuit composed of both types of MOSFET transistors is called a complementary MOS or CMOS circuit, which is widely used for digital design. When two switches are connected in series, the resulting circuit conducts only if both switches conduct, i.e., the circuit implements logic AND. On the other hand, when two switches are connected in parallel, the resulting circuit conducts if either of the two switches conducts, i.e., the circuit implements logic OR. Due to such logic properties of the series and parallel connections of the pMOS and nMOS transistors, various logic circuits can be constructed to realize a given logic function , where each of the inputs is either a low or high a voltage, representing, respectively, logic value 0 or 1.

Corresponding to each possible combination of the inputs, the output is either low or high in voltage for logic 0 or 1. In general, a logic function connected to the voltage source is realized by two complementary circuits, one pull-up circuit , and a pull-down circuit connected to ground, as shown in the figure:

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5/18/2012 9:15 PM

## CMOS Digital Logic Circuits

http://fourier.eng.hmc.edu/e84/lectures/ch4/node15.html

## When the input variables

are such that the pull-up circuit is conducting (short) and the is connected to the voltage source to output a are such that the pull-up is

## high voltage representing logic 1; however, when the input variables

circuit is cutoff (open) and the complementary pull-down circuit is conducting (short), the output connected to ground to output a low voltage representing logic 0.

Before discussing the implementation of the pull-up and pull-down circuits, recall the famous De Morgan's Law:

Here is the negation of variable . In general, the De Morgan's law states that the negation (complementary) of a given function can be found by negating the logical operations (AND, OR) as well as the variables in a function. As the simplest example, the NOT gate is implemented by a pull-up circuit composed of only a pMOS transistor and its complementary pull-down circuit composed of only a nMOS transistor, as shown below:

Logic NAND The pull-up function is , and the pull-down function is , which is indeed

the negation of the pull-up function, i.e., the output function is the same as the pull-up function, a negation of AND, or NAND. Logic NOR The pull-up function of the circuit on the right is is , and the pull-down function

, the negation of the pull-up function. The output is the same as the pull-up function

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5/18/2012 9:15 PM

## CMOS Digital Logic Circuits

http://fourier.eng.hmc.edu/e84/lectures/ch4/node15.html

## , negation of OR, or NOR.

More complicated logic functions can be similarly implemented using CMOS circuits. Example: Implement logic function First, find the complementary function : by a CMOS circuit.

## and then the CMOS circuit can be designed as shown:

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5/18/2012 9:15 PM

## CMOS Digital Logic Circuits

http://fourier.eng.hmc.edu/e84/lectures/ch4/node15.html

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