VLSI DESIGN (2 MARKS) UNIT-I MOS TRANSISTOR 1. What is meant Photolithography?

Photolithography that allows us to translate on screen computer drawings to a physical structure that replicates the patterns defined by our CAD package. 2. What is photoresist? The process starts by coating the surface of the chip with light sensitive organic polymer(i.e., plastic) called photoresist which acts similarly to ordinary photographic film. 3. Describe the process of ion implantation. The process of adding impurity atoms (arsenic) to the silicon called doping and impurities themselves called dopants.To force the dopants into the the silicon wafer, the atoms are ionized and then accelerated using ion guns. This process is called ion implanation. 4. What is defect density? Defect density describes point defects on the wafer surface and is significant because a single defect can ruin the circuitry on a die. 5. What is annealing? In the ion implanation process, the wafer is heated in a furnace to heal the damage created by the impact of the ions on the silicon crystal. This step is called annealing and is required to help the dopants set correctly into the crystal structure. 6. What are the two categories in the region of chip? Region of a chip are divided into two categories,depending upon their usage. i. active area(transistor section) ii. field region. It can be written by Active + Field = Chip surface. 7. What are the different integration levels? The different integration levels are i. SSI(Small-Scale Integration) ii. MSI(Medium-Scale Integration) iii. LSI(Large- Scale Integration) iv. VLSI(Very Large-Scale Integration) v. ULSI(Ultra Large-scale Integration) vi. GSI(Giga-Scale Integration) 8. Define yield. The yield Y of a process is defined as Y= Number of good die X 100 Total number 9. What is SSI and MSI? Small-Scale Integration(SSI) with less than about 1,000 transistors. SSI includes chips with individual logic gates. Medium-Scale Inregration(MSI) to around 100,000 transistors. An example of an MSI chip is a 4-bit arithmetic logic unit or a basic calculator. 10. What is LSI and GSI? Large-Scale Integration(LSI) to around 1,000,000 transistors. 8- and 16-bit microprocessors and basic digital signal processors are in this caregory. Giga-Scale Integration(GSI) as an alternate. 11. What is VLSI and ULSI? Very Large-scale Integration (VLSI) to around 100,000,000 transistors. This includes the current generation of microprocessors that have 40-50 million transistors. Ultra Large-Scale Integration(ULSI) with about one billion transistors,which some have coined. 12. What are the pattern layers needed for nFET masking sequence? The pattern layers needed for nFET masking sequence are i. Active. ii. Poly. iii. n-implant. 13. What are the pattern layers needed for pFET masking sequence?

The pattern layers needed for nFET masking sequence are i. n- well ii. Active iii. Poly iv. p- implant. 14.Where we introduce length metric lambda? Scalable design rules that allow us to construct layouts that can be moved from one process to another by a simple procedure. To achieve this, we introduce a length metric lambda,in units of lambda. 15. Define design rule check(DRC). Design rules must be followed at all times during the mask design procedure. A routine called the design rule check is provided in the layout editor to help find DR violations that may have been missed. 16. What are the sequences we used to create the pattern? The sequences are iv. Design the pattern on a computer. v. Create a mask or reticle. vi. Print the pattern onto the surface of the chip. vii. Use the printed region to define the material pattern. 17. Describe the term reticle. Reticle consists of a high quality piece of glass with a chromium metal replica of the pattern on one side. In photolithography , the reticle is optically transparent except in those regions where the chromium metal regions exist,the reticle is opaque and any incident light is reflected by the metal. 18. What is the use of passivation mask? In CMOS fabrication,the passivation mask is used to open holes in the nitride that give electrical access to the top metal layer. In other words,passivation cuts define the entrance and exit points to the outside world. 19. State Moores law. Moores law states that The number of transistors on a die will double in every eighteen months. 20. What are the classification of design rules? Design rules can be classified into i. Minimum feature ii. Minimum spacing iii. Surround rule iv. Exact size 21.What is minimum feature and minimum spacing? Minimum feature is a smallest side length of an object on the layer. If the object is a line ,then this specifies the minimum line width. Minimum spacing rules govern how close two polygons can be placed. 22.What is surround rule and exact size? A surround rule is used when a feature on one layer must be embedded with in a polygon on another layer. An exact size rule means that the feature can only have the dimensions specified in the rule . other sizes are not permitted. 23.What is process specific rules ? To assign numerical values to every important width, spacing and specialized situation that may arise in constructing a CMOS layout. This is known as Process specific rules. 24. Define design rules(DRs). Minimum width and spacing values are specified for every layer on the chip. They are part of a larger group of geometrical specifications that collectively are known as layout design rules. 25. What is meant by Reactive Ion Etching? Reactive Ion Etching in which ionized atoms of an inert gas such as argon(Ar) are mixed with etch-assisting chemicals. The mixture is then excited with a radio frequency electric field in a manner that drives the ions/chemicals in a vertical up-down motion to etch away the surface. 26. Give the advantages of IC? The advantages are i. Size is less

ii. High Speed iii. Less Power Dissipation 27. Give the variety of Integrated Circuits? i. More Specialized Circuits ii. Application Specific Integrated Circuits(ASICs) iii. Systems-On-Chips 28. Give the basic process for IC fabrication. i. Silicon wafer Preparation ii. Epitaxial Growth iii.Oxidation iv.Photolithography v.Diffusion vi.Ion Implantation vii.Isolation technique viii.Metallization ix.Assembly processing & Packaging UNIT-II MOSFET TRANSISTOR 1. What are the materials we use to built the MOSFET? It consists of i. Poly-gate. ii. Gate-oxide. iii. Semiconductor. 2. Define surface charge, Qs. In the structure of MOS capacitor, the positive charge is found at the top Surface of the silicon (at the silicon-to-oxide interface) is referred to as surface Charge, Qs. Qs=Qb+Qn Where Qb _ bulk charge Qn_ layer of free electrons in p-type silicon. 3. What are the three different regions of operation using in square law model? The regions are i. Cut-off region. ii. Triode or linear or non-saturation region. iii. Saturation region. 4. Define body bias voltage. The body bias voltage is expressed as VSB=VS-VB 5. How to express the device transconductance and process transconductance. The device transconductance is expressed as K= k(W/L) It has the units of A/V2 The process transconductance is expressed as K= Cox It also has the unit of A/V2 6. Define mobility ratio. Taking the ratio of both nFET and pFET process transconductance it will gives the kn n Cox kp = p Cox n = p = r where r is the mobility ratio. The exact value of r varies with the processing as many factors affect the mobility. 7.How to measure the effective channel length? In MOS capacitor, the effective channel length Leff that is measured between the edges of the n-type drain and source regions. 8. Write the current equation for cut off, triode and saturation region. For cut off region, ID=0 For triode region

ID= Kn[2(VGS-VTn)VDS-V2 DS] 2 For saturation region, ID = Kn(VGS-VTn)2[1+O(VDS-Vsat)] 2 9. Define MOSFET capacitors. MOSFET capacitors are defined between pairs of terminals, including the bulk connections. This gives rise to five contributions such as CGS,CGD,CGB, C SB and CDB. CGS, CGD,CGB are related to MOS capacitor. The remaining two C SB and CDB are due to PN junction. 10. How to express the MOS capacitors in terms of gate capacitance? The MOS capacitors can be expressed in terms of gate capacitance is CG=Cox WL Where area has been taken to be A=WL 11. Write the capacitance equation for three regions? For cut off region, CGB=CG, CGS,CGD=0. For triode region, CGS= 2 CG , CGD=0, CGB=0 3 For saturation region, CGS , CGD= 1 CG, CGB=0 2 12. How we find the threshold voltage variation in transistor? The threshold voltage of transistor varies according to VTn = VT0n + P [Q(2|S| +VSB) - Q(2|S|)] Where VT0n is the zero body bias threshold voltage and is called the body bias coefficient. 13.What is the possible modification to change the saturation current? The possible modification to change the saturation current is I D,sat = Kn (VGS-VTN)T 2 Where T varies with 1.2 to 1.5 for submicron devices. 14.What is the total capacitance for n-type source /drain? For n-type source or drain the total capacitance is sum of bottom and sidewall contributions in the form of Cn = Cbot + Csw 15. What are the different regions we can define in MOSFET depend upon voltages? For cut off region, Vds=0 For triode region, Vds<Vgs-Vt For saturation region, Vds>Vgs-Vt and Vgd<Vt 16. Define threshold voltage V(t). Threshold voltage can be defined as voltage Vgs(gate to source voltage) applied below which Ids drop to zero. Vt=V t-mos + Vf band 17. What is body effect? Threshold voltage Vt is not constant with respect to voltage difference between substrate and source of MOS transistor. This is known as body effect and it is otherwise known as substrate bias effect. 18. What are the parameters in threshold voltage? The parameters are i. Gate conductor material. ii. Gate insulation material. iii. Gate insulator thickness-Channel doping. iv. Impurities at the silicon- Insulator surface. v. Voltage between source and substrate. 19. What is Enhancement mode transistor and Depletion mode Device? Enhancement mode transistor is the device that is normally cut-off with zero gate

bias. Depletion mode Device is the device that conduct with zero gate bias. 20. When the channel is said to be pinched off? If a large Vds is applied this voltage with deplete the Inversion layer .This Voltage effectively pinches off the channel near the drain. 21. What are the advantages of CMOS process? i. Low power Dissipation ii. High Packing density iii.Bi directional capability iv. Low Input Impedance v.Low delay Sensitivity to load. 22. Why NMOS technology is preferred more than PMOS technology? N- channel transistors has greater switching speed when compared to PMOS transistors. 23. What are the different MOS layers? i. n-diffusion ii. p-diffusion iii.Polysilicon iv.Metal 24. Define Threshold voltage in CMOS? The Threshold voltage, VT for a MOS transistor can be defined as the voltage applied between the gate and the source of the MOS transistor below which the drain to source current, IDS effectively drops to zero. 25. What is Latch up? Latch up is a condition in which the parasitic components give rise to the establishment of low resistance conducting paths between VDD and VSS with disastrous results. Careful control during fabrication is necessary to avoid this problem. 26.What is Stick Diagram? It is used to convey information through the use of color code. Also it is the cartoon of a chip layout. 27.What are the uses of Stick diagram? i. It can be drawn much easier and faster than a complex layout. ii.These are especially important tools for layout built from large cells. UNIT-III CMOS LOGIC GATES DESIGN AND LAYOUT 1. Draw the circuit and layout diagram for series connected nFETs. 2. Draw the circuit and layout diagram for parallel connected nFETs. 3. What is Elmore time constant? In a series connected RC network,the time constant is given by =2RnC2+RnC1 The first term is due to C2 discharging through a total resistance of 2Rn,while the second term is from C1 discharging through one Rn. This is referred to as an Elmore time constant. 4. Draw the logic circuit diagram for NOR gate. 5. Draw the logic circuit diagram for NAND gate. 6. Define rise time and fall time. The time for the signal to rise from a low value to the high value in a linear ramp is called rise time. The time interval for the pulse to fall from a high to a low value is called fall time. 7. Define time start and time pulse. The delay from t=0 before the pulse is applied is called time start. The pulse width,i.e., the length of time that the pulse is kept at the high value. 8. Write a short note about complex logic gates. Complex logic gates give a combination of logical OR and AND functions in a single circuit. This is useful for merging functions and designing small circuit. Example is f=a.b+c which provides one AND and one OR operation.The NOT is a characteristics of CMOS logic. 9. What is tri-state circuits? In a tri-state circuits,the output can also be in a Hi-Z(high impedance)

state,giving the circuit three distinct states. The simplest technique for implementing a tri-state inverter is to add two additional transistors to the basic NOT gate. 10.Draw the circuit and symbol for transmission gate. 10. Design 2:1 MUX using transmission gate. 11. Draw the transmission gate based XOR circuit. 12. When there is a necessary to design transistors with large channel width? The transistors is designed with large channel width,when the devices must accommodate large-current flow levels. A few layout problems arise if W is large compared to the channel length,L. 13. What is the operation of transmission gate? When s=1,both FETs are ON,and the input a is transmitted to the output so that f=a. The TG is capable of full-rail transmission since the nFET can pass a strong 0(0V) and the pFET can pass a strong 1(VDD). If s=0,then both transistors are OFF and the output is in a Hi-Z state.In this case,f is undefined. 14. What are the different cell levels in cell hierarchy? The four cell levels are a. Primitive cells. b. Simple cells. c. Moderate complexity cell. d. Higher complexity cell 15. Define custom design. In cell hierarchy, some times the existing cells will not give the desired characteristics, So it is a necessary to design new ones. This is called as custom design. 16. What is cell library? The collection of cell files is called cell library. It is made up of both primitive functions and large macro functions,like adders and memories,that form the basis of the design. 17. Define layer-to-layer crosstalk. Different levels of metal interconnect are stacked according to the process flow.Capacitive coupling between successive conducting layers can cause unwanted signal transferal from one line to the other. This is called crosstalk. 18. Define Full custom design. If a chip is engineered from scratch without the use of a cell library, then it is called a full custom design. In a complexity of modern digital systems,full custom designs are found only in very specialized circumstances. 19.What is the characteristics of cell library? An important characteristics of cell library is uniformity.Every cell must be designed with compatible geometrical features to allow interfacing at the physical level. . UNIT-IV STORAGE ELEMENTS AND DYNAMIC LOGIC CIRCUITS 1. What is the operation of SR latch? If (S,R)=(0,0), then the latch is in a hold state, which means the Q and Q retain their current value. If (S,R) changes to (1,0), the inputs set the latch outputs to (Q,Q)=(1,0); Conversely,if (S,R) changes to(0,1), the outputs are reset to(Q,Q)=(0,1).The combination (S,R)=(1,1) is not used. 2. Draw the NOR based SR and D latches. 3. How to design the simple register using transmission gate. 4. What is bistable circuit ? The closed loop consists of two inverters,such that both a=0 and a=1 are stable states,i.e., they will hold their value.This is due to feedback and can be verified by tracing through the loop. 5. What is meant by ring oscillator? Any closed loop that has an even number of inverters will be a stable circuit. If an odd number of stages is used, the ring oscillate, and it appropriately is called a ring oscillator. 6. What is meant by positive edge triggered D-type flip flop? A positive edge triggered D-type flip flop loads the value of D on when the clock makes a positive transition from 0 to 1. The edge triggered property is indicated by the triangle at the clock input.

7. How charge leakage exists in CMOS circuits? In Negative edge triggered Flip-Flop,the operation appears to be straightforward,charge storage on the capacitor,is subject to a problem called charge leakage. 8. Explain about master slave D- type flip flop when clock signal=0 and 1. When the clock=0,the master accepts the input. During this time, both the feedback transistor in the master latch and the input FET to the slave are open. When the clock makes the transition to 1, corresponding to a positive edge, the master input is blocked and the bit is transferred to the slave. The master feedback loop is closed to ensure complete transmission. 9. What is dynamic DFF? A dynamic circuit operates by using the parasitic capacitance on a CMOS node to store electric charge. A dynamic flip flop can be built using two oppositely phased tristate inverters. These are connected in master-slave configuration. 11.Write a short note about static RAM cell. Static random-access memories(SRAMs)are highly repetitive VLSI structures that are used for read/write data storage. An SRAM cell is different from simple latch, in that it uses the same lines for input and output. The most widely used design is 6T(six transistor). 12. When the static RAM cell is in hold state. In static RAM, there are two transistors called access transistors and are used to provide conduction path to the internal bit storage circuit. The access FETs are controlled by the word line signal, Wl. When Wl=0, both transistors are OFF, and the cell is in a hold state. 13. What is meant by dynamic logic gat In nMOS dynamic logic gate, uses a single clock controlled complementary Pair consisting of Mn and Mp. The logic is performed entirely by an array of nFET that acts like an open or closed switch,depending on the inputs.This is possible because only one type of FET(nFET or pFET) is really is needed to provide the switching. 14. What is precharge ? When the clocking signal=0, the circuit is in precharge(P) where pFET is ON and nFET is OFF. This allows the output capacitor,Cout, to charge to a voltage of Vout=VDD, every half clock cycle. 15. What is evaluate? When the clocking signal=1, the circuit is in evaluate(E) where pFET is OFFand nFET is ON. This allows the output capacitor,Cout, to go to a voltage of Vout=0V, every half clock cycle. 16. Write a short note about domino logic. Domino logic is an extension that adds an inverter at the output to Overcome the possibility of a hardware glitch.It is designed to use the clock pulse to synchronise the precharge event. 17. What is meant by self resetting logic gate? Self resetting logic uses a feedback network to automatically restore the charge on the internal capacitor after a discharge event. 18. Write a short note about dynamic memories. Dynamic Rams are the most widely used memories because they can be manufactured at the lowest cost per bit. System memories are almost exclusively DRAMs. Modern memory design and manufacturing is based on the best fabrication processes. Since size and speed of a DRAM chip relies on the resolution and electrical characteristics of the silicon. 19. How to estimate the leakage current using I-V relationship. The leakage current is due to many effects, but the sub threshold conduction is the most important in a submicron technology. The leakage current is expressed as Ileak = Cs \Vs \Vt 20. Write the equation for hold time. The hold time is expressed as th = Cs [Vs(0)-V1] Ileak Where V1 is the minimum voltage that can be recognized as a logic 1.

Vs(0) is the initial voltage on the capacitor. UNIT-V VHDL 1)Write the acronym for VHDL? VHDL is an acronym for VHSIC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). 2) What are the different types of modeling VHDL? 1) Structural modeling 2) Data flow modeling 3) behavioral modeling 4) Mixed type of modeling 3) What is packages and what is the use of these packages A package declaration is used to store a set of common declaration such as components types procedures and functions these declaration can then be imported into others design units using a use caluse. 4) What is variable class ,give example for variable An object of variable class can also hold a single value of a given type , However in this case different values can be assigned to a variable at different time. Ex:variable ss: integer; 5) Name two subprograms and give the difference between these two. 1) Function 2) procedure Only one output is possible in function.. Many outputs possible using procedure 6) What is subprogram Overloading If two or more subprogram to be executed in a same name. overloading of subprogram should be performed. 7) write the VHDL coding for a sequential statement (d-flipflop ) entity dff is port(clk,d:in std_logic; q:out std_logic); end; architecture dff of dff is begin process(clk,d) begin if clk event and clk= 1 then q<=d; end process; end; 8) What are the different kinds of The test bench? Stimulus only Full testbench Simulator specific Hybrid testbench Fast testbench 9) What is Moore FSM The output of a Moore finite state machine(FSM) depends only on the state and not on its inputs. This type of behaviour can be modeled using a single process with the case statement that switches on the state value. 10) Write the testbench for and gate entity testand2 is end entity architecture io of testand2 is signal a,b,c:std_logic; begin g1:entity work.and2(ex2) port map(a,b,c) a<= 0 , 1 after 100 ns; b<= 0 , 1 after 150 ns; end; 11) Give the different arithmetic operators? Operator symbol Operation performed Number of operands * Multiply Two

/ Divide Two + Add Two - Subtract Two % Modulus Two ** Power (exponent) Two 12). Give the different bitwise operators. Operator symbol Operation performed Number of operands ~ Bitwise negation One & Bitwise and Two | Bitwise or Two ^ Bitwise xor Two ^~ or ~^ Bitwise xnor Two ~& Bitwise nand Two ~| Bitwise nor Two 13. Differentiate a signal and variable? SIGNAL VARIABLE Represents circuit in interconnects(wires) Represents local information Can be global(seen by entire code) Local(visible only inside the corresponding PROCESS,FUNCTION,or PROCEDURE) Update is not immediate in sequential code(new value generally only available at the conclusion of the PROCESS,FUNCTION, or PROCEDURE Updated immediately (new value can be used in the next line of code) 14. Explain case statement in VHDL with an Example. The case statement selects one of the branches for execution based on the value of expression. The expression value must be of discrete type or of a one-dimensional array type. Case is the statement intended exclusively for sequential code(along with IF, LOOP and WAIT). The syntax is CASE identifier IS WHEN value =>assignments; WHEN value =>assignments; END CASE; EXAMPLE entity dff is port(clk, rst,d:in std_logic; q:out std_logic); end dff; architecture behaviour of dff is begin process(clk,d) begin case rst is WHEN 1=> q<=0; WHEN 0=> if (clk event and clk= 1) then q<=d; end if; WHEN OTHERS=>NULL; End case; end process; end behaviour; 15.. Explain BLOCK statement in VHDL with an Example. A block statement is a concurrent statement. It can be used for three major purposes: i. To disable signal drivers by using guards. ii. To limit scope of declarations , including signal declarations. iii. To represent a portion of a design. The two kinds of block is

1. simple. 2. guarded. The syntax of block statement is Block-label:block[(guard-expression)] is [block-header] [block-declarations] Begin Concurrent-statements End block[block-label]; Example: BG:block(guard-expression) Signal SIG:BIT; Begin SIG<=guarded waveform-elements; End block BG; 16. Explain Process statement in VHDL with an Example. A process statement contains sequential statements that describe the functionality of a portion of an entity in sequential terms. It is characterized by the presence of IF , WAIT,CASE or LOOP and by a sensitivity list. The syntax is [label:] PROCESS(sensitivity list) [VARIABLE name type[range] [:=intial_value;] ] Begin (sequential code) End PROCESS [label]; Example: Architecture behaviour of example is SIGNAl temp:bit; Begin Temp <=a NAND b; PROCESS(clk) Begin If(clk event and clk-1) then Q<=temp; End PROCESS; End example; 17. Explain Generate statement in VHDL with an Example. GENERATE is a concurrent statement(along with operators and WHEN). It is equivalent to the sequential statement LOOP in the sense that it allows a section of code to be repeated a number of times, thus creating several instances of the same assignments. The syntax is Label:FOR identifier IN range GENERATE (concurrent assignments) End GENERATE; Example: SIGNAL x: bit_vector(7 downto 0); SIGNAL y: bit_vector(15 downto 0); SIGNAL z: bit_vector(7 downto 0); G1:FOR I IN x RANGE GENERATE Z(i)<=x(i) and y(i+8); End GENERATE; 18. What is Test Bench? The test bench name comes from the analogy with a real hardware test bench, on which a device under test is stimulated with waveform generates and observed with probes. A VHDL test bench consists of an architecture body containing an instance of component to be tested and processes that generate stimuli on signals , terminals or quantities connected to component instance. 19. Give the behavioral model for JK flipflop. entity JKFF is port(SR, RN, J, K,clk:in std_logic; q:out std_logic);

end JKFF; architecture behaviour of JKFF is begin process(clk, SN, Rn) begin if RN=0 then q<=0; elsif SN=0 then q<=1; elsif clk=0 and clk event then q<=(J and NOT q) or (NOT k and q); end if; end process; end JKFF; 20. Give the behavioral model for T flipflop. entity tff is port(clk,t:in std_logic; q:out std_logic); end tff; architecture behaviour of tff is begin process(clk,t) begin if clk event and clk= 1 then q<=d; end process; end behaviour; 21. Give the data flow model for half adder and half subtractor. // half adder Entity halfadder is port(a, b:in std_logic; sum, carry:out std_logic); end halfadder; architecture behaviour of halfadder is sum<= a XOR b; carry<=a AND b; end behaviour // half subtractor Entity halfsubtractor is port(a, b:in std_logic; diff, borrow:out std_logic); end halfadder; architecture behaviour of halfadder is diff<= a XOR b; borrow<= (NOT) a AND b; end behaviour; 22. Give the dataflow model for full adder. // full adder Entity fulladder is port(a, b, c:in std_logic; sum, carry:out std_logic); end fulladder; architecture behaviour of fulladder is sum<= (a XOR b) XOR c; carry<=(a AND b) OR (b AND c) OR (c AND a); end behaviour; 23. Give the dataflow model for full subtractor. // full subtractor Entity fulladder is port(a, b, c:in std_logic; diff, borrow:out std_logic); end fullsubtractor; architecture behaviour of fullsubtractor is diff<= (a XOR b) XOR c;

borrow<=(NOT a AND b) OR (b AND c) OR (c AND NOT a); end behaviour 24. What is component instantiation? A component instantiation statement defines a subcomponent of the entity in which it appears. It associates the signal in the entity with the ports of that subcomponent. A format of a component instantiation statement is Component-label:component-name[port map(associaton-list)]; Example: -- component declaration: component NAND2 port(A,B: in std-logic; Z:out std_logic); End component; -- component instantiation: N1:NAND2 port map(s1,s2,s3); 25.. Differentiate sequential from concurrent signal assignment statements. Sequential signal assignment statements concurrent signal assignment statements signal assignment statements can also appear within the body of process statement called sequential signal assignment statements signal assignment statements that appear outside of process are called concurrent signal assignment statements. Not event triggered and are executed in sequence in relation to other sequential statement that appear within the process. Event triggered i.e., they are executed whenever there is an event on a signal that appears in its expression. *****ALL THE BEST***** .