Volume 1 Issue 1 July

International Journal Of Communication And Computer Technologies
Volume 01 No.1, Issue: 01 JULY 2012
Performance Evaluation of AODV, DSR and DSDV for Congestion Control in Wireless Sensor Networks
R. B. Dravida Priyaa (M.E CCE), SNS College of Technology, Coimbatore.
Abstract In recent years, Wireless Sensor
Networks plays a vital role in various fields. Wireless Sensor Networks (WSNs) have emerged as an important new area in wireless technology. Wireless sensor network consists of numerous tiny sensors deployed at high density in regions requiring surveillance and monitoring. There are many existing protocols, techniques and concepts from traditional wireless networks, such as cellular network, mobile ad-hoc network, wireless local area network and Bluetooth are applicable and still used in wireless sensor networks. In WSNs, packet loss occurs due to congestion. In WSN, congestion detection and congestion control are the major research areas. It is important to design protocols for controlling congestion. As wireless sensor networks are evolving to applications where high load demands dominate and performance becomes a crucial factor, congestion remains a serious problem that has to be effectively and efficiently tackled. Congestion in WSNs is mitigated wither by reducing the data load or by increasing capacity (employing sleep nodes). The design of routing protocols for WSNs must consider the power and resource limitation of network nodes, The time varying quality of wireless channels and packet loss and delay. Protocols like AODV, DSR and DSDV have been proposed. Simulation results show that AODV performs better in the case of throughput, average end-to-end delay and packet delivery ratio, whereas DSR performs better in the case of packet drops. Keyword: AODV, DSR, DSDV, Wireless Sensor Networks, Performance Evaluation. efficient as possible and rely on their large number to obtain high quality results. Network protocols must be designed to achieve fault tolerance in the presence of individual node failure while minimizing energy consumption. In addition, since the limited wireless channel bandwidth must be shared among all the sensors in the network, routing protocols for these networks should be able to perform local collaboration to reduce bandwidth requirements. Communication between the sensor nodes and the base station is expensive, and there are no high energy nodes through which communication can proceed. The goal of this paper is to carry out a systematic performance of three dynamic routing protocols for WSN, Ad-hoc On Demand Distance Vector Protocol (AODV), Dynamic Source Routing Protocol (DSR) and Destination Sequenced Distance Vector Protocol (DSDV) in wireless sensor networks using NS2.
II ROUTING OBJECTIVES
Some sensor network applications only require the successful delivery of messages between a source and destination. However, there are applications that need even more assurance. These are the real-time requirements of the message delivery, and in parallel, the maximization of network lifetime.
I INTRODUCTION
Wireless Sensor Networks (WSNs) are defined as an autonomous, adhoc system consisting of collection of networked sensor nodes designed to intercommunicate via wireless radio. These are small with sensing, computations and wireless networking capabilities and as such these networks represent the convergence of important technologies. Sensor networks can contain hundreds or thousands of sensing nodes. It is desirable to make these nodes as cheap and energy
i) Non-Real Time Delivery: The assurance of message delivery is indispensable for all routing protocols. It means that the protocol should always find the route between the communicating nodes, if it really exists. This correctness property cab be very proven in a formal way, while the average case performance can be evaluated by measuring the message delivery ratio. ii) Real Time Delivery: Some applications require that a message must be delivered within a specified time to a location, otherwise the message becomes useless or its information content is decreasing after the time bound. Therefore, the main objective of these protocols is to completely control the network delay. Page 1
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iii) Network Lifetime: The protocol objective is crucial for the networks, where the application must run on sensor nodes as long as possible. The protocols aiming this concern try to balance energy consumption equally among nodes considering their residual energy levels. However, the metric used to determine the network lifetime is also dependent. Most protocols assume that every node is equally important and they use the time until the first node dies as a metric, or the average energy consumption of the nodes as another metric. If nodes are not equally important, then the time until the last or high priority nodes die as a reasonable metric. III SIMULATION MODEL Simulation Area Model Transmitting Power Receiving Power Transmission Range Number of nodes Antenna Model Network Interface Type MAC Type Routing Type Interface Queue Type 500*500 Energy 0.660 0.396 250m to 450m 50 Omni Antenna Phy/ Wireless Phy 802.11 AODV, DSR, DSDV Queue/DropTail
Each node also maintains information about its reachable neighbors with bi-directional connectivity. Whenever a node (router) receives a request to send a message, it checks its routing table to see if a route exists. Each routing table entry consists of the following fields: a) Destination address b) Next Hop address c) Destination Sequence number d) Hop Count
V DYNAMIC SOURCE ROUTING (DSR) PROTOCOL

DSR is based on source routing, which means that the originator of nodes through which the packet must pass while travelling to the destination. The DSR protocol consists of two basic mechanisms: Route Discovery and Route Maintenance. a) Route Discovery Route discovery is used only when a source node attempts to send a packet to a destination node and does already know a route to it. To initiate the Route Discovery, the source node transmits a Route Request with a unique ID as a single local broad cast packet. When come intermediate mode receives this route request, at first it determines whether it has seen the route request or not. If the node is already seen the route request earlier, it will discard the packet. Otherwise, it will check its Route Cache whether there is a route to the destination of the packet. If it has the route to the target in its routing cache, it returns a route reply to the initiator of the route discovery, giving a copy of the accumulated route record from the route request. Otherwise, it transmits the route request until the route request is received by the target. b) Route Maintenance
IV AD-HOC ON-DEMAND DISTANCE VECTOR ROUTING (AODV) PROTOCOL

In AODV, each node maintains two separate counters: 1. Sequence number, a monotonically increasing counter used to maintain freshness information about the reverse route to the source. 2. Broadcast-ID, which is incremented whenever the source issues a new route request (RREQ) message.
DSR protocol implements the route maintenance mechanisms while communicating the packets from source node to the destination node. In this scenario, DSR protocols uses the route mechanisms, to detect any other possible known route towards the destination to transmit data. If the route maintenance fails to find an alternative known route to establish the communication then it will invoke the route discovery to find the new route to the destination.
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delay.
VI DESTINATION SEQUENCED DISTANCE VECTOR ROUTING (DSDV) PROTOCOL

It is table driven routing protocol based on Bellman-Ford routing algorithm with certain improvements. Every mobile station maintains a routing table that lists all available destinations, the number of hops to reach the destination and the sequence assigned by the destination node. The sequence number is used to distinguish stale routes from new ones and thus avoid the formation of loops. The stations periodically transmit their routing tables to their immediate neighbors. A station also transmits its routing table if a significant change has occurred in its routing table from the last update sent. So, the update is both time-driven and event driven.
Fig.1. Average End-to-End Delay Vs Number of b) Packet Drop

DSR packet drop very low when compared to DSDV and AODV. Drop rate is more at less number of sources in the case of DSDV. Drop rate is almost constant in AODV irrespective of varying load. Hence DSR outperforms DSDV & AODV.
VII SIMULATION RESULTS & CONCLUSION a) Comparison of Delay

Simulations were run for varying number of packets with constant packet size. The results shows that the delay of DSR is slightly less than AODV and DSDV for increasing number of packets, the delay is more for DSDV for lower number of packets. According to the above result, it can be said that AODV outperforms DSR for more number of sources or for more network traffic and DSR performs better even though increasing number of packet in terms of
Nodes
Fig.2. Total Packet Drop Vs Number of Nodes
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c) Packet Delivery Ratio

The ratio of the number of packets originated by the application layer to the number of packets received. The results show that DSDV outperforms DSR and AODV especially when the
Fig.4. Received Packet Rate Vs Number of Nodes VIII CONCLUSION

In this paper, Wireless sensor routing protocols like AODV, DSR and DSDV has been implemented using NS-2.33 and the various performance parameters like Packet delivery ratio, Packet received rate, Total dropped packets, Average End-to-End delay has been compared. DSDV uses the proactive table driven routing strategy whereas DSR uses the reactive on-demand routing strategy with different routing mechanisms. Experimental results showed that AODV perform better for packet delivery ratio as well as throughput. It is also showed that DSR performs better packet received rate for nodes less than 10, but for nodes more than 10, AODV perform better than DSR and DSDV. DSR outperformed than AODV and DSDV for total dropped packets. AODV performs better than DSR and DSDV for average end-to-end delay. The future work is to compare the proposed protocol and the other classes of Ad-Hoc routing protocols with different simulation parameters and metrics.
number of nodes are between 15 and 30.
Fig.3. Packet Delivery Ratio Vs Number of Nodes d) Received Packets

AODV, DSDV and DSR protocols for Received Packets with varying numbers of nodes of 5,10 and 15. From figure it is observed that for small number of nodes up to 10 numbers, the performance of DSR protocol have better performance than AODV & DSDV protocols but for more numbers of nodes that is more than 10 nodes, the performance of AODV protocol have better performance than DSR & DSDV protocol.
References
1. Charalambos Sergiou and Vasos Vassiliou, (2010), DAlPAS: A Performance Aware Congestion Control Algorithm in Wireless Sensor Networks, IEEE transaction. Chonggang Wang1, Kazem Sohraby1, Victor Lawrence2, Bo Li3, Yueming Hu4,(2006), Priority-based Congestion Control in Wireless Sensor Networks, Proceedings of the IEEE International Conference on Sensor Networks. Charles E. Perkins, Pravin Bhagwat, (1994), Highly dynamic DestinationSequenced Distance Vector routing (DSDV) for mobile computers, In proceedings of the SIGCOMM '94 Conference on Communications Architectures, Protocols and Applications, pp 234-244. De Marco, F. Postiglione, M. Longo, (2004), Run-time adjusted congestion control for multimedia: experimental results, Journal of Interconnection Networks (JOIN), vol. 5, no. 3, pp. 249266.
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5.
C.T. Ee and R. Bajcsy,(2004), Congestion Control and Fairness for Many-to-one Routing in Sensor Networks, in Proc.ACM Sensys.
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B. Hull, K. Jamieson, and H. Balakrishnan, (2004), Mitigating Congestion in Wireless Sensor Networks, in Proc. ACM Sensys. 7. M. Ishizuka and M. Aida,(2004), Performance Study of Node Placement in Sensor Networks In Proceedings of the 24th international Conference on Distributed Computing Systems Workshops - W7: EC (ICDSCW'04) Volume 7. 8. Le D. Johnson, D.Maltz, (1996), Dynamic source routing in ad-hoc wireless networks, In proceddings of Mobile Computing, Chapter 5. 9. Josh Broch, David Johnson and David Maltz, (1998), The dynamic source routing in mobile ad-hoc networks, IETF. 10. J. Kang, Y. Zhang, and B. Nath, Tara: Topology-aware resource adaptation to alleviate congestion in sensor networks, IEEE Transactions on Parallel and Distributed Systems, vol. 18, no. 7, pp. 919931. 11. Mohammad Z. Ahmad and Damla Turgut,(2008), Congestion Avoidance and Fairness in Wireless Sensor Networks, Published in the IEEE GLOBECOM proceedings. 12. N. Pekergin, 1998, Stochastic Bounds on Delays of Fair Queueing Algorithms. Technical Report PRISM, UVSQ 10, Universite de Versailles-St-Quentin.
13. Rong Pan, Balaji Prabhakar, and Konstantinos Psounis,2000, CHOKe, A Stateless Active Queue Management Scheme for Approximating Fair Bandwidth Allocation. IEEE INFOCOM, Mar 2000. 14. C. Sergiou, V. Vassiliou, A. Pitsillides,(2007), Reliable Data Transmission in Event-based Sensor Networks during Overload Situation, in Proc. of the 2nd International Workshop on Performance Control in Wireless Sensor Networks (PWSN 2007), Austin, Texas. 15. R.Then Malar,(2010), Congestion Control in Wireless Sensor Networks Based MultiPath Routing In Priority Rate Adjustment Technique, Published in International Journal of Advanced Engineering & Applications. 16. C. Tien Ee, R. Bajcsy,(2004), Congestion Control and Fairness for many-to-one Routing in Sensor Networks, In Proceedings of the 2nd International Conference on Embedded Networked Sensor Systems. 17. C.-Y. Wan, S. B. Eisenman, and A. T. Campbell, (2003) CODA: congestion detection and avoidance in sensor networks, in SenSys 03: Proceedings of the 1st international conference on Embedded networked sensor systems. New York, NY, USA: ACM Press, pp. 266279. 18. N.S.M. Usop, A.Abdullah, A.F.A.Abidin, (2009), Performance evaluation of AODV, DSR and DSDV routing protocol in grid environment, IJCSNS International Journal of Computer Science and Network Security, Vol. 9, pp 261-268.
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Design of 16-Bit CRC Generator

1
A.S.Prabhu, 2 N.Vignesh and 3 V.Elakya
Asst Prof, [M.E.,VLSI Design], EBET Group of Institutions, Kangayam, Tamil Nadu, India. Mail id: prabhu.mevlsi@gmail.com 2 P.G Scholar [M.E., VLSI Design], Bannari Amman Insistute of Technology, Sathyamangalam, Tamil Nadu, India. Mail id: vickee76@gmail.com 3 Asst Prof, [M.E., VLSI Design], Angel College of Engineering and Technology, Tirupur, Tamil Nadu, India. Mail id: elakya.17@gmail.com
Abstract Cycle Redundancy Check (CRC) Generator provides an advanced tool for implementing the most widely used error detection scheme in serial digital data handling systems. The implementation of high speed 16-Bit CRC Generator architecture that archives low area, less power consumption based on Gate Diffusion Input logic .Gate Diffusion Input logic is a technique to design low power digital circuits that is used to reduce transistor count, power consumption and propagation delay of the digital circuits. Here the Gate Diffusion Input D flip flop is a basic cell to design a CRC Generator, maintaining low complexity of logic design. Hence the total area of the CRC Generator and power can be reduced. Power consumption and transistor count can be calculated by using Tanner Electronic Design Automation Tool.
reduce power consumption, they are not suitable for operation in the sub-threshold region. In addition these designs require a large number of transistors, resulting in a large area, not suitable for small, low-priced systems.
This paper presents the implementation of 16-bit CRC Generator using area and power efficient Gate-Diffusion-Input (GDI) D flip flop.
II. CMOS LOGIC DESIGN TECHNIQUES To reduce the power consumption different CMOS logic design techniques like CMOS complementary logic, Pseudo nMOS, Dynamic CMOS, Clocked CMOS logic (C2MOS), CMOS Domino logic, Cascade voltage switch logic (CVSL), Modified Domino logic, Pass Transistor Logic (PTL) have been proposed [8]. One form of logic that is popular for in low-power digital circuits is PTL. The advantages of PTL over standard CMOS design are 1) High speed, due to small node capacitances. 2) Low power dissipation, as a result of reduced number of transistors. 3) Lower interconnection effect, due to smaller area. In spite of these advantages of PTL, there are two main drawbacks. One is the threshold voltage across the single channel pass transistors results in reduced drive and hence slower operation at reduced voltages and the other one is, since the
Index Terms Low power; VLSI; GDI technique; Flip-Flops; CRC Generator; Sequential circuits
I. INTRODUCTION Power dissipation has become a prime constraint in high performance applications, especially in portable and battery operated ASIC systems. It is necessary to reduce power consumption. Power consumption is proportional to square of supply voltage [1]. Technology scaling can be used in which the threshold voltage is scaled in proportion to the supply voltage. As technology scales, leakage currents have become one of the main power consumers and this leads to increase in sub threshold leakage power. Many design architecture and techniques have been developed to reduce power dissipation [2]. Of the various building blocks in digital designs one of the most complex and power consuming is the Flip-Flop. Although several Flip-Flop designs have been proposed to
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high input voltage level is not VDD the PMOS device in inverter is not fully turned off. In order to overcome these problems some sort of PTL techniques have been proposed. Transmission gate CMOS (TG) uses transmission gate logic to realize complex logic functions using less number of transistors. It solves the problem of low logic level swing by using PMOS as well as NMOS. Complementary pass transistor logic (CPL) uses NMOS pass transistor logic with CMOS output inverters. Small stack height and internal node low swing are important features but it suffers from static power consumption due to the low swing at the gates of the output inverters [9]. Double pass transistor logic (DPL) uses complementary transistors to keep full swing operation and reduce the dc power consumption. This eliminates the need for restoration circuitry. One disadvantage of DPL is large area due to the presence of PMOS transistors.
B 1 B C 0
1 B 0 B 1
A A A A A
A'+B A+B AB
F2 OR AND
A'B+AC MUX A' NOT
Table I shows how different logic functions implemented with GDI cell. GDI enables simpler gates, transistor count and lower power dissipation in with standard CMOS and PTL techniques. IV.
IMPLEMENTATION OF D FLIP -FLOP
III. CMOS VS GDI A new low power design technique GateDiffusion-Input (GDI) that solves most of the problems. This technique reduces the power consumption, propagation delay, and area of digital circuits. The GDI method is based on the simple cell shown in Figure.1. A basic GDI cell contains four terminals G (common gate input of nMOS and pMOS transistors), P (the outer diffusion node of pMOS transistor), N (the outer diffusion node of nMOS transistor), and D (common diffusion node of both transistors).
A. Design of Static Cmos D Flip Flop To reduce power a Double edge triggering is implemented. In Double edge triggering is done on both edges of clock since they effectively enable a halving of the clock frequency. A novel implementation of D Flip-Flop in CMOS technique is shown in Figure.2. It is based on the Master-Slave connection of two CMOS D Latches.
Fig. 1: Basic GDI cell
Fig. 2: Design of Static CMOS D Flip Flop
Table I: Logic functions implemented with GDI cell
N P 0 B
G A
D A'B
F F1
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Fig. 3: Output waveform static CMOS D Flip Flop
Fig. 5: GDI D Flip Flop without Buffer
B. Design of GDI D Flip Flop To reduce power a Double edge triggering is implemented. In Double edge triggering is done on both edges of clock since they effectively enable the clock frequency. A novel implementation of D Flip-Flop in GDI technique is shown in Figure.4. It is based on the Master-Slave connection of two GDI D Latches. Each latch cell consists of four basic GDI cells [3],[4].
The Output waveform of GDI D Flip Flop without Buffer is shown in the following the wave form has some distortion in it GDI D flip flop will not produce strong ones and zeros
Fig. 6: Output waveform GDI D Flip Flop without Buffer
Fig. 4: D Flip Flop implementation in GDI technique This D Flip-Flop design reduces powerdelay product and area of circuit but isnt always suitable for strong inversion operation due to the threshold voltage drop, but this is substantially reduced in sub-threshold operation.
To reduce this effect one buffer has been added in the output of the GDI flip flop so that the distortion has been eliminated the figure 7 shows the GDI D flip flop with buffer at the output.
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determine whether or not the check bits agree with the data, to ascertain with a certain degree of probability whether or not an error occurred in transmission. If an error occurred, the receiver sends a negative acknowledgement (NAK) back to the sender, requesting that the message be retransmitted [6]. Figure. 9 shows the 16 bit CRC Generator.
Fig. 7: GDI D Flip Flop with Buffer
Finally the distortion less output has been obtained in the following figure 8 shows the distortion less output of GDI D flipflop.
Fig. 9: 16 bit CRC Generator The technique is also sometimes applied to data storage devices, such as a disk drive. In this situation each block on the disk would have check bits, and the hardware might automatically initiate a reread of the block when an error is detected, or it might report the error to software. The CRC is based on polynomial arithmetic, in particular, on computing the remainder of dividing one polynomial in GF(2) (Galois field with two elements) by another [7]. It is a little like treating the message as a very large binary number, and computing the remainder on dividing it by a fairly large prime such as Intuitively, one would expect this to give a reliable checksum. Table II shows the generator polynomials used by some common CRC standards.
Fig. 8: Output waveform GDI D Flip Flop with Buffer
V. IMPLEMENTATION OF CRC GENERATOR
The cyclic redundancy check, or CRC, is a technique for detecting errors in digital data, but not for making corrections when errors are detected. It is used primarily in data transmission [5]. In the CRC method, a certain number of check bits, often called a checksum, are appended to the message being transmitted. The receiver can
Table II: Generator Polynomials Of Some CRC Codes Page 9
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.include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\T-Spice v12.0\models\ml2_125.md" .tran 10n 90n
A. 16 Bit CMOS CRC Generator The implementation of CMOS CRC Generator can be designed by using master slave D Flip Flop which consist of 24 transistor with buffer at the output for the distortion less output .Finally the total transistor count in 16 bit CMOS CRC Generator is 514 it consume average power of 7.45w at the input voltage 5v and the processing time of T-spice is 53.19 seconds. Implementation of 16 bit CMOS CRC Generator is shown in Figure. 10 and its output waveform is shown in Figure.11.the T-spice code was written to calculate the power consumption.
vs vdd GND 5 v1 d GND BIT ({1100}) v2 clk GND BIT ({1101}) .print tran v(q) v(d) v(clk) .power vs 0 90n .end
Fig. 10: 16 Bit CMOS CRC Generator
B. 16 Bit GDI CRC Generator The implementation of GDI CRC Generator can be designed by using master slave GDI D Flip Flop consist of 18 transistor with buffer at the output for the distortion less output. Finally the total transistor count in 16 bit GDI CRC Generator is 418. The average power of 64.4 mw at the input voltage 5v and the processing time of T-spice is 2.50 seconds. Implementation of 16 bit GDI counter is shown in Figure. 12 and its output waveform is shown in Figure.13. The T-spice code was written to calculate the power consumption.
Fig. 11: 16 Bit CMOS CRC Generator output wave form
Fig. 12: 16 Bit GDI CRC Generator
16 Bit Cmos CRC Generator T-Spice Coding: Page 10

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No.of Transistors Power Consumption Total access time
418 64.4 mw
514 7.45 w
2.50 seconds
53.19 seconds
VII. ANALYSIS CHART The result of the comparative analysis chart is shown in following figures. The following figure 14 shows the transistor count, figure 15 shows the power, figure 16 shows total access time.
Fig.13: 16 Bit GDI CRC Generator output waveform 16 Bit GDI CRC Generator T-spice Coding: .include "C:\Documents and Settings\Administrator\My Documents\Tanner EDA\T-Spice v12.0\models\ml2_125.md" .tran 10n 90n vs vdd GND 5 v1 d GND BIT ({1100}) v2 clk GND BIT ({1101}) .print tran v(q) v(d) v(clk) .power vs 0 90n .end
VI. ANALYSIS TABLE Simulation results are summarized in Table III. Table III shows CMOS CRC Generator and GDI CRC Generator comparison.
600 500 400 300 200 100 0 No.of transistors
GDI CRC Generator CMOS CRC Generator
Fig. 14: Transistor count Comparison
W6 a t 4 t s 2
0 POWER
Fig. 15: Power Comparison
Table III :Simulation Results Supply Voltage:5v GDI CRC Generator CMOS CRC Generator Page 11
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60 s 50
e c o n d s
40 30 20 10 0 Total acess time
Flip-Flop and the comparison results have been shown. The implementation of 16 BIT CRC Generator has been presented in GDI technique and can be extended to higher configurations. REFERENCES
[1] Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, ,2006. Digital Integrated Circuits - A Design Perspective.2 nd ed., Prentice Hallof India Pvt Ltd, New Delhi. A.P. Chandrakasan, S. Sheng, and R.W. Brodersen,1992.Low-power CMOS digital design.IEEE J. Solid-State Circuits, vol. 27, pp. 473-484. A.Morgenshtein, A. Fish, I.A. Wagner, 2002.Gate-Diffusion Input (GDI) A Power Efficient Method for Digital Combinational Circuits, IEEE Trans. VLSI, vol.10, no.5 pp.566-581. A.Morgenstein, A. Fish, I. Wagner, 2004 An Efficient Implementation of D- Flip-Flop Using the GDI Technique, ISCAS 04, pp. 673- 676. A. Perez, Byte-wise CRC Calculations, IEEE Micro, Vol. 3, No. 3, June 1983, pp. 40-50 G. Albertango and R. Sisto, Parallel CRC Generation, IEEE Micro, Vol. 10, No. 5, October 1990, pp.63-71. T. B. Pei and C. Zukowski, High-speed parallel CRC cicuits in VLSI, IEEE Transaction Communication,Vol. 40, No. 4, pp. 653-657, 1992. M. Morris Mano, Digital Design Third Edition, Prentice Hall of India private limited, 2006. N. H. E. Weste, and K.Eshraghain, PRINCIPLES OF CMOS VLSI Design, A Systems Perspective, Pearson Education, 2010.
[2]
[3]
Fig. 16: Total access time Comparison

VIII. CONCLUSION In this paper different CMOS logic design families has been reviewed and evaluated based on the performance metrics like area, power, total access time and transistor count. But the proposed techniques have the disadvantages of transistor count, delay and power dissipation. So a new technique, Gate-Diffusion-Input (GDI) technique has been adopted for reducing the transistor count .The GDI technique has been implemented in D
[4]
[5] [6] [7]
[8] [9]
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SIMULATION OF AN AUTOMATIC IMAGE REGISTRATION THROUGH HISTOGRAM BASED IMAGE SEGMENTATION

T.DEVIKA*, Mrs.G.VALARMATHI** *M.E (APPLIED ELECTRONICS)-FINAL YEAR **ASSISTANT PROFESSOR GNANAMANI COLLEGE OF TECHNOLOGY
ABSTRACT: Automatic image registration is still an actual challenge in several fields. Although several methods for automatic image registration have been proposed in the last few years, it is still far from a broad use in several applications, such as in remote sensing. In this paper, a method for automatic image registration through histogram-based image segmentation (HAIRIS) is proposed. This new approach mainly consists in combining several segmentations of the pair of images to be registered, according to a relaxation parameter on the histogram modes delineation, followed by a consistent characterization of the extracted objects through the objects area, ratio between the axis of the adjust ellipse, perimeter and fractal dimension and a robust statistical based procedure for objects matching. The application of the proposed methodology is illustrated to simulated rotation and translation. HAIRIS allows for the registration of pairs of images (multitemporal and multisensor) with differences in rotation and translation, with small differences in the spectral content, leading to a subpixel accuracy. INTRODUCTION
AUTOMATIC IMAGE REGISTRATION
image processing related applications. Remote sensing applications are one of the fields where further research on AIR methods is required. Under this scope, there are particular difficulties so that AIR methods suitable for many computer vision applications will present limited performance. The rigid-body model under the scope of automatic image registration methods is still a present subject of research, in particular under the scope of remote sensing applications. The problem of registering remote sensing images can roughly be locally seen as the determination of translations and a small rotation. Under the scope of computer vision applications, the rigid-body transformation may seem a simple problem to solve with many existing methods. Under the scope of remote sensing applications, one of the major problems is related to the radiometric content (due to multi sensor or multispectral pairs of images). Moreover, scale is frequently known, as most satellite images are provided with sufficiently accurate scale information, being the exception aerial photographs when the aircraft is flying across a region with significant differences in the terrain elevation.
Automatic image registration (AIR) is still a present challenge regarding
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HISTOGRAM BASED METHODS Histogram-based methods are very efficient when compared to other image segmentation methods because they typically require only one pass through the pixels. In this technique, a histogram is computed from all of the pixels in the image, and the peaks and valleys in the histogram are used to locate the clusters in the image. Color or intensity can be used as the measure. A refinement of this technique is to recursively apply the histogram-seeking method to clusters in the image in order to divide them into smaller clusters. This is repeated with smaller and smaller clusters until no more clusters are formed. Histogram-based approaches can also be quickly adapted to occur over multiple frames, while maintaining their single pass efficiency. The histogram can be done in multiple fashions when multiple frames are considered. The same approach that is taken with one frame can be applied to multiple, and after the results are merged, peaks and valleys that were previously difficult to identify are more likely to be distinguishable. The histogram can also be applied on a per pixel basis where the information results are used to determine the most frequent color for the pixel location. This approach segments based on active objects and a static environment, resulting in a different type of segmentation useful in Video tracking. Histogram-based image segmentation comprises three stages: Recognizing the modes of the histogram, Finding the valleys between the identified modes
Finally apply thresholds to the image based upon the valleys. SCOPE OF THE PROJECT A method for automatic image registration through histogram-based image segmentation (HAIRIS) is proposed, which allows for a more detailed histogram-based segmentation, rather than the traditional methods, and consequently to an accurate image registration. HAIRIS is able to estimate the rotation and/or translation between two images which may be multitemporal or multisensory with small differences in the spectral content. PROJECT DESCRIPTION: HAIRIS DESCRIPTION: Finding the relationship between two coordinate systems using pairs of measurements of the coordinates of a number of points in both systems is a classic photogrammetric task. The transformation between two Cartesian coordinate systems can be thought of as the result of a rigid-body motion and can, thus, be decomposed into a rotation and a translation. Suppose that we have a pair of images in the same scale (same pixel size with respect to the scene), and the existence of a translation and/or rotation difference between the two images, where one of them is static (image 1) and the other (image 2) is to be registered onto the static image. Assuming that are the
coordinates of the static image and are the (Pixel, Line) pair of the image to be
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registered. The transformation may be written as where the origin is considered to be the upper left corner of the static image, is the orientation difference, and is the shift between the two images. The proposed methodology of automatic image registration is schematically represented in Fig. 1. It begins with a pre-processing stage in order to reduce unnecessary detail on the images content, important for the subsequent histogram-based image segmentation phase (which includes a relaxation parameter). The objects extracted from the segmentation stage are characterized and matched according to some related properties, which finally allows for the statistically-based rotation and translation parameters estimation. In the following, the several steps involved in HAIRIS are explained, where the main objective is to estimate. PREPROCESSING: Too much detail on the pixel domain may lead to undesirable segmentation results. Therefore, it is advisable an image Enhancement step prior further processing. By image enhancement (which is itself a largely subjective process), it is intended to obtain an image with less detail than the original version, nearest to the object identification which is performed by the human eye. Although typically more mathematical and complex, restoration algorithms may provide the exploitation of the detailed characteristics of an image and its degradation. Despite the main purpose of image restoration methods is to model and remove the degradation, these methods may also be used with other purposes. Since with image segmentation it is intended to extract objects (in particular their boundaries), one may view the image
objects which have some texture as a kind of degradation. Therefore, it is intended to remove that degradation, which is assumed to be additive random noise. The Wiener filter is one of the most used filters under the scope of image restoration methods. However, it may also be used for image enhancement, with the aim of reducing the detail on an image, since it is typically a low pass filter and consequently induces a significant blurring effect. Its frequency response is given by where stands for the original image power spectra and for the additive random noise power spectra. Although one might be interested in inducing some blurring on the image, the use of a fixed (space-invariant) filter throughout the image may decrease the clearness of the objects boundaries. Therefore, an adaptive image restoration is required. A pixel-by-pixel processing approach may become quite computationally expensive, in opposition to a sub image-by-sub image processing where we divide the image into a certain number of tiles. The latter is typically considered for sub images with size between 8X8 and 32X32 pixels. However, since the objective of the Wiener filter employment is different from restoration, it is advisable to consider the conservative smallest possible square tile (beyond a single pixel) size of 3X3 pixels. Although this latter approach might induce the socalled blocking effect, it may be ignored for images with low SNR. Recalling the additive random noise, we generally have no a priori information, which may be overcome by considering measured features such as the local variance, providing the determination
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of the presence of significant highfrequency details. Since we are interested in delineating the objects boundaries, an edge-sensitive adaptive image restoration version of the Wiener filter is adequate. This method is based upon the idea of reducing more noise near edges without additional edge blurring through a cascade of 1-D adaptive filters. Let Ti [.](1<=i<=N) represent a 1-D (space variant) filter, where N is four and represents the four directions corresponding to the angles of 0deg, 45deg, 90deg, and 135deg. Then, these operators are sequentially applied, which lead to an improvement over the performance of some 2-D adaptive restoration algorithms, and to typically less computational requirements. Additionally, in order to overcome significant differences between the histograms of the images to be registered, an histogram equalization of image 2 using the histogram counts of image 1 is performed, prior to the application of the Wiener filter. In this way, the Wiener filtering on image 2 allows both for the reduction of the image detail, as well as to the smoothing of the histogram, which becomes spiky due to the histogram equalization step.
HISTOGRAM BASED SEGMENTATION:
the sequence of the consecutive slopes, where M+1 is the number of histogram levels ( M=255 for an 8-b image). The idea behind this approach is to choose an adequate threshold for considering whether or not one is in the presence of a mode, which is characterized by a significant increase and/or decrease on the slopes sequence. In Fig. , the histogram of the image in Fig is shown, where roughly seven modes are visible. Also in the same figure, the consecutive slopes of the histogram are shown in fig 6.3, where each global transition from positive slopes to negative slopes is associated to a mode on the histogram.
MODE DELINEATION AND IMAGE SEGMENTATION: The method used for mode delineation is based upon the analysis of the consecutive slopes of the histogram. Let x (m) be the image histogram counts m=0 ., M and
(a) Input Image (b) Histogram of the image
y n=1..,M
(n)=x(n)-x(n-1)
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a class. Then, for each class, those pixels which are 4-connected are considering as belonging to the same object, resulting in the final segmentation of the image. In some cases, a significant amount of no data (DN=0orDN=255 for unsigned 8-b images) may be present, which can mask in some way the histogram shape. Therefore, those corresponding pixels should be discarded prior to the representation of the image histogram. CHARACTERIZATION OF THE EXTRACTED OBJECTS: The extracted objects at the segmentation stage are characterized by four attributes which allow for their adequate morphological description: area (Area), perimeter (Perim), axis ratio (ARat) and fractal dimension (Db) . The attribute area is merely obtained by the number of pixels which form an object, whereas the perimeter is obtained by calculating the distance between each adjoining pair of pixels around the border of the region. These two attributes allow for the evaluation of an object with respect to its size and compactness, respectively. The major axis length corresponds to the major axis length of the ellipse that has the same normalized second central moments as the object, from which it may be also obtained the minor axis length. The ratio between the major and the minor axis length lead to the attribute (axis ratio). The attribute allows for the characterization of the object according to its narrow or wide nature. Although the three previously described measures comprise the most general aspects of an object characterization, several uncertainties would still persist on the objects matching stage. Therefore, there is the need for considering a complementary attribute
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Slopes of the histogram A relaxation parameter () is considered on the mode delineation, which in theory is a continuous parameter, defined on the space [0, 1], and has to pass through a discretization process in practice. The inclusion of this parameter leads to the obtention of several different segmentation results, which allows for the subsequent stages of the proposed methodology to be more robust. The relaxation parameter () corresponds to the proportion of the height of the histogramconsidered to correspond to the highest modefor which below this value, the mode is to be considered as a flat region. In this way, the method becomes much more useful and adaptable to a large variety of situations. The common methods of merely identifying a mode correspond to selecting the null value for (). Once the modes and flat regions are identified for each value of (), the image may be segmented considering each interval (either a mode or a flat region) as
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which considers the particular complexity nature of an object shape: the fractal dimension. Fractal dimension is one among several notions of dimension proposed by mathematicians. In this work, the box-counting dimension Db one of the special forms of Mandelbrots fractal dimension was the considered fractal dimension. It generally consists on the slope of a straight line, fitted to a scatter plot with log(N(s)) and log (1/s) on the vertical and horizontal axis, respectively, where is the mesh size of the grid overlaid on the object and N is the number of grid boxes which contain pixels of the object. The four previously described attributes are used for the later stage of objects matching. These four attributes are expected to be similar for corresponding objects. As stated at the beginning of HAIRIS description, it is assumed that the pair of images differ with respect to rotation ( ) and translation ( x and y). Therefore, in order to allow for the registration of the pair of images, there is the need to have an orientation and positioning indicators. Regarding orientation, for each extracted object, the angle between the x-axis and the major axis of the ellipse that has the same second-moments as the object is stored. With respect to translation, the centroid of each object (the center of mass of the object) is also stored. MATCHING: The matching step begins with the evaluation of a cost function, between every possible two-by-two combination of objects obtained by the segmentation of the two images, for every possible combination of the values considered for both images. This leads to a matrix with rows and columns, where and correspond to the number of extracted objects from images 1 and 2, respectively. The cost
function, evaluated for the values of the properties of the objects from images 1 and 2, is defined as follows:
Where and are the average of each property for images 1 and 2 values. With defined in this manner, it allows for a normalized sum of the considered properties, and consequently to the sum of them. Then, the values are represented in the form of box plots, with the image which led to the lower number of segmented objects corresponding to the horizontal (categorical) axis. A valid matching between two objects should lead to the lower values of, sufficiently far from the majority. This can be statistically evaluated through the outlier detection criterion used in the box plots representation, where a point is considered an outlier (regarding the smaller values) if it is smaller than, where and are the first and third quartiles, respectively. Although is typically considered as 1.5, in this step the more flexible value of 1 is required (also commonly used in practice), in order to reduce the loss of eventual matching candidates. This procedure of outlier detection is applied to each object of the image in the horizontal axis. Segment of the images shown in Fig. where (a) corresponds to band 1 and (b) to band 2 with the simulated shift. Superimposed (in white) are the boundaries of two objects obtained from the segmentation stage, which have been matched. The attributes values from the
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object in (a.1) are (1759, 2.66, 647.7, 1.12) and from the object in (b.1) are (1685, 2.67, 555.2, 1.09).
allows for the detection of a modal class, restricting the set of possible values for rotation. Then, among these rotation candidates, a robust strategy of finding is performed, through considering the frequencies of the rotation candidates, and finding the rotation value which absolute frequency corresponds to the higher outlier, according to the procedure of box plot outliers detection previously described. This procedure leads to a robust estimation . TRANSLATION ESTIMATION: Once is obtained, only the initial matching candidates which correspond to the obtained rotation are considered. Then, a similar procedure as that followed in the rotation estimation is considered for obtaining (x and y). CONCLUSION A large variety of automatic image registration methods can be found. In several applications, the registration model only assumes rotation and translation, where the registration of satellite images is an example. In this paper, a new approach for automatic image registration through Histogram-based image segmentation (HAIRIS) is proposed, The presented images were contrast stretched in order to allow for a better visualization. Clear advantages by joining these two main areas of image processing. Since HAIRIS does not require any search interval either for rotation or translation, it is a fully automatic procedure.
(a) Image (b) Segment of the image ROTATION ESTIMATION: The rotation and translation are determined on a statistical basis. Given the set of matching objects candidates, the histogram of the extracted objects orientation differences is represented. This
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AUTOMATED MANAGEMENT OF HOME APPLIANCES USING RTOS

B.JAI KUMAR #1 & P.MAHENDRAN #2 II-ME-EMBEDDED SYSTEM TECHNOLOGIES#1 ASSISTANT PROFESSOR / DEPARTMENT OF ECE#2 Email:- jaikumarbecse@gmail.com#1 Email:-tm_dav@yahoo.com #2 KSR COLLEGE OF ENGINEERING TIRUCHENGODE, NAMAKKAL, TAMILNADU
Abstract To develop a Real Time Operating System for managing embedded devices used in home and building automation. The embedded software applications require performing a task which is efficiently achieved by dividing the global task into many smaller subtasks. This presents a Distributed Operating System (DOS) based on the Service-Oriented Architecture (SOA) to manage all embedded devices in a home network at high level of interoperability. Each subtask apart from executing its own task, services a part of the global task. When the consequences for failure are expensive or, worse, life threatening, VxWorks RTOS is the only choice. Wireless sensor networks have become an essential part of home and building automation, especially for energy management and health monitoring. The concept of dynamic assignment of priorities to interrupts is discussed which reduces the time delay for a lower priority task which under some circumstances becomes a higher priority task. Slicing of interrupt timings is also discussed which can be used to improve the performance. The highest priority task is serviced more number of times and with lesser time period. Hence it need not wait for the slack time of other previously higher priority interrupts. Wireless sensor networks represent a promising technology especially in home and building automation. These networks have nowadays many applications in energy management, security and health monitoring. Index TermsService Oriented Architecture, Distributed Operating System, Real Time Operating System(RTOS), Wireless Sensor Networks.
priority task is serviced more number of times and with lesser time period. Hence it need not wait for the slack time of other previously higher priority interrupts. Wireless sensor networks play a vital role in home and building automation, for energy management system and health monitoring. Energy meter reading is given to ARM processor by using an IR sensor fixed to the meter to detect the number of times the metal plate in it rotates and cuts the IR rays between the IR-Tx and Rx. Voltage sensor and current sensor are interfaced to microcontroller the capacitor bank is powered and the capacitor banks are used to power the uninterrupted working of the home and building. Everything will be monitored in LCD. If any human appeared in room, then automatically load1 will be ON by using PIR sensor to save the energy. If temperature getting more than normal then AC machine automatically getting adjusted.
I. INTRODUCTION VxWorks is the RTOS that powers more than 1 billion real-time systems across the globe, from small consumer products to commercial airliners. When the consequences for failure are expensive or, worse, life threatening, VxWorks RTOS is the only choice. After 30 years of RTOS leadership and consistently successful deployments, Wind River is the name you know you can trust. Slicing of interrupt timings is also discussed which can be used to improve the performance .the highest
Fig 1.Block Diagram of System
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Here we are using scheduling method to get the real time output and accuracy using PC. Keyboard is used for manual control this tendency will increase especially with the emerging technology that requires more intelligence in managing the energy that is consumed and produced by the home itself in order to enable the integration of smart electrical current counters, sensors and other related appliances. The networked embedded devices in home and building applications can be classified into two classes. The first class is embedded devices that have an Ethernet interface with enough resources to run the standard TCP/IP stack. These devices are called Service-Oriented Architecture (SOA)-ready devices and can be directly integrated with IP-based networks. The second class is the resourceconstrained embedded devices, which are based on a network standard different from Ethernet network standards like IEEE 802.15.4. These devices have minimal resources and small size in order to enhance the mobility requirement. These devices are not IPready in their design and do not have enough resources to run the standard TCP/IP network stack. They are usually called SOA not-ready devices.
Fig 3. Diagram for SOA-DOS Implementation A. Devices Monitor This represents a user interface to monitor and analyze the data and events coming from embedded layer. The devices data will be filled with the data received from the embedded devices upon GET requests from clients or receiving events from event driven embedded devices. The sensing data and event data can be very useful for auditing, service quality management and performance analysis. B. Devices Management The devices management is based on the devices database and has user interfaces for configuring the information of all devices in the embedded layer like access information (IPv4, IPV6), name, location, software version, and other additional information. C. Services Management This is responsible for publishing the services of the devices in the embedded layer to clients in the Internet. It provides the required information about the capabilities of these devices and how they can be accessed and used. It is based on the services database which contains the service description files for all embedded devices in the embedded layer. The SOA-DOS provides two types of service discovery to discover the services of the embedded devices: dynamic and static service discovery. Using dynamic service discovery requires enabling the dynamic service description in the WSDiscovery module on the configured embedded device. In this case the WS-Discovery will send a service description file in JSON format including the description of all device services to the services management module in SOA-DOS. This file can be sent each time the device is being turned on or upon receiving a discovery request from the SOA-DOS.
Fig 2. General Flow of entire process Our SOA-based Distributed Operating System (SOA-DOS) proposes a feasible and more realistic model for managing all embedded devices in home or building environment from both classes SOA-ready and SOA-not ready devices II. SOA -DOS IMPLEMENTATION The SOA-DOS manages all tasks concerning the communication between the different embedded devices in a home network and the access to the services of these devices from Internet
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Using the static service discovery requires disabling the dynamic service description in WS-Discovery. In this case the administrator of the SOA-DOS must insert the service description of the device's services into the services database in order to enable the services management to publish. The benefit of using the static service discovery instead of the dynamic one is decreasing the network overhead in embedded layer and that will improve the reliability and the quality of the service. Furthermore the services management in SOA-DOS can publish these services in different format than JSON like XML or WSDL D. Events Management This module is used to configure and manage the relationships between event senders and their listeners. Simply the module, upon receiving an event, will save its data and notify all listeners that are subscribed to this event in the events data. Generally, each embedded device or client in Internet has to subscribe to its interesting events in the SOADOS in order to receive notifications about them. This method is called asynchronous method, and it is more effective than the polling method in terms of network overhead and event sending time. The subscription to events can be also manually configured for some devices by the administrator through configuring event relationships between these embedded devices according to user requirements. The Event Management listens on a specific port in order to receive the POST requests that contain the events data in JSON format E. Queue Management and dispatcher Accessing embedded devices in a network based on a networking protocol different from that used in the Ethernet requires an adaptation or transformation. This layer represents an intrinsic interface by integrating embedded devices into Internet, especially wireless sensors with limited resources. Furthermore most of the adapted IP protocols for wireless sensor networks only support a limited number of multiple simultaneous connections. For example the IP protocol, which is the dominant protocol in wireless sensor networks enabled for IP-based networking, needs to determine the number of the simultaneous connections at compile time. Every new connection requires its own static memory. There is a limit for the number of supported connections and if the number of simultaneous incoming connections exceeds this limit, a problem of refusing the new connection will raise and sometimes the connections which are
already in use will freeze. This represents a critical problem that decreases the reliability of the integrated communication. That means the actual implementations of adapted IP protocols for wireless sensor networks do not handle efficiently with multiple simultaneous connections.
Fig 4. Diagram for Queue and Dispatcher Service We took this point of failure into consideration when designing SOA-DOS by implementing a queue management and dispatcher in order to organize multiple simultaneous user requests to one of devices services. In SOA-DOS each embedded device has a queue and a dispatcher to dispatch the queued requests to the suitable gateway in the layer by calling the requester F. Cache Management The caching is an optional mechanism in the client-server model, and it is well-known in Internet. Simply the cache is a part of memory to save the last requested information in order to reuse this information on demand quickly by the same requested client or by other clients during a specific period of time. Applying the caching model helps in reducing the load on the server, because the server does not need to reprocess and prepare the response's data. The caching concept will be very useful in accessing a wireless sensor network, especially if the state of the requested resources on these embedded devices slowly or rarely changes. In our SOA-DOS we adapted the caching concept according to our layered architecture
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In first scheme, all the subtasks are in a sequential infinite loop, where each subtask gets executed only once in an iteration of while loop. The ISRs are very small as they are used only to set flags which are checked in the super loop. This architecture is not efficient as an interrupt flag once checked in the super loop, will be checked only after all the other interrupt flags have been checked or/and serviced if required. Every task, immaterial of its criticality (priority), is treated equally because of which a potentially higher priority task has to wait for the other tasks. The servicing of the interrupt flag also depends on the current position of program counter. Fig 5.Diagram of Cache Allocation In the first one the cache is located on the embedded devices, and each embedded device has to validate whether the last data in cache still be valid or not, depending on the request time coming from the client and the device's current time. This solution will not be efficient for a wireless sensor network, because it will increase the request size by including the cache's control parameters which leads to increase network overhead and power consumption. Furthermore this solution needs time synchronization between the client and the requested device. The second caching possibility depends on locating the cache in SOA-DOS layer. In this case the caching module in the SOA-DOS validates whether to get the response from the SOA-DOS's cache or from the embedded device depending on the client's request time and the time of inserting the last requested service data for this device in the cache. When the SOA-DOS answers the client from its cache, there will be no communication with the embedded layer, thus leads to decrease response time, network overhead and power consumption in the embedded layer. The third possibility is based on locating the cache on the client's side, and in this case the client takes over the cache validating process. The disadvantage of this method is the lack of interoperability, because the client should not only know the service's URL of the device but also needs more information in order to adjust the right maximum cache time, which usually depends on how often the sensing data on the embedded device change. A long caching time may lead to send old or wrong data to the client, which will in turn decrease the reliability of the whole communication. III. Real Time Operating System A. High-Performance Real-time Kernel Facilities The VxWorks kernel, wind, includes multitasking with preemptive priority scheduling, inter task synchronization and communications facilities, interrupt handling support, watchdog timers, and memory management. B. C++ Development Support In addition to general C++ support including the iostream library and the standard template library, the optional component Wind Foundation Classes adds the following C++ object libraries: VxWorks Wrapper Class library Tools.h++ library from Rogue Wave The VxWorks multitasking kernel, wind, uses interrupt-driven, priority-based task scheduling. It features fast context switch times and low interrupt latency. Under VxWorks, any subroutine can be spawned as a separate task, with its own context and stack. Other basic task control facilities allow tasks to be suspended, resumed, deleted, delayed, and moved in priority. C. Interrupt Handling Support VxWorks supplies routines for handling hardware interrupts and software traps without having to resort to assembly language coding. Routines are provided to connect C routines to hardware interrupt vectors, and to manipulate the processor interrupt level.
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Fig 6. RTOS system with ISR Services
Fig 8. Flow Chart for the main program
VI. CONCLUSION Fig 7. Loop Execution For ISR Our proposed SOA-based distributed operating system represents a user-friendly model for managing all distributed embedded devices in a heterogeneous network environment like in home network. It is especially targeting deep resourceconstrained embedded devices like in wireless sensor networks, enabling them to integrate into Internet at a high level of interoperability. Designing a universal SOA-based operating system at the level of home or other local environments that allows just one universal Internet connection seems to be a feasible and cost realistic solution. Using a SOA-based distributed operating system provides valuable benefits for managing embedded networks. In heterogeneous environment like Industries, Homes, Hospitals use a specific OS to perform a task. The designing of a OS will take more time, complexity. Certain OS results in high cost too. Instead of designing an OS, it is very easy to develop a RTOS. It will take less time, less money compared to an OS. Design of RTOS, developed using Vxworks. REFERENCES
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A. Selman, R.Moeller. SOA Distributed Operating System for Managing Embedded Devices in Home and Building Automation.2011,03 March 2011. A. Dunkels. "Full TCP/IP for 8-Bit Architectures". Proceedings of the first International Conference on Mobile Applications, Systems and Services (MOBISYS2003), May 2003. G. Mulligan. The 6lowpan architecture. In Proceedings of the 4th workshop on Embedded networked sensors, New York, USA, 2007. E. Zeeb, A. Bobek and F. Golatowski. Service-oriented architecture for embedded systems using devices profile for web services. In 2nd International IEEE Workshop on SOCNE07, 2007. M. Durvy, J. Abeille, P. Wetterwald, C. OFlynn, B. Leverett,E. Gnoske, M. Vidales, G. Mulligan, N. Tsiftes, N. Finne, and A. Dunkels. Making Sensor Networks IPv6 Ready. In SenSys, 2008. A. Sleman, R. Moeller, "Integration of Wireless Sensor Network Services into other Home and Industrial networks", in International Conference ICTTA, 2008. B. Priyantha, A. Kansal, M. Goraczko, and F. Zhao. Tiny web services: design and implementation of interoperable and evolvable sensor networks. In Proceedings of SenSys, 2008. T. Kindberg, J. Barton, J. Morgan, G. Becker, D. Caswell,P. Debaty, G. Gopal, M. Frid, V. Krishnan, H. Morris, J. Schettino, B. Serra, and M. Spasojevic. People, places, things: web presence for the real world. Mob. Netw. Appl., 2002. D. Guinard and V Trifa. Towards the web of things: Web mashups for embedded devices. In International World Wide Web Conference, Madrid, Spain, 2009. Adam Dunkels, Bjrn Grnvall, and Thiemo Voigt. Contiki a Lightweight and Flexible Operating System for Tiny Networked
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Sensors. In Proceedings of the IEEE Emnets, USA, 2004. D. Crockford. The application/json media type for JavaScript Object Notation (JSON). The Internet Engineering Task Force (IETF), Network Working Group, RFC 4627, July 2006. S. Chakrabarti , E. Nordmark, IPv6 LoWPAN Neighbor Discovery and Addressing Choices , March 2010. J. Romkey, RFC 1055. A NONSTANDARD FOR TRANSMISSION OF IP DATAGRAMS OVER SERIAL LINES: SLIP, June l988. C.E.Otero, A.Velazquez, I.Kostanic, C.Subramanian, J.Pinelli, L. Buist, RealTime Monitoring of Hurricane Winds using Wireless and Sensor Technology, Journal of Computers, Vol. 4, Nov 2009. X. Li, and W. Zhang, The design and implementation of home networks systems using OSGi compliant middleware, IEEE Transactions on Consumer Electronics, vol. 50, no. 2, pp. 528-534, May 2004. R. D. Redondo, A. F. Villas, M. Ramos, J. J. Pazos Arias, and M. Rey Lpez, Enhancing residential gateways: OSGi service composition, IEEE Transactions on Consumer Electronics, vol. 53, no. 1, pp. 8795, Feb. 2007. C. Y. Leong, A. R. Ramli and T. Perumal, "A rule-based framework for heterogeneous subsystems management in smart home environment", IEEE Transactions on Consumer Electronics, vol.55, no.3, pp.12081213, August 2009. T. Perumal, A. R. Ramli, and C. Y. Leong, "Design and implementation of SOAP-based residential management for smart home systems", IEEE Transactions on Consumer Electronics, vol. 54, pp. 453-459, 2008.
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MODELING of THREE PHASE SELF EXCITED INDUCTION GENERATOR

T. Gopinath*, P. Vetrivellan** * Research Scholar, **Assistant professor Department of EEE Jayam College of Engineering and Technology, Dharmapuri - 636 813, Tamilnadu, India EMAIL ID: tgopiece@gmail.com
Abstract - Dynamic characteristics assessment of three phase self excited induction generator is one of the main issue in isolated applications as it proves its importance in recent years. The transient characteristics of SEIG has important role to define its better applicability. In this paper a generalized state-space dynamic model of a three phase SEIG has been developed using d-q variables in stationary reference frame for transient analysis. The proposed model for induction generator, load and excitation using state space approach can handle variable prime mover speed and various transient conditions. Also the effect of variation of excitation capacitance on system is analyzed. The equation developed has been simulated using powerful software MATLAB/SIMULINK and its responses justify the proposed model. Keywords: Transient characteristics, capacitance, prime mover speed, variable load. Excitation
Rs
: Stator resistance per phase in ohms
Rr
: Rotor resistance per phase referred to stator in ohms
Xls Xlr C
: stator leakage reactance per phase : Rotor leakage reactance per phase : minimum value of self Excitation Capacitance
R Wr
: load resistance per phase in ohms : rotor speed in rad/sec
NOMENCLATURE Ild, Ilq : d-q axes load current per phase Vsd, Vrd isd, ird Vsq, Vrq isq, irq Lm Lr, Ls Im Te P L : Stator, rotor d-axis voltages : Stator, rotor d-axis currents : Stator, rotor q-axis voltages : Stator, rotor q-axis currents : Magnetizing Inductance : Rotor, Stator Inductances : Magnetizing current : Electromagnetic Torque : Number of poles : Load Inductance per Phase in Henry I. INTRODUCTION It is well known that the three phase self excited induction machine can be made to work as a selfexcited induction generator [1, 2], provided capacitance should have sufficient charge to provide necessary initial magnetizing current. In an externally driven three phase induction motor, if a three phase capacitor bank is connected across its stator terminals, an EMF is induced in the machine windings due to the self excitation provided by the capacitors. The magnetizing requirement of the machine is supplied by the capacitors. For self Vld, Vlq: d-q axes excitation voltage per phase icd, icq : d-q axes capacitor currents per phase
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excitation to occur, the following two conditions must be satisfied:i. The rotor should have sufficient residual magnetism. ii. The three capacitor bank should be of sufficient value. If an appropriate capacitor bank is connected across the terminals of an externally driven induction machine and if the rotor has sufficient residual magnetism, an EMF is induced in the machine windings due to the excitation provided by the capacitor. The EMF if sufficient would circulate leading currents in the capacitors. The flux produced due to these currents would assist the residual magnetism. This would increase the machine flux and larger EMF will be induced. This in turn increases the currents and the flux. The induced voltage and current will continue to rise until the VAR supplied by the capacitor is balanced by the VAR demanded by the machine, a condition which is essentially decided by the saturation of the magnetic circuit. This process is cumulative and the induced voltage keeps on riding until saturation is reached. To start with transient analysis, the dynamic modeling of induction motor has been used which further converted into induction generator [1, 4, 9]. Magnetizing inductance is the main factor for voltage buildup and stabilization of generated voltage for unloaded and loaded conditions. The dynamic Model of Self Excited Induction Generator is helpful to analyze all characteristic especially dynamic characteristics. Different constraints conditions: 1. for analyzing transient
5.
and rated load by keeping rotor speed above synchronous speed and by keeping capacitance constant and the rotor speed is varied above synchronous speed. The resultant voltage and current waveforms has been observed. The transient periods of voltage build up and voltage collapses has been observed when switching periods between the excitation and application of load varies.
An uncontrolled self excited induction generator shows considerable variation in its terminal voltage, degree of saturation and output frequency under varying load conditions. It is convenient to represent the circuit model in terms of base frequency for the analysis. The per-phase, equivalent circuit of generator connected to capacitor of capacitance the excitation VAR. steady-state, stator-referred a self-excited induction a load is given below. A Co is connected to provide
Fig 1. Stator referred circuit model normalized to base Frequency
2.
3.
4.
The machine is run as an induction motor and then increase the speed above synchronous speed to make it as a generator, after complete excitation the variation of generated voltages observed by applications of various loads. The machine is started as induction generator with the rated load and transient response is observed with various excitation and rotor speed. The machine is started as induction generator with no load and the voltage variations has been observed by applying the load after complete excitation. The analysis has been extended to variation of the excitation capacitance under no load
II. GENERALIZED SEIG MODELLING The d and q axis current are given by the set of differential equations [1, 3] shown below,
... (2.1)
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(2.8) Where, ] ... 2.2) (2.9) (2.10) From the above equations, ... (2.3) (2.11) (2.12) Equations (5.24) and (5.25) represents the d-q axes load voltages and currents, (2.13) (2.14)
] ..(2.4) Where K = The variation of the magnetizing inductance is the main factor in the dynamics of the voltage build up and stabilization in SEIG. The non linear relationship between magnetizing inductance (Lm) and magnetizing current (Im) is given as, (2.5)
III. SIMULATION OF SELF EXCITED INDUCTION GENERATOR Simulation and the equations described above has been implemented in MATLAB/SIMULINK block sets. The current equations have been implemented in subsystem Induction Generator whose outputs are currents in d & q axis. The load and excitation model is implemented in subsystem Excitation and Load as shown in fig. 3.2 & 3.3 by using equations (2.7) to (2.14). Further these currents are the function of constants viz. stator and rotor inductances, resistances, speed, excitation capacitance and load impedance.
(2.6)
The following equations represents the self excitation capacitor currents and voltages in d-q axes representation, (2.7)
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Fig.3.1 SIMULINK model of Self Excited Induction Generator
Fig.3.2 Excitation model
analysis of the generalized per phase equivalent circuit, (in which all parameters are divided by the base frequency), of the three phase induction machine and either the loop impedance or the nodal admittance concept is applied. When the loop impedance concept is used in the analysis of the equivalent circuit, the process of self excitation is satisfied by equating the sum of the loop impedance's to zero. Then both the real and imaginary parts of the total impedance are equated to zero, resulting in two nonlinear simultaneous equations in both self-excitation capacitor reactance and frequency. The degrees of both the equations are two and six in the case of R-L load respectively. Using the nodal admittance concept [8] and by equating the real and imaginary parts of the total admittance to zero, a sixth order polynomial in the per unit frequency is obtained after a series of algebraic manipulations by decoupling the load and excitation capacitor branches. From fig 3.2, the loop equation for the current I can be written as IZ = 0 . (4.1)
Where Z is the net loop impedance given by
. (4.2) Since under steady state excitation the current is not equal to zero, it follows from the above equation that Z=0 or both real and imaginary parts of Z are zeros. Considering Xm = Xsmax, the equation obtained from the real part is, . (4.3) Similarly the equation obtained from the imaginary part is, . (4.4)
Fig. 3.3 Load model
IV. DETERMINATION OF CAPACITANCE There are two main methods used in the calculation of the minimum capacitance necessary for self-excitation. The first method is based on the generalized machine theory in which the characteristic equation of the operational impedance matrix has to be solved numerically for its roots. In this method the characteristic equation which represents the self-excitation process is a tenth order differential equation for inductive and capacitive loads, while an eighth order differential equation results for resistive load conditions. The second method is based on the
Equating the above equations the following fourth order equation given below is obtained,
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. (4.5) Where are positive constants.
Let {Fi, i 4} be the set of positive real roots of the equation and {Ci , i 4} be the corresponding set of positive capacitor values. Since all these values of C are sufficient to guarantee self-excitation of the induction generator, it follows that the minimum capacitor value required is given by Cmin = min {Ci, i 4} .(4.6)
If the eqn. (4.5) has no real roots, then no excitation is possible. In fact, there is a minimum speed value, below which the equation (4.5) has no real roots. Correspondingly, no excitation is possible. Substituting the given values of the machine, the values of F obtained are 0.4965 and 1.084 for which the values of capacitances obtained are 657F and 45.6 F respectively. The degree of eqn.4.5 determines the number of capacitor values from which the minimum value is selected. V. SIMULATION RESULTS The figure given below shows the simulated responses of the studied induction machine operated from an induction-motor mode to an IG mode. The stator phase current at starting is of high vale but latter it settles downs to a very small steady value.
Fig.5 (a). Stator phase current
Fig 5(b) Stator phase current (ias)
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Fig. 5.3 Variation of Torque
VI. CONCLUSION This paper has presented generalized state space dynamic modeling of three phase self excited induction generator. With this model it is possible to isolate induction generator, excitation and load. This feature is guaranteed by the separate parameter representation of the machine model, the self excitation bank of the capacitor and the load. The main advantages of this approach are (i) representation of SEIG in the form of classical state equation (ii) separation of machine parameters from the self excitation capacitors from the load parameters, the transient analysis can be effectively analyzed (iii) this model works effectively even with the consideration of main and cross flux saturation and gives better result. APPENDIX Generator Rating and Parameters Rated Power Rated Line to Line Voltage Rated Frequency Stator Resistance, Rs ohms Stator Leakage Reactance, Xls ohms
Fig. 5.2 Rotor Speed
Fig.5.1 Stator phase voltages
The rotor speed starts from 0 rpm at t=0.0s and approaches to 1499 rpm at t=0.5 S. the rotor speed changes to be 1550 rpm at t= 1.5s. The electrical torque changes to be negative at t= 1.5s when the machine acts as an IG. Fig. 5.2 & 5.3 plots the dynamic variation of rotor speed and Te during various modes of operation.
5.5 HP 400V 50 Hz 0.063 0.163 0.1179
Rotor Resistance, Rr ohms
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Rotor Leakage Reactance, Xlr ohms Number of Poles, P 4
0.163
6)
REFERENCES 1) S.S. Murthy, C. Nagamani, K.V.V. Satyanarayana, Studies of the use of conventional induction motors as self excited induction generators, IEEE transactions on energy conversion vol. 3, No 4, December 1998. 2) R. Chaturvedi, S.S. Murthy, Use of conventional induction motor as a wind driven self excited induction generator for autonomous operation, 1998 IEEE. 3) Avinash kishore, G. Satish kumar Dynamic modeling and analysis of three phase self excited induction generator using generalised state space approach International symposium on power electronics. 4) P.C. Krause, Analysis of Electric Machinery, McGraw hill Book Company, 1986 5) Bhim Singh, Madhusudan Singh Transient Performance of Series Compensated Three-Phase Self-Excited
7)
8)
9)
10)
induction Generator Feeding Dynamic Loads IEEE Transactions on Industry Applications, Vol. 46, July/August 2010 S.N. Mahato, M.P. Sharma, S.P. Singh Determination Of Minimum And Maximum Capacitances Of A SelfRegulated Single-Phase Induction Generator Using A Three-Phase Winding Proceedings of India International Conference on Power Electronics 2006 B.Venkatesa perumal and Jayanta K.Chaterjee Voltage and frequency control of a standalone wind electric generation using generalized impedance controller IEEE transactions on energy conservation, Vol. 23, June 2008 Kh Al Jabri, A I Alolah, Capacitance requirement for isolated self excited induction generator, IEEE proceedings, Vol. 137, Pt. B. No. 3, March 1990 L. Sridhar, Bhim Singh, C. S. Jha, Transient performance of the self regulated short shunt self excited induction generator, IEEE transactions on energy conversion vol. 10, No. 2, June 1995. J. L. Bhattacharya, J. L. Woodward, Excitation Balancing of a self excited induction generator for maximum power output, IEE proceedings, Vol. 135, Pt. c, No. March 1998.
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VLSI Architecture Design for Analysis of Fast Locking ADPLL via Feed Forward Compensation Algorithm
S.ARUL MURUGAN #1 & T.M.SATHISH KUMAR#2
DEPARTMENT OF ECE Email:- snarul@live.com, 9943201055#1 Email:- ed.samuvel27@gmail.com, 9843499123 #2 K.S.R.COLLEGE OF ENGINEERING
Abstract-- The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loop is commonly used to generate well-timed on-chip clocks in high performance digital systems. Modern wireless communication systems employ Phase Locked Loop mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. A fast locking all-digital phaselocked loop (ADPLL) via feed-forward compensation technique is proposed in this Paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. The proposed ADPLL can easily be ported to different processes in a short time. It can reduce the design time, Locking time, Power Consumption and wide tunable frequency range of the ADPLL, making it very suitable for system-onchip applications. Keywords:- All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), feed-forward compensation technique, frequency Divider (DIV).
widely used in modern electronic devices, with output frequencies from a fraction of an Hz to many GHz. Basically, analog approaches are adopted to design PLLs. But it is difficult to integrate an analog PLL into a noisy SoC environment so that we are moving to ADPLL. Comparing with PLL, ADPLL have higher immunity to switching noise and then easy to implement in electronic design automation tools (EDA). It helps to reduce designing time gradually. In the ADPLL voltage control oscillator (VCO) replaced by numerical control oscillator (NCO) can be used. The frequency of the numerical controlled oscillator (NCO) is tuned by digital codes. So ADPLLs are much easier to achieve fast frequency acquisitions. There are several frequency search algorithms used in ADPLLs. One of the typical methods is adjusting the PLLs loop Band width dynamically the locking time is directly proportional to the initial frequency difference between the reference clock and the divided clock, and inversely proportional to the loop bandwidth of the PLL. In when the phase error between the reference clock and the divided clock is large, the PLL increases the loop bandwidth and achieves fast locking. Conversely, when the phase error is small, the PLL decreases the loop bandwidth and minimizes the output jitter. But this method will increase the complexity of the PLL circuits. The PLL must be stable over a wide range of the PLLs loop bandwidth, and must tolerate the errors in the prediction of the loops parameters such as the oscillator gain.
I. INTRODUCTION:Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to recover a signal from a noisy communication channel, generate stable frequencies at a multiple of an input frequency (frequency synthesis), or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked loop building block, the technique is
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II. STRUCTURE OF THE PROPOSED ADPLL:
In (1), replacing F1 with M/2, and using Wlocked instead of W1, then Wlocked can be calculated by (2),
Wlocked W2 K f M F2 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (2) From (2), it is seen that the ADPLL with the proposed algorithm can achieve a fast frequency locking when the values W2 and Kf *(M/2-F2) are known. The code W2 is generated by the ADPLL itself. The value of M is set to the ADPLL before the ADPLL works, and the value of F2 is sensed by the MDIV, so these values can be obtained easily. The value which is the most difficult to obtain is Kf,, it is seen that the parameter Kf is PVT dependent. So it is better to recalculate the value of Kf for every initialization of the ADPLL. III. OPERATION OF THE PROPOSED ADPLL: The operation of the proposed ADPLL is based on the two operating modes, Frequency Acquisition Mode and Phase Acquisition Mode. 1. Frequency Acquisition Mode:In the frequency acquisition mode consists of three modules. In this mode, the feed-forward compensation structure which includes the MDIV, LC, and DCO is activated.
Fig:1 Overall Block Diagram
Our overall system consists of six modules, which are Phase/Frequency detector (PFD), Enhanced Modified divider, loop control (MDIV), Digital control oscillator (DCO), phase to digitalized mode (P2D) and Digital loop filter. The code W is assigned to tune the DCO, the DCO frequency is f. F is the corresponding value sensed by the Modified Frequency Divider. It counts by the rising edge of the DCO clock when the reference clock is low level. When the reference clock rises, the value of the counter in MDIV is saved as F. In the following, the subscripts on the symbols and accord with the subscript on the symbol W. So, when two codes W1 and W2 and are assigned to tune the DCO successively, the corresponding frequencies of the DCO are f1 and f2. and F1 and F2 are the corresponding values sensed by the MDIV. .
W1 W2 K f F1 F2 . . . . . (1)
The stored value of F is M/2 when the ADPLL is frequency locking. M is the frequency divider ratio. Fig:2 Frequency Acquisition mode
The MDIV is reused as a frequency detector in this mode. The output of the MDIV F
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sends to the LC. The LC is a digital processing section. Depending on the value of F, it generates the next code and sends the code to the DCO and the DLPF. Based on the code, the DCO generates the DCO clock CLK [0] which is fed back to the MDIV. The value of Kf be reduced to the half of the previous value only when the relation between the value of F and M/2 changes from large to small. This operation will continue until the ADPLL achieves a frequency locking. Furthermore, the minimum difference between the current code and the previous code is set to one. When the frequency locking is achieved, the ADPLL enters phase acquisition mode.
Then the output of the DLPF tunes the DCO. Finally, the DCO clock is divided by the MDIV and is fed back to the PFD.
IV. PROCESS OF THE PROPOSED ADPLL The frequency locking is achieved when the output of the MDIV F is equal to M/2. the LC generates the middle code W1. The sensed value by the MDIV is F1 If F1 equals M/2, the ADPLL enters Phase acquisition mode, else check F1>M/2 it indicates that the frequency of the DCO is higher than the desired frequency and should be decreased. So the second code W2 will be decreased compared with W1. If F1<M/2, the second codeW2 will be increased. The corresponding output of the MDIV is F2. If F2 equals M/2, the ADPLL enters phase acquisition mode, The LC estimates the ADPLL parameter Kf with (1), and predicts the third code W3 according to (2). If the corresponding output of the MDIV F3 is not equal to W3, the mode will stay in same State. The fourth code W4will be computed by the LC based on the third sensed frequency informationF3.
2. Phase Acquisition Mode:In the frequency acquisition mode consists of three modules, that includes PFD, P2D, Digital Loop filter. PFD has been used to sense phase error between two input signals, sensed phase error is converted to digital format with help of P2D mode, In the Digital loop filter consists of low pass filter to filter the sensed phase error
V. STRUCTURE OF THE ADPLL:
1. Phase Frequency Detector:The structure of the PFD is shown in Fig.4. If the REF falls first, the signal UP is high level and the signal DOWN is low level. It indicates that the REF leads the DivCLK. If the signals UP and DOWN are both high levels, the two signals are both reset to low levels by a
Fig: 3 Phase Acquisition mode
The ADPLL is under phase acquisition mode, a PLL is activated to eliminate the remaining frequency error. The ADPLL achieves a phase locking when the code for the DCO oscillates between the neighboring codes. If the digitized phase error is larger than 63, the state will turn to State 0 at the rising edge of the signal Upd_state, or else the digital information is sent to the DLPF.
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feedback reset signal.
The resolution of the MDIV reused as the time-to-digital converter (TDC) is the period of the DCO clock. To reduce the quantization error of the MDIV reused as the TDC, the P2D module is added to count the phase error with the other four DCO clocks CLK [4:1]. The structure of the P2D is given in Fig.5. It includes four two-bit counters, four comparators, one multiplier, and two adders. If the value of the MDIV (for instance, P) is observed, Thus the other four counters can be replaced by four two-bit counters. Then the sum result P1 is the digitalized phase error. The quantization error is less than one fifth of the DCO clock period.
Figure 4. Structure of the PFD 3. First Order Digital Loop Filter:The sensed phase error by the PFD is the XOR-operation result of the signals UP and DOWN. An OR gate is inserted into the reset path. When the signal Reset_div is high level, the D flipflops in the PFD are reset. So during the frequency acquisition mode, the PFD does not sense the phase error.
2. Phase 2 Digitalized:-
The structure of the DLPF is shown in Fig.6 k1 and K2 are the DLPF parameters. When the signal Enable is high level, the code predicted by the LC is inserted into the integral path. Due to the structure of the PFD, the input of the DLPF keeps zero during the frequency acquisition mode. So, when the ADPLL enters the phase acquisition mode, the first code output by the DLPF is Wlocked . Then the following codes are decided by the sensed phase error.
Fig : 6. Structure of the DPLF
Fig : 5 Structure of the P2D
4. Structure of the DCO:-
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Fig: 7. Circuit of the delay cell DCO
Fig: 8. Structure of Enhanced MDIV
The DCO is the combination of a digital-to-analog converter (DAC) and a voltage controlled oscillator (VCO). Based on the input code, the DAC converts the code to the voltage then the voltage controls the frequency of the VCO.
5. Structure of the Enhanced MDIV:In the proposed ADPLL, the DIV is added by three modules which are Save F module, Reset_syn module and T2D module. The DIV with the three modules are renamed as MDIV. The Save F module saves the value of the counter in the DIV when the REF rises. Because the DCO clock is not synchronous with the REF, the REF is retimed by the falling edge of the CLK. Then the value of counter N[n-1:0] will be stored in F[n-1:0] when the signal REF_d rises.
The function of the Reset_syn module is generating the reset signal Reset_div to control the operation of the DIV. When the signal Reset_di v is low level, the DIV counts by the rising edge of . When the signal Reset_div is high level, the DIV is reset for the next counting operation, and leaves the time for the LC to tune the DCO. The signal Reset_div turns to be high level under two conditions. First, the system reset signal in_Reset is high level. Second, the ADPLL is under frequency acquisition mode, the REF is high level, and the value of F[n-1:0] is saved by the Save F module.
VI. SIMULATION RESULTS: PFD module:-
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P2Dmodule:-
locking time is three cycles. Based upon simulation the maximum frequency locking time and power consumption is reduced.
REFERENCES
[1.] Xin Chen, Jun Yang, Member, IEEE, and Long-Xing Shi, A Fast Locking All-Digital PhaseLocked Loop via Feed-Forward Compensation Technique, vol. 19, no. 5, May 2011
DLPF module:-
[2]. P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.Y. Lee, A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications, IEEE J. Solid-State Circuits, vol. 41, no.6, pp. 12751284, Jun. 2006.
[3]. T.Watanabe and S.Yamauchi, An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 198204, Feb. 2003.
[4]. I. Hwang, S. Lee, and S. Kim, A digitally controlled phase-locked loop with a digital phasefrequency detector for fast acquisition, IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1574 1581, Oct. 2001 VII. CONCLUSION [5]. C.-C. Chung and C.-Y. Lee, An all-digital phase-locked loop for high speed clock generation, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp.347351, Feb. 2003
A feed-forward compensation algorithm is proposed in this ADPLL. Furthermore, the frequency divider is fully reused. The predicted error due to the estimation errors and the stabilities of the proposed ADPLL during the frequency acquisition mode and phase acquisition mode are analyzed in detail. The ADPLL can complete frequency locking with in 2 reference cycles and phase locking with in 11cycles. The corresponding power consumption is 12.01 mW. However, based on the simulation results, the maximum frequency
[6].Panda, Bibhu Prasad Design and analysis of

an Efficient Phase Locked Loop for Fast Phase and Frequency Acquisition (2011).
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Volume 1 Issue 1 July

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International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

International Journal Of Communication And Computer Technologies

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V DYNAMIC SOURCE ROUTING (DSR) PROTOCOL

IV AD-HOC ON-DEMAND DISTANCE VECTOR ROUTING (AODV) PROTOCOL

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VI DESTINATION SEQUENCED DISTANCE VECTOR ROUTING (DSDV) PROTOCOL

Fig.1. Average End-to-End Delay Vs Number of b) Packet Drop

VII SIMULATION RESULTS & CONCLUSION a) Comparison of Delay

Fig.2. Total Packet Drop Vs Number of Nodes

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c) Packet Delivery Ratio

Fig.4. Received Packet Rate Vs Number of Nodes VIII CONCLUSION

number of nodes are between 15 and 30.

Fig.3. Packet Delivery Ratio Vs Number of Nodes d) Received Packets

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International Journal Of Communication And Computer Technologies

Design of 16-Bit CRC Generator

A.S.Prabhu, 2 N.Vignesh and 3 V.Elakya

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A'B+AC MUX A' NOT

Fig. 1: Basic GDI cell

Fig. 2: Design of Static CMOS D Flip Flop

Table I: Logic functions implemented with GDI cell

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Fig. 3: Output waveform static CMOS D Flip Flop

Fig. 5: GDI D Flip Flop without Buffer

Fig. 6: Output waveform GDI D Flip Flop without Buffer

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Fig. 7: GDI D Flip Flop with Buffer

Fig. 8: Output waveform GDI D Flip Flop with Buffer

V. IMPLEMENTATION OF CRC GENERATOR

Table II: Generator Polynomials Of Some CRC Codes Page 9

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Fig. 10: 16 Bit CMOS CRC Generator

Fig. 11: 16 Bit CMOS CRC Generator output wave form

Fig. 12: 16 Bit GDI CRC Generator

16 Bit Cmos CRC Generator T-Spice Coding: Page 10

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No.of Transistors Power Consumption Total access time

600 500 400 300 200 100 0 No.of transistors

GDI CRC Generator CMOS CRC Generator

Fig. 14: Transistor count Comparison

GDI CRC Generator CMOS CRC Generator

Fig. 15: Power Comparison

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40 30 20 10 0 Total acess time

GDI CRC Generator CMOS CRC Generator

Fig. 16: Total access time Comparison

[5] [6] [7]

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SIMULATION OF AN AUTOMATIC IMAGE REGISTRATION THROUGH HISTOGRAM BASED IMAGE SEGMENTATION

Automatic image registration (AIR) is still a present challenge regarding

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International Journal Of Communication And Computer Technologies

International Journal Of Communication And Computer Technologies

International Journal Of Communication And Computer Technologies

International Journal Of Communication And Computer Technologies

(a) Input Image (b) Histogram of the image

International Journal Of Communication And Computer Technologies

International Journal Of Communication And Computer Technologies

International Journal Of Communication And Computer Technologies