International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

VLSI Architecture Design for Analysis of Fast Locking ADPLL via Feed Forward Compensation Algorithm
S.ARUL MURUGAN #1 & T.M.SATHISH KUMAR#2

DEPARTMENT OF ECE Email:- snarul@live.com, 9943201055#1 Email:- ed.samuvel27@gmail.com, 9843499123 #2 K.S.R.COLLEGE OF ENGINEERING
Abstract-- The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, and frequency synthesizers. Phase locked-loop is commonly used to generate well-timed on-chip clocks in high performance digital systems. Modern wireless communication systems employ Phase Locked Loop mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit operation, there is a need of a PLL circuit with faster locking ability. A fast locking all-digital phaselocked loop (ADPLL) via feed-forward compensation technique is proposed in this Paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. The proposed ADPLL can easily be ported to different processes in a short time. It can reduce the design time, Locking time, Power Consumption and wide tunable frequency range of the ADPLL, making it very suitable for system-onchip applications. Keywords:- All-digital phase-locked loop (ADPLL), digitally controlled oscillator (DCO), feed-forward compensation technique, frequency Divider (DIV).

widely used in modern electronic devices, with output frequencies from a fraction of an Hz to many GHz. Basically, analog approaches are adopted to design PLLs. But it is difficult to integrate an analog PLL into a noisy SoC environment so that we are moving to ADPLL. Comparing with PLL, ADPLL have higher immunity to switching noise and then easy to implement in electronic design automation tools (EDA). It helps to reduce designing time gradually. In the ADPLL voltage control oscillator (VCO) replaced by numerical control oscillator (NCO) can be used. The frequency of the numerical controlled oscillator (NCO) is tuned by digital codes. So ADPLLs are much easier to achieve fast frequency acquisitions. There are several frequency search algorithms used in ADPLLs. One of the typical methods is adjusting the PLLs loop Band width dynamically the locking time is directly proportional to the initial frequency difference between the reference clock and the divided clock, and inversely proportional to the loop bandwidth of the PLL. In when the phase error between the reference clock and the divided clock is large, the PLL increases the loop bandwidth and achieves fast locking. Conversely, when the phase error is small, the PLL decreases the loop bandwidth and minimizes the output jitter. But this method will increase the complexity of the PLL circuits. The PLL must be stable over a wide range of the PLLs loop bandwidth, and must tolerate the errors in the prediction of the loops parameters such as the oscillator gain.

I. INTRODUCTION:Phase-locked loops are widely employed in radio, telecommunications, computers and other electronic applications. They can be used to recover a signal from a noisy communication channel, generate stable frequencies at a multiple of an input frequency (frequency synthesis), or distribute clock timing pulses in digital logic designs such as microprocessors. Since a single integrated circuit can provide a complete phase-locked loop building block, the technique is

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International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

II. STRUCTURE OF THE PROPOSED ADPLL:

In (1), replacing F1 with M/2, and using Wlocked instead of W1, then Wlocked can be calculated by (2),

Wlocked W2 K f M F2 2
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (2) From (2), it is seen that the ADPLL with the proposed algorithm can achieve a fast frequency locking when the values W2 and Kf *(M/2-F2) are known. The code W2 is generated by the ADPLL itself. The value of M is set to the ADPLL before the ADPLL works, and the value of F2 is sensed by the MDIV, so these values can be obtained easily. The value which is the most difficult to obtain is Kf,, it is seen that the parameter Kf is PVT dependent. So it is better to recalculate the value of Kf for every initialization of the ADPLL. III. OPERATION OF THE PROPOSED ADPLL: The operation of the proposed ADPLL is based on the two operating modes, Frequency Acquisition Mode and Phase Acquisition Mode. 1. Frequency Acquisition Mode:In the frequency acquisition mode consists of three modules. In this mode, the feed-forward compensation structure which includes the MDIV, LC, and DCO is activated.

Fig:1 Overall Block Diagram

Our overall system consists of six modules, which are Phase/Frequency detector (PFD), Enhanced Modified divider, loop control (MDIV), Digital control oscillator (DCO), phase to digitalized mode (P2D) and Digital loop filter. The code W is assigned to tune the DCO, the DCO frequency is f. F is the corresponding value sensed by the Modified Frequency Divider. It counts by the rising edge of the DCO clock when the reference clock is low level. When the reference clock rises, the value of the counter in MDIV is saved as F. In the following, the subscripts on the symbols and accord with the subscript on the symbol W. So, when two codes W1 and W2 and are assigned to tune the DCO successively, the corresponding frequencies of the DCO are f1 and f2. and F1 and F2 are the corresponding values sensed by the MDIV. .

W1 W2 K f F1 F2 . . . . . (1)
The stored value of F is M/2 when the ADPLL is frequency locking. M is the frequency divider ratio. Fig:2 Frequency Acquisition mode

The MDIV is reused as a frequency detector in this mode. The output of the MDIV F

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International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

sends to the LC. The LC is a digital processing section. Depending on the value of F, it generates the next code and sends the code to the DCO and the DLPF. Based on the code, the DCO generates the DCO clock CLK [0] which is fed back to the MDIV. The value of Kf be reduced to the half of the previous value only when the relation between the value of F and M/2 changes from large to small. This operation will continue until the ADPLL achieves a frequency locking. Furthermore, the minimum difference between the current code and the previous code is set to one. When the frequency locking is achieved, the ADPLL enters phase acquisition mode.

Then the output of the DLPF tunes the DCO. Finally, the DCO clock is divided by the MDIV and is fed back to the PFD.

IV. PROCESS OF THE PROPOSED ADPLL The frequency locking is achieved when the output of the MDIV F is equal to M/2. the LC generates the middle code W1. The sensed value by the MDIV is F1 If F1 equals M/2, the ADPLL enters Phase acquisition mode, else check F1>M/2 it indicates that the frequency of the DCO is higher than the desired frequency and should be decreased. So the second code W2 will be decreased compared with W1. If F1<M/2, the second codeW2 will be increased. The corresponding output of the MDIV is F2. If F2 equals M/2, the ADPLL enters phase acquisition mode, The LC estimates the ADPLL parameter Kf with (1), and predicts the third code W3 according to (2). If the corresponding output of the MDIV F3 is not equal to W3, the mode will stay in same State. The fourth code W4will be computed by the LC based on the third sensed frequency informationF3.

2. Phase Acquisition Mode:In the frequency acquisition mode consists of three modules, that includes PFD, P2D, Digital Loop filter. PFD has been used to sense phase error between two input signals, sensed phase error is converted to digital format with help of P2D mode, In the Digital loop filter consists of low pass filter to filter the sensed phase error

V. STRUCTURE OF THE ADPLL:

1. Phase Frequency Detector:The structure of the PFD is shown in Fig.4. If the REF falls first, the signal UP is high level and the signal DOWN is low level. It indicates that the REF leads the DivCLK. If the signals UP and DOWN are both high levels, the two signals are both reset to low levels by a

Fig: 3 Phase Acquisition mode

The ADPLL is under phase acquisition mode, a PLL is activated to eliminate the remaining frequency error. The ADPLL achieves a phase locking when the code for the DCO oscillates between the neighboring codes. If the digitized phase error is larger than 63, the state will turn to State 0 at the rising edge of the signal Upd_state, or else the digital information is sent to the DLPF.

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International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

feedback reset signal.

The resolution of the MDIV reused as the time-to-digital converter (TDC) is the period of the DCO clock. To reduce the quantization error of the MDIV reused as the TDC, the P2D module is added to count the phase error with the other four DCO clocks CLK [4:1]. The structure of the P2D is given in Fig.5. It includes four two-bit counters, four comparators, one multiplier, and two adders. If the value of the MDIV (for instance, P) is observed, Thus the other four counters can be replaced by four two-bit counters. Then the sum result P1 is the digitalized phase error. The quantization error is less than one fifth of the DCO clock period.

Figure 4. Structure of the PFD 3. First Order Digital Loop Filter:The sensed phase error by the PFD is the XOR-operation result of the signals UP and DOWN. An OR gate is inserted into the reset path. When the signal Reset_div is high level, the D flipflops in the PFD are reset. So during the frequency acquisition mode, the PFD does not sense the phase error.

2. Phase 2 Digitalized:-

The structure of the DLPF is shown in Fig.6 k1 and K2 are the DLPF parameters. When the signal Enable is high level, the code predicted by the LC is inserted into the integral path. Due to the structure of the PFD, the input of the DLPF keeps zero during the frequency acquisition mode. So, when the ADPLL enters the phase acquisition mode, the first code output by the DLPF is Wlocked . Then the following codes are decided by the sensed phase error.

Fig : 6. Structure of the DPLF

Fig : 5 Structure of the P2D

4. Structure of the DCO:-

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International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

Fig: 7. Circuit of the delay cell DCO

Fig: 8. Structure of Enhanced MDIV

The DCO is the combination of a digital-to-analog converter (DAC) and a voltage controlled oscillator (VCO). Based on the input code, the DAC converts the code to the voltage then the voltage controls the frequency of the VCO.

5. Structure of the Enhanced MDIV:In the proposed ADPLL, the DIV is added by three modules which are Save F module, Reset_syn module and T2D module. The DIV with the three modules are renamed as MDIV. The Save F module saves the value of the counter in the DIV when the REF rises. Because the DCO clock is not synchronous with the REF, the REF is retimed by the falling edge of the CLK. Then the value of counter N[n-1:0] will be stored in F[n-1:0] when the signal REF_d rises.

The function of the Reset_syn module is generating the reset signal Reset_div to control the operation of the DIV. When the signal Reset_di v is low level, the DIV counts by the rising edge of . When the signal Reset_div is high level, the DIV is reset for the next counting operation, and leaves the time for the LC to tune the DCO. The signal Reset_div turns to be high level under two conditions. First, the system reset signal in_Reset is high level. Second, the ADPLL is under frequency acquisition mode, the REF is high level, and the value of F[n-1:0] is saved by the Save F module.

VI. SIMULATION RESULTS: PFD module:-

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International Journal Of Communication And Computer Technologies

Volume 01 No.1, Issue: 01 JULY 2012

P2Dmodule:-

locking time is three cycles. Based upon simulation the maximum frequency locking time and power consumption is reduced.

REFERENCES

[1.] Xin Chen, Jun Yang, Member, IEEE, and Long-Xing Shi, A Fast Locking All-Digital PhaseLocked Loop via Feed-Forward Compensation Technique, vol. 19, no. 5, May 2011

DLPF module:-

[2]. P.-L. Chen, C.-C. Chung, J.-N. Yang, and C.Y. Lee, A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications, IEEE J. Solid-State Circuits, vol. 41, no.6, pp. 12751284, Jun. 2006.

[3]. T.Watanabe and S.Yamauchi, An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp. 198204, Feb. 2003.

[4]. I. Hwang, S. Lee, and S. Kim, A digitally controlled phase-locked loop with a digital phasefrequency detector for fast acquisition, IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1574 1581, Oct. 2001 VII. CONCLUSION [5]. C.-C. Chung and C.-Y. Lee, An all-digital phase-locked loop for high speed clock generation, IEEE J. Solid-State Circuits, vol. 38, no. 2, pp.347351, Feb. 2003

A feed-forward compensation algorithm is proposed in this ADPLL. Furthermore, the frequency divider is fully reused. The predicted error due to the estimation errors and the stabilities of the proposed ADPLL during the frequency acquisition mode and phase acquisition mode are analyzed in detail. The ADPLL can complete frequency locking with in 2 reference cycles and phase locking with in 11cycles. The corresponding power consumption is 12.01 mW. However, based on the simulation results, the maximum frequency

[6].Panda, Bibhu Prasad Design and analysis of

an Efficient Phase Locked Loop for Fast Phase and Frequency Acquisition (2011).

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