International Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan.

7-8, 2012 Dubai

Hardware Implementation of Watchdog Timer for Application in ATM Machine Using Verilog and FPGA
Iqbalur Rahman Rokon, Toufiq Rahman, Md. Murtoza Ali Quader, and Mukit Alam

Abstract - In this paper, the design of a watchdog timer for

application in an ATM machine is described. An ATM machine may need a watchdog timer in two situations: when the user gives no input after inserting the ATM card, and when the ATM machine goes hang. This paper deals with both situations. The authors created the system input, inout, and output signals by themselves based on hardware perception. First, a block diagram is shown with some subblocks. Then a flow of interactions of sub-blocks is presented. Next, hand-drawn waveforms of all the associated signals are given. Then comes the heart of the design the state machine. After that, the system signals are briefly described. Next, simulation results are shown and in the end, conclusion is drawn discussing the authors satisfaction and encouragement to work with similar things in the future.

A watchdog timer (or computer operating properly (COP) timer) is a computer hardware or software timer that triggers a system reset or other corrective action if the main program, due to some fault condition, such as a hang, neglects to regularly service the watchdog. The intention is to bring the system back from the unresponsive state into normal operation [2]. Some embedded designs, such as space probes, are simply not accessible to human operators. If their software ever hangs, such systems are permanently disabled. In other cases, the speed with which a human operator might reset the system would be too slow to meet the uptime requirements of the product. A watchdog timer is a piece of hardware that can be used to automatically detect software anomalies and reset the processor if any occur [3].

Keywords ATM Machine, FPGA, Verilog, Watchdog Timer.

I.

INTRODUCTION
Fig. 1 Typical watchdog setup

automated teller machine (ATM), also known as a Cashpoint (which is a trademark of Lloyds TSB), cash machine is a computerised telecommunications device that provides the clients of a financial institution with access to financial transactions in a public space without the need for a cashier, human clerk or bank teller. ATMs are known by various other names including ATM machine, automated banking machine, and various regional variants derived from trademarks on ATM systems held by particular banks. Using an ATM, customers can access their bank accounts in order to make cash withdrawals, credit card cash advances, and check their account balances as well as purchase prepaid cellphone credit [1].
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Mr. Iqbalur Rahman Rokon is with the department of Electrical Engineering and Computer Science, North South University, Dhaka 1229, Bangladesh (e-mail: irahman@northsouth.edu). Toufiq Rahman is a graduate student from the department of Electrical Engineering and Computer Science, North South University, Dhaka 1229, Bangladesh (e-mail: ullash_nsu@yahoo.com). Md. Murtoza Ali Quader is a student of the department of Electrical Engineering and Computer Science, North South University, Dhaka 1229, Bangladesh (e-mail: shadman.ali@gmail.com). Mukit Alam is a student of the department of Electrical Engineering and Computer Science, North South University, Dhaka 1229, Bangladesh (e-mail: mukit110@gmail.com).

A major issue related with ATMs is its timing control. That means what happens if a person enters his card and doesnt enter any value. It will be a test of patience for the customers standing in the long queue. Here the watchdog timer comes to the rescue. The system waits for a predefined time-period and if it exceeds that time period without any input to it, then it indicates that using some indicator. The indicator remains high as long as there is no input. And once some input comes, the timer is reset and the indicator is turned off. Normal operation can resume after that. Another issue is that what will happen if the ATM machine goes hang and does not work properly. In that case, after waiting for a particular timeperiod in the alarm state, the ATM machine is reset to go to the initial state so that it can work properly after that.

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International Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan. 7-8, 2012 Dubai

II. BLOCK DIAGRAM

III.

FLOW OF INTERACTIONS OF SUB-BLOCKS

Fig. 2 Block diagram

Fig. 3 Interaction-flow of sub-blocks

A. State Machine This is a vital block of the design. It determines when different output signals will come in effect. Two most significant signals of this block are nextstate and currentstate both of which are 3 bit bus signals. To generate nextstate, some other signals like CARD, PWRD, registered version of OPTION (OPTIONreg), time-out signals (to1 & to2), and currentstate are needed. nextstate and currentstate are used as internal input signals for other blocks. B. Watchdog Timer This block keeps track of time. It provides the system with two different time-out parameters: one for switching to alarm states if the user gives no input and the other for system reset when probably there is something wrong causing the ATM machine not working. C. Internal Signal Generator This is an important block that deals with generating the internal signals like OPTIONreg, to1, to2, int1, int2, Rreg etc. These signals contribute to generate the final outputs and also to switch states. D. Reset & Alarm Control This block is in the charge of driving the value of RESETn low if the ATM machine goes hang and does not work properly. It will also show alarm to the user if the currentstate is ALARM1 or ALARM2. E. Control Output Generator This section is responsible for generating all three control output signals OK, AM, LK. This section is affected directly by the state machine. Asynchronous reset is used to generate all of these signals.

IV.

HAND-DRAWN TIMING DIAGRAMS

A. For Normal Operation

Fig. 4 Diagram for normal operation

Fig. 4 Continued

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International Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan. 7-8, 2012 Dubai

B. For Alarm Operation

Fig. 6 Continued Fig. 5 Diagram for alarm operation

V. STATE MACHINE DETAILS

Fig. 5 Continued C. For Reset Operation Fig. 7 State machine

A. IDLE State During IDLE state, all the output signals are kept low. This state is entered from: - RESETn = 0 when the system is initialized - WAIT, ALARM1, ENABLE, ALARM2 or IDLE, when there is no ATM card in the ATM machine. The next state will always be WAIT when the ATM card is inserted into the machine. This state is indicated by the binary value 000 in the code. B. WAIT State During this state, the machine waits for password. The WAIT state is entered from only IDLE state when the card is inserted. The next state will be: - ENABLE if the user gives the correct password.
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Fig. 6 Diagram for reset operation

International Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan. 7-8, 2012 Dubai

- LOCK if the user gives an incorrect password. - ALARM1 if the user does not give any password for a certain period of time. This state is indicated by the binary value 001 in the code. C. LOCK State During this state, the ATM machine locks the inserted ATM card and the user will not be able to do anything. This state is entered from: - WAIT when the user gives an incorrect password. - ALARM1 when the user gives an incorrect password. There will be no next state from the LOCK state. The only way to go back to normal operation is resetting the system after waiting for a certain period of time. This state is indicated by the binary value 011 in the code. D. ALARM1 State During this state, the machine shows alarm to the user to give the password. This state is entered only from WAIT state if the user gives no password for a certain period of time The next state will be: - ENABLE if the user gives the correct password within a predefined time-period. - LOCK if the user gives an incorrect password within a predefined time-period. This state is indicated by the binary value 010 in the code. E. ENABLE State This state indicates the proper operation of an ATM card in an ATM machine. The ENABLE state is entered from: - WAIT if the user gives the correct password. - ALARM1 if the user gives the correct password within a predefined period of time. - ALARM2 if the user selects one of the options shown in the screen within a predefined period of time. - ENABLE if the user selects an option immediately after giving the correct password. The next state will be: - ALARM2 if the user does not select any option for a predefined time-period after giving the correct password. - IDLE if the user takes the ATM card out of the machine. This state is indicated by the binary value 100 in the code.
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F. ALARM2 State During this state, the machine shows alarm to the user to select an option shown in the screen of the ATM machine after entering the ENABLE state. This state is always entered from ENABLE. The next state will be: - ENABLE if the user selects an option within a specific period of time. - IDLE if the user takes the card out of the ATM machine. This state is indicated by the binary value 101 in the code. VI. BRIEF DESCRIPTION OF THE SIGNALS A. CLK This is an input signal. It is the system clock. B. RESETn This is an inout signal. It is the system reset signal which is active-low. C. CARD This is an input signal. It is driven high when an ATM card is inserted in the ATM machine. D. PWRD This is an input signal. It is a 4-bit bus signal. It indicates the password given by the user after inserting the ATM card. E. OPTION This is an input signal. It is a 3-bit bus signal. It indicates the options the user must select after giving the correct password. F. OK This is an output signal. It is driven high when the ATM machine is in properly operating mode i.e. the system is in ENABLE state. G. AM This is an output signal. It is driven high when the card is locked in the ATM machine i.e. the system is in LOCK state. H. LK This is an output signal. It is driven high when the ATM machine shows alarm to the user i.e. the system is in ALARM1 or ALARM2 state. It should be noted that verilog HDL is used to generate proper output/inout signals from the input/inout signals [4]. VII. SIMULATION RESULTS

International Conference on Electronics, Biomedical Engineering and its Applications (ICEBEA'2012) Jan. 7-8, 2012 Dubai

A. For Alarm Operation

also convey their gratefulness to Dr. Abdul Awal, the chairman of the EECS Department of North South University for helping them with his wise advice. They also thank all those people who helped them in any way regarding this paper and enriched them with different ideas and lot of support. REFERENCES
[1] Automated teller machine http://en.wikipedia.org/wiki/Automated_teller_machine [2] Watchdog timer http://en.wikipedia.org/wiki/Watchdog_timer [3] Watchdog Timer http://intranet.daiict.ac.in/~ranjan/esp2007/watchdog.pdf [4] Palnitkar, S. (2006). A Guide to Digital Design and Synthesis (2nd ed). India: Dorling Kindersley Pvt. Ltd.

Fig. 8 Simulation results B. For Reset Operation

Fig. 8 Continued

VIII. CONCLUSION This paper presents an efficient design of watchdog timer for ATM machine. The authors are really satisfied with this work. They have learnt a lot of things regarding the applications of watchdog timer, and have gained more indepth knowledge about the verilog HDL coding while doing this paper-work. Watchdog timer is indeed a very useful component and has got its application ranging over various fields. The authors are very keen to implement watchdog timer in many other fields in the future using verilog and FPGA.

ACKNOWLEDGMENT At first the authors would like to thank the Almighty for giving them the strength and courage to begin and complete this paper. Then they would want to mention their parents who supported them with mental and financial support. They
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