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´ LABORATOIRE Louvain-la-Neuve UNIVERSIT E CATHOLIQUE DE LOUVAIN ´ D’HYPERFR EQUENCES Modelling and Characterisation
´ LABORATOIRE Louvain-la-Neuve
´
LABORATOIRE
Louvain-la-Neuve

UNIVERSIT E CATHOLIQUE DE LOUVAIN

´

D’HYPERFR EQUENCES

Modelling and Characterisation of the SOI MOSFET for MMIC Applications

Jury

Renaud GILLON

Prof. P. Sobieski (Pr´esident) Prof. D. Vanhoenacker (Promoteur) Prof. A. Vander Vorst Prof. J.-P. Colinge Prof. P. Jespers Dr Ch. Raynaud

Th`ese pr´esent´ee en vue de l’obtention du grade de docteur en Sciences Appliqu´ees

Juin 1998

Ce doctorat n’aurait pu exister sans l’´etroite collaboration entre les Lab- oratoires d’Hyperfr´equences et de Micro´electronique, mise sur pied par les professeurs Danielle Vanhoenacker et Jean-Pierre Colinge. Je leur suis pro- fond´ement reconnaissant d’avoir cr´e´e cet environnement de recherche riche et stimulant. Merci, ´egalement, au professeur Andr´e Vander Vorst, responsable de l’unit´e, pour la qualit´e du cadre de travail au Laboratoire d’Hyperfr´equences. La trame de cette th`ese est tiss´ee de nombreux avis et conseils recueil- lis aupr`es des professeurs Danielle Vanhoenacker, Jean-Pierre Colinge, Andr´e Vander Vorst, Paul Jespers et Fernand Van de Wiele. Je tiens a` leur t´emoigner ici ma gratitude et `a rendre hommage `a leur savoir-faire. Plusieurs r´esultats pr´esent´es dans cet ouvrage sont issus de discussions fructueuses avec des col- l`egues. En particulier, avec Jean-Pierre Raskin pour la mod´elisation et les ex- tractions, avec Jian Chen pour les aspects technologiques, avec Isabelle Huynen pour les lignes et les ´etalonnages, avec Jean-Paul Eggermont pour les amplifi- cateurs op´erationnels, et avec Denis Flandre, Luis Ferreira et Benjamin I˜n`ıguez pour le mod`ele “charge-sheet”. Je les remercie tous chaleureuseme nt pour leur disponibilit´e et leur aide. Aux membres du Jury, qui ont consacr´e leur temps `a la lecture des manu-

scrits et ont contribu´e `a en am´eliorer la qualit´e par leur remarques, je souhaite

`

exprimer ma reconnaissance. A Danielle Vanhoenacker tout sp´ecialement, qui en tant que promoteur, m’a judicieusement guid´e et abondamment encourag´e. Les travaux de recherche associ´es `a cette th`ese ont n´ecessit´es de nombreuses r´ealisations techniques. Merci a` Andr´e Crahay et `a toute l’´equipe de fabrica- tion de circuits int´egr´es; `a Pierrot Loumaye pour l’encapsulation des puces ; a` Robert Platterborze pour les fabrications de circuits imprim´es et pour toutes les am´eliorations apport´ees aux stations de caract´erisation; `a Hubert Sablain pour son aide minutieuse lors des mesures sur tranche; a` Fran¸cois-Michel Plennevaux et Christian Renaux qui ont repris le fardeau de la caract´erisation. Merci, enfin, `a tous les ing´enieurs, techniciens et informaticiens qui ont apport´e le soutien

indispensable a` mes travaux. Ce travail a b´en´efici´e du soutien financier de la R´egion Wallonne, de la Communaut´e Fran¸caise par son programme “d’Actions Concert´ees” et de la Communaut´e Europ´eenne grˆace au programme “ESPRIT”. Je remercie affectueusement mon ´epouse pour sa patience et son courage lors des difficiles p´eriodes d’intense r´edaction.

Je d´edie cet ouvrage a` ceux qui m’ont transmis leur goˆut de la technique.

Renaud

Preface

Silicon-on-insulator technology has been under development for more than three decades. Interest in thin-film SOI for high performance applications dates back from the late 70’s, when several commercial companies undertook research efforts in this area. SOI remained an exotic technology, confined in niche applications for some time, until recently, when the quest for low-voltage performance driven by the boom in portable electronics and mobile communi- cations brought it under the spotlight. Thin-film SOI MOSFET’s offer indeed interesting low-voltage performances, higher speed and increased integration density, all with simpler processing than bulk silicon MOSFET’s of compa- rable size, [1]. Many recent realisations of logic circuits, memories, and RF circuits, [2], have confirmed both the advantages and the viability of thin-film SOI circuits, even in the case of very large systems.

To support the development of thin-film SOI circuits, adequate device mod- els must be made available concurrently with the maturation of fabrication processes. Several models have already been proposed for thin-film SOI MOS- FET’s, [3,4,5,6,7]. Very few of them have however been tailored to the design of analogue microwave circuits. The majority of these models is indeed targeted at the prediction of quasi-static characteristics, failing to account properly for channel propagation delays which become significant at microwave frequencies. Some of these models do not meet the strict continuity requirements necessary for the non-linear simulation of analogue circuits. None of the existing mod- els deals properly with substrate coupling effects and particularly with their influence on the back gate at high frequencies.

This thesis concerns the development and the validation of a comprehensive model of the thin-film SOI n-MOSFET intended for the simulation of analogue circuits in the microwave domain. To enable model validation at microwave frequencies, new characterisation techniques and parameter extraction proce- dures are proposed, which will be shown to be accurate and reliable. Finally, the model is used to evaluate the feasibility of microwave SOI MOSFET mixers.

v

Preface

The text is structured as follows :

Chapter I : Introduction The global context of this work is presented. The evolution of technology under the impulse of the recent boom in mobile telecommunications is briefly analysed. Silicon-on-insulator and bulk silicon technologies are compared in the perspective of this evolution, and the specific advantages of SOI CMOS technology for low-voltage applications are illus- trated. The main-stream fabrication processes of SOI material are described. Finally, several aspects of characterisation and modelling are discussed.

Chapter II : On-wafer characterisation at microwave frequencies The scattering parameters measurement techniques developed in this work are described. The chapter starts with an introduction to the rigorous framework which forms the foundation of scattering parameters measurements. The cal- ibration procedures of interest to on-wafer characterisation are reviewed, and new reference impedance determination methods are proposed, which enable to use powerful scattering parameters calibrations directly for the complete de- embedding of devices integrated on any kind of wafer. The new de-embedding strategy is shown to be more reliable than the conventional immittance correc- tion approach.

Chapter III : Modelling fully depleted SOI MOSFET’s Several mod- els are developed with the specific needs of analogue microwave circuit design in mind. Such issues as short-channel effects, channel propagation delays, dis- persive behaviour of the interface states and continuity of all characteristics are addressed. For the intrinsic device, a large-signal current and charge model, a small-signal equivalent circuit model, and a distributed channel model at V DS = 0 are proposed. The picture is completed with a small-signal equivalent circuit accounting for device parasitics : series resistances, gate-diffusion ca- pacitances, substrate capacitances, etc. Finally, model limitations concerning device dimensions, biasing conditions and maximum frequency are discussed.

Chapter IV : Extraction of the SOI MOSFET model parameters A progressive extraction strategy is demonstrated which leads to the identifica- tion of the majority of model parameters. All extractions can be formulated as optimisation problems, which are solved by selective optimisation on the most influencing parameters in order to minimise uncertainty. Original direct extraction schemes are proposed as advantageous alternatives, being inherently robust and efficient. The chapter includes numerous comparisons of predicted and measured characteristics, providing confidence in the validity of the newly introduced models.

Chapter V : Microwave MOSFET down-conversion mixers

alytical current and charge model is used to evaluate the performance of mi-

crowave mixer designs based on SOI MOSFET’s. The feasibility of resistive SOI MOSFET mixers at 2 .0 GHz is established by simulations and confirmed

The an-

vi

REFERENCES

by measurements performed on basic mixing cells. The implementation of a single-chip down-conversion stage with image rejection is presented.

References

[1] J.-P. Colinge, Silicon-on-Insulator Technology : Materials to VLSI. Boston – Dordrecht – London: Kluwer Academic Publ., 2nd ed., 1997.

[2] S. R. Wilson et al., “TFSOI circuit applications,” in Proc. of the 8th Intl Symp. on SOI technology and devices (S. Cristoloveanu, ed.), vol. 97-23, pp. 359–372, The Electrochemical Society, 1997.

[3] Dept of Electrical Engineering and Computer Sciences, University of Cal- ifornia, Berkeley, BSIM3SOI v1.0 Manual, 1997.

[4] E. Arnold, “Double-charge-sheet model for thin silicon-on-insulator films,” IEEE Trans. on Electron Devices, vol. 43, pp. 2153–2163, Dec. 1996.

[5] B. I˜n`ıguez, L. F. Ferreira, B. Gentinne, and D. Flandre, “A physically- based C -continuous fully-depleted SOI MOSFET model for analog ap- plications,” IEEE Trans. on Electron Devices, vol. 43, pp. 568–575, Apr.

1996.

[6] C. Mallikarjun and K. N. Bhat, “Numerical and charge sheet models for thin-film SOI MOSFET’s,” IEEE Trans. on Electron Devices, vol. 37, pp. 2039–2051, Sept. 1990.

[7] S. Veeraraghavan and J. G. Fossum, “A physical short-channel model for the thin-film SOI MOSFET applicable to device and circuit CAD,” IEEE Trans. on Electron Devices, vol. 35, pp. 1866–1875, Nov. 1988.

vii

Contents

Preface

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References

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vii

Main scientific publications

 

xiii

List of abbreviations

xvii

I Introduction

I-1

I.1

RF and microwave monolithic IC’s

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I-1

I.1.1

I.1.2

New driving forces

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I-2

Technology directions

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I-4

I.2

Competing technologies for emerging RF applications

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I-8

I.2.1

I.2.2

I.2.3

. Thin-film SOI MOSFET’s Bulk bipolar transistors

Bulk MOSFET’s

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I-9

I-13

I-14

I.2.4

. Thin-film lateral bipolar SOI transistors

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I-14

I.2.5

Low-voltage systems-on-a-chip, the future of SOI

 

I-16

I.3

Silicon-on-Insulator substrate technology

I-16

I.3.1

Silicon-on-sapphire

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I-16

I.3.2

I.3.3

I.3.4

Separation by Implantation of Oxygen

. The blooming of a SOI era? .

Wafer-bonding

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I-17

I-18

I-19

I.4

. Characterisation and modelling of MMIC’s

 

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I-20

I.5

Conclusion

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I-22

References

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I-23

II On-wafer characterisation at microwave frequencies

 

II-1

II.1

Introduction .

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II-1

II.2

Uniform waveguides

II.2.1

II.2.2

. Modal electro-magnetic fields

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II-2

II-2

Waveguide voltage and current

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II-3

ix

CONTENTS

 

II.2.3

II.2.4

. Characteristic impedance

Power

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II-4

II-4

II.2.5

II.2.6

Normalisation of waveguide voltage and current

 

II-5

Transmission line equivalent circuit

II-6

II.3

General waveguide circuit theory

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II-7

II.3.1

Travelling wave intensities

II-7

II.3.2

Pseudo-waves

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II-8

II.3.3

Power-waves

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II-9

II.3.4

Load impedance

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II-10

II.3.5

Scattering matrix for pseudo-waves

 

II-11

II.3.6

II.3.7

II.3.8

. Immittance matrices

Transfer matrix

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II-12

II-13

Change of reference impedance

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II-14

II.4

Measurement set-up

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II-15

II.5

Calibration methods

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II-17

II.5.1

The transfer-matrix formalism

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II-18

II.5.2

II.5.3

. TAN self-calibration procedures

SOLT procedure

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II-20

II-21

II.6

Reference impedance determination

II-27

II.6.1

II.6.2

Propagation constant measurement

Load measurement

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II-27

II-28

II.6.3

. Calibration comparison

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II-31

II.7

De-embedding strategies

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II-34

II.7.1

Immittance corrections

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II-35

II.7.2

In-situ calibration

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II-36

II.8

Conclusion

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II-37

References

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II-37

IIIModelling fully depleted SOI MOSFET’s

 

III-1

III.1 Introduction

. III.1.1 The SOI MOSFET structure

. III.1.2 Operating modes of the generic SOI MOSFET structure

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III-1

III-3

III-3

 

III.1.3 Thin-film SOI MOSFET’s

III-4

III.1.4

Splitting the device in intrinsic and extrinsic regions

 

III-5

III.1.5

Requirements for a good MOSFET model for analogue circuit designIII-5

III.2 Charge-sheet models for the intrinsic device

 

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III-7

III.2.1 Surface potential and charge density equations

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III-8

. III.2.3 An analytical approximate charge-sheet model

III.2.2 A numerical charge-sheet model

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III-12

III-13

III.2.4 A dynamic model for the interface traps

 

III-16

III.2.5 Short channel effects

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III-17

III.3 Static conduction current

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III-20

III.3.1

Carrier velocity

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III-20

III.3.2 Triode operation

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III-21

III.3.3

Saturation

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III-23

III.3.4

Unified model

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III-28

III.4 Dynamic currents

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III-30

x

CONTENTS

III.4.1 Surface potential profile

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III-31

III.4.2

Front-gate charge

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III-32

. III.4.4 Ward’s channel-charge partitioning scheme

III.4.3 Back-gate charge

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III-34

III-34

. III.4.6 Alternative formulation of the charge model

III.4.5 Drain and source charges

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III-35

III-36

III.5 Operation at microwave frequencies

 

III-38

III.5.1 The non-quasi-static small-signal model topology

 

III-39

III.5.2 The distributed channel model at V DS = 0

III-41

III.5.3 A non-quasi-static large-signal channel model

III-44

III.6 Small-signal model for the extrinsic device

III-46

III.6.1 Diffusion and contact resistances

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III-46

III.6.2 Parasitic capacitances

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III-47

III.6.3 Lateral signal distribution in the basic MOSFET cell

III-50

III.6.4 Dedicated model for the common-source configuration .

III-53

III.7 Model limitations

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III-55

III.7.1 Channel length

III.7.2 Biasing conditions

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III-55

III-56

III.7.3 Scaling rules

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III-57

III.7.4

Frequency

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III-57

III.8 Conclusion

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III-58

References

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III-59

IV Extraction of SOI MOSFET model parameters

IV-1

IV.1 Introduction

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IV-1

IV.2 Substrate resistivity

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IV-3

IV.3 Three-terminal MOSFET model

IV.3.2 Channel length

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IV-3

IV.3.1 Shunt parasitic elements

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IV-7

IV-12

IV.3.3 Series parasitic elements

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IV-16

IV.4 Four-terminal MOSFET model

IV.4.1 Corrections to the shunt parasitic elements

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IV-25

IV-25

IV.4.2 Corrections to the series parasitic elements

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IV-29

IV.5 Intrinsic MOSFET in the linear operating regime

IV-32

IV.5.1 Determination of the C-V curve from broadband measurementsIV-32

 

IV.5.2 Threshold voltage

 

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IV-35

IV.5.3

Mobility .

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IV-36

IV.5.4 Unified analytical model from depletion to inversion

 

IV-38

IV.6 Intrinsic MOSFET in saturation

 

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IV-40

IV.7 Conclusion

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IV-44

References

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IV-44

V Microwave MOSFET downconversion mixers

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V.1

Introduction .

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V-1

V-1

V.2

. Single FET mixers

 

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V-2

V.2.1

Active mixers

 

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V-3

V.2.2

Passive mixers

 

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V-6

xi

CONTENTS

V.3

V.2.3

Balanced mixers

V.3.1

The MOSFET switch

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V-7

V-8

V-9

V.3.2

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V-11

V.4

A low-IF down-conversion architecture

 

V-13

V.4.1

Basic IF cell

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V-15

V.4.2

Quadrature generation

 

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V-15

V.4.3

Evaluation chip

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V-17

V.5

Conclusion

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