Proceedings of the International Conference on Communication & Signal Processing 2012, Adhiparasakthi Engineering College, Melmaruvathur, Kanchipuram, T.N.

., India. 4-5 April,2012, pp.169-174.

Design of Low power FIR Filter Structure using GDI Technique using 90nm Technology
R.R.Thirrunavukkarsu and D.Malathy Kongu Engineering College, Perundurai, Erode India thirrunavu@gmail.commalathy@kongu.ac.in

Abstract -FIR filter is a key component in the Digital Signal Processing applications(DS P). This paper presents the design of an energy efficient FIR filter using GDI Technique. The addition operation in the filter is optimized, so that delay and power is reduced. Simulation results shows that the power for the FIR filter is 24mW when compared with the conventional CMOS FIR filter that dissipates58.5mW. The power consumption of GDI FIR filter is obtained using 90nm Technology. The FIR Filter consumes lesspower when evaluated. Key Words: Full Adder, CMOS , GDI, FIR.

commonly used in almost all DSP applications. Others forms such as cascade and Lattice forms are occasionally used. 1.1 Direct Form Structure In the time -domain the input and output relation of the FIR filter is given by (1)

I. INTRODUCTION Filteris desirable to have circuits capable of selectively filtering one frequency or range of frequencies out of a mix of d ifferent frequencies in a circuit. A circu it designed to perform this frequency selection is called a filter. No ise is a rando m phenomenon does not carry useful information and always undesirable. Noise and other unwanted parts of a signal can be removed by filters. The types of Filters are broadly classified as analog and digital. An analog filter usually analog electronic circuits made fro m co mponents such as resistors, capacitors and op amps to produce the required filtering effect. Such filters are widely used in applicat ions such as noise reduction, video signal enhancement, graphic equalizers in hi-fi systems and many other areas . A digital filter uses a digital processor to perform numerical calculations on sampled values of the signal. The processor may be general purpose computer such as PC and specialized DSP chip. The time do main classification of a dig ital transfer function based on the length of its impulse response sequence leads to the finite impulse response and infin ite impulse response transfer functions.The impulse response is finite because there is no feedback in the Fin ite Impu lse Response (FIR). A lack of feedback guarantees that the impulse response will be fin ite. FIR filter can be implemented in two forms, the direct-form and transpose-form. These structures are

Figure 1.1 Direct form 8-tap FIR filter x(n) is the input signal, y(n) is the output signal, h(k)are the filter coefficients, also known as tap weights N is the filter order X(nk) in these terms are common ly referred to as taps FIR filters are important building blocks for various digital signal processing (DSP) applications. The other applications concerned with this filters includes video signal processing, transmission, mobile co mputing and mu ltimed ia applications and demands high performance and low power VLSI Dig ital Signal Processing Systems (DSP).

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FIR d igital filters arethe fundamental processing elements by virtue of stability and easy implementation. However, the large nu mber of involved mu ltip licat ions leads to excessive hardware comp lexity and power consumption. The FIR filter is compos ed of mu ltip licat ions and additions . The performance of mu ltip licat ions and adders determines the speed of FIR filter is represented by the following equation.

Most of the Very Large Scale IC (VLSI) applications, such as digital signal processing and microprocessors, use arithmet ic operations extensively. In addition, among these widely used operations, subtraction and mu ltiplication are most common ly applied. The single bit full adder is the building block of these operation modules. Therefore, enhancing its performance is crucial in overall modules. II. LITERATURE REVIEW Considering customized performance of d ifferent logics of full adders existing are conventional 20transistor transmission gate full adder[2], Conventional Co mplementary CMOS fu ll adder[3], 14-t ransistor 1-bit full adder[4],10-transistor 1-b it full adder cell[5].The block diagram of full adder is shown in the figure 2.1

Reconfigurable Architectures for ImplementingFIR Filters with Low Co mplexity[7] in mu lt istandard wireless communicat ion systems uses Reconfigurability architectures proposed for low co mp lexity are Constant Shifts method and Programmable shifts method. Proposed architecture reconfigurable and Lo w co mplex FIR filter offers good area, power reductions and speed improvement co mpared to other reconfigurable FIR implementations.A Novel VLSI Architecture for Low power FIR Filter[8] describes that a novel Wallace tree mu ltip lier is proposed which consumes 48% less power than conventional multip lier architecture. The power consumed by adder structure is also very significant wh ile designing a low power filter. The trade off occurs here as 16-bit input ripple carry adder consumes more power than carry look ahead adder. In a Lo w Power Linear Phase Digital FIR Filter for Wearable ECG Devices [9] the filter architecture reduces thearithmetic operat ions for each sample wh ich in turn lowersthe power consumption. The filter is designed fro m interpolated fin ite impulse filter technique.It is advantageous as it improves the attenuation at notch frequencies and in the stopband, compared with the existingdesigns. The Infinite Impulse Response (IFIR) based ECG Filter is suitable for VLSI Implementation for portable ECG devices.Low Power Dig ital FIR Filter based on low power mu ltip liers [10] to reduces dynamic power consumption of a digital Fin ite Impu lse Response filter. The method include low power serial mu ltiplier and serial adder, co mbinational booth mu ltiplier, shift/add mu ltip liers, fo lding transformation in linear phase architecture and it is applied to FIR filters to minimize the glitches, the power consumption is also reduced. For reduced power consumption and area, the technique includes combination of Booth mult iplier, lo w power serial mult iplier and serial adder, mu lt iplier based on shift/add in two forms and folding t ransformat ion. In Low Power Imp lementation of Linear Phase FIR Filters for Single Mult iplier[11] includes linear phase FIR filters and its imp lementationdeals with the two co mmon methods. It also describes an effective framework wh ich co mb ines layout, timing and capacitive informat ion and finally results in the net power reduction. III. PROPOSED METHOD

Figure 2.1 Block Diagram of Full Adder In the case of Memory Based Realization of Dig ital filter[6],the look-up-table (LUT)-mu ltiplier-based approach is used, thememory elements store all the possible values of products of thefilter coefficients . It is be an area-efficient alternative to Distributed Arith meticbaseddesign of FIR filter with the same throughput of implementation. The trade-off occurs at the cost of high order widths than other conventional method.New

The basic circuit for Gate Diffusion Input (GDI)

Figure 3.1 Basic GDI Cell

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CMOS Inverter.The GDI cell contains three inputs -G (common gate input of NM OS and PMOS), P (input to the source/drain of PMOS), and N (input to the source/drain of NM OS).Bulks of both NMOS and PM OS are connected to N or P respectively, so that it can be arbitrarily biased in contrast to CMOS inverter.Tab le 1 shows how a simple change of the input configuration of the Basic GDI cell co rresponds to different Boolean function. Most of these functions are complex (612transistors) in CM OS, as well as in standard PTL implementations, but very simp le (only 2transistors per function) in GDI design method.
T able 1: Some logic functions that can be implemented with a single GDI cell

functions. The second stage must have enough driving capability to drive output stages. So, the drivability and decoupling of second stage is important. So one inverter is added per each cell and it is suitable for fu ll signal swing and decoupling of inputs and outputs . New addercell can be cascaded arbitrarily and work reliably in any circu it configuration. Thus the second stage which produces SUM and Couthave enough driving capability.The output inverter guarantees sufficient drive tothe cascaded cells.In this full adder cell, a circu it based on complementary CMOSlogic style is used. Its robustness against voltage scaling and transistor sizing enables it tooperate reliab ly at low voltage.

XOR and XNOR functions are the important one for the Full adder equations. Thus enhancing the performance of XOR and XNOR functions will imp rove the performance of Full adder. The GDI cell uses ten transistors to built the XOR/ XNOR circuit which is free fro m the logic degradation. The circuit for XOR/XNOR using GDI cell is shown in figure 3.2

Figure 3.3 GDI Full Adder using GDI XOR/XNOR gate For FIR Filter design, the basic components needed are Full Adder, Ripple Carry Adder, D-Flip Flop and Multiplier. The design of 8-bit input Low Power FIR Filter using GDI Technique consists of 16-b it GDI Ripple Carry Adder, 8x8 GDI array mult iplier and 8-b it GDI DFlipFlop. The 16-b it GDI Ripple carry adder is made up of 16-GDI Full Adders which includes 16-bit inputs as X and Y, the output are 16-b it Su m and One Carry.The 8x8 GDI Array mu ltip lier can be constructed from GDI AND gate,GDI Full adders and GDI Half adders. The structure of 4x4 GDI Array mult iplier is shown in the figure 3.4The structure of 4x4 GDI array mult iplier consists of 16- GDI AND gates, 4-GDI Half Adders and

Figure 3.2 XOR/XNOR Circuit using GDI Cell The GDI Full Adder using XOR/ XNOR is shown in figure 3.3 consists of 26 Transistors. The first stage of the Full Adder cell is used to generate XOR/XNOR Fig 3.4 8- GDI full adder

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a3

a2

a1

b0 b1 HA b2 FA b2 FA FA HA p2 FA FA HA p1 p0

FA

FA

FA

HA

a0

p3 p4 p5 p6 p7

Figure 3.4 4x4 Array Multiplier using GDI Technique The structure of 8x8 GDI array mult iplier is shown in the figure 3.5. It consists of 8-bit mu ltip lier, 8-b it mu ltip licand as input and 16 bit part ial products as output.

two GDI D-Latches[13]. Each latch consists of four basic GDI cells, resulting in a simp le eight-transistor structure.

The delay element for the GDI FIR Filter is usually made up of D-Flip Flop. GDI based D-Flip Flop is used as the delay element in FIR Filter design. The transistor structure for GDI D-Flip Flop is shown in the figure 3.6.It is based on the master-slave connection of

Figure 3.6 GDI D-Flip Flop

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The GDI DFF design allowsreducing power-delay product and area of the circuit,wh ile maintaining low co mp lexity of logic design. The relatively compact structure of the GDI DFF,containing 18 transistors (with the inverter forco mplementary value of D), makes it efficientwith low area andhigh performance.The 8-b it GDI D Flip Flop is shown in Figure 3.7. The CLK frequency used in 8-b it GDI D-Flipflop is 250MHz.

IV. SIMULATION RESULTS AND DISCUSSION The simulated output for Low power 8-Tap FIR filter using GDI Technique in figure 4.1 & 4.2 has been implemented in direct form. Based on the transistor level implementation, it has been synthesized by using Synopsys Custom Designer Toolusing 90n m Technology. The supply voltage is 1.2V.

Figure 3.7 8-Bit GDI D Flip Flop

Figure 4.1 Simulated output for Low Power 8-tap FIR Filter using GDI Technique

Figure 3.8 GDI FIR Filter Structure

Using the above designed components such as GDI Full Adder, 16-bit GDI Ripple Carry Adder, 8x8 GDI Array Multip lier and 8-b it GDI D-Flip Flop, FIR filter is designed. The transistor level structure of Low Vo ltage Lo w Power 8-tap FIR Filter using GDI Technique is shown in the figure 3.8. It consists of eight number of 8-bit GDI D-Flip Flops, eight nu mber of GDI 8x8 array mult ipliers and seven 16-b it GDI Ripple Carry Adders. The delay elements in 8-tap FIR Filter is constructed by 8-bit GDI D-Flip Flop. The input of 8-tap FIR Filter using GDI technique has 8-bit input, which is represented in 8-b it binary format.The tap weights are series of constants, used to multip ly against delayed sample values called coefficients. Figure 4.2 Simulated output for Low Power 8-tap FIR Filter using GDI Technique The table 4.1 represents the number of t ransistors constructed by basic blocks and it shows that number of transistor count is reduced by using GDI method when compared to the static conventional CMOS method. The number of transistors required to construct the FIR filter structure using GDI and Conventional CMOS technique is

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comparisonof Conventional and GDI method FIR filter is shown in the table 4.3 Table 4.1 Number of transistors in Each Cell

[7]

Name of Cells Half Adder Full Adder 8x8 array multiplier D-Flip Flop 8-tap FIR filter
V. CONCLUSION

Conventional Method 18 28 1872 24 19456

GDI Method 6 26 1424

[8] [9]

[10] [11]

18
[12]

15312

[13]

R. Mahesh and A. P. Vinod New Reconfigurable Architectures for ImplementingFIR Filters with Low ComplexityIEEE Transactions On Computer-Aided Design Of Integrated Circuits and Systems, VOL. 29, NO. 2, February 2010. A.M.VijayaPrakash and K.S.Gurumurthy, A Novel VLSI Architecture for Low power FIR Filter.International Journal of Advanced Engineering & Application, Jan 2011 Issue. Yong Lian and Jianghong Yu, A Low Power Linear Phase Digital FIR Filter for Wearable ECG Devices. Proceedings of the 2005 IEEE Engineering in Medicine and Biology 27th Annual Conference Shanghai, China, September 1-4, 2005. BahramRashidi, BahmanRashidi and MajidPourormazd, Design and Implementation of Low Power Digital FIR Filter based on low power multipliers and adders on xilinx FPGA, IEEE 2011. A.T . Erdogan and T. Arslan, Low power Implementation of Linear phase FIR filters for single multiplier CMOS based DSPs, IEEE 1998. Mehdi Faed, Dr. Mohammad Mortazavi andAlirezaFaed,Analysis of Digital DSP Blocks Using GDI T echnology IEEE 2010. ArkadiyMorgenshtein,Alexander Fish and Israel A. Wagner An Efficient Implementation of D-flip-flop using the GDI T echnique,IEEE 2004.

The output value obtained using GDI FIR filter is free fro m glitches and power consumption is reduced when compared with the static conventional CMOS FIR filter. The simu lation results are performed in Synopsys custom Designer Tool using 90 n m Library Technology. The power factor and area value of FIR filter using GDI technique is improved to the static conventional CM OS FIR filter. The Samp le period of CLK cycle for the FIR filter is 4ns and CLK frequency value is 250M Hz. The future work is to draw the layout for the GDI FIR filter and verify the RC extraction with back annotation. Table 4.2 Performance Comparison of FIR Filter Performance Power Area Conventional FIR Filter 58.5mW 408.6 m2 GDI FIR Filter 24mW 321.5m2

REFERENCES
[1] AlirezaSaberkari, Shahriar B. Shokouhi, A Novel Low-Power Low-Voltage CMOS1-Bit Full Adder Cell with the GDI Technique, Proceedings of the 2006 IJME - INTERTECH Conference. J. P. Uyemura. Fundamentals of MOS Digital Integrated Circuits. Reading, Addison-Wesley, pp. 136-137. N. Weste and K. Eshraghian, Principles of VLSI Design, A System Perspective, Reading, MA: Addison-Wesley, 1993. E. Abu Shama, A. Elechouemi, S. Sayed and M. Bayoumi. An Efficient Low Power BasicCell for Adders. Proc. 38th Midwest Symposium on Circuits and Systems, pp. 306-309, 1996. A. A. Fayed and M. A. Bayoumi. A Low Power 10 Transistor Full-Adder Cell for EmbeddedArchitectures. IEEE International Symposium on Circuits and Systems, pp. 226-229, 2001. Pramod Kumar Meher,New Approach to Look-Up-Table Design and Memory-Based Realization of FIR Digital Filter.IEEE Transactions On Circuits and SystemsI: Regular papers, VOL. 57, NO. 3, March 2010.

[2] [3] [4] [5] [6]

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