POWER

DISSIPATION IN FPGA DEVICES

RICHARD FABIAN RODRIGUEZ JAIME ANDRES SALAZAR UNIVERSIDAD DEL VALLE

CONTENT
1. INTRODUCTION 2. POWER DISSIPATION: concept, components and equaIon. 3. POWER ESTIMATION TECHNIQUE FOR FPGA.
3.1- Switching acIvity 3.2- Capacitance

4. FPGA vs. ASIC 5.CONCLUSIONS

1. INTRODUCTION
Development of portable compuIng system. Power dissipaIon is becoming one of the most important issue to consider in the design of FPGA based systems. FPGA is becoming more popular because CMOS technology improves at an exponenIal rate but power dissipaIon diers a lot compared to ASIC based systems.

2. POWER DISSIPATION
ASIC power components: Dynamic and staIc components. JuncIon leakage and tunneling gate currents are not considered. FPGA power components (all 3 with dynamic and staIc components): Power up component. ConguraIon component. ExecuIon component.

 First term= dynamic power. ExponenIal Vdd. Second term= staIc power. Vdd= voltage source supply. C=parasiIc capacitance. F= operaIng frequency. = acIvity of the circuit. Vt= threshold voltage of the transistor. S= slope factor. U= uIlizaIon of a resource. Si= switching acIvity of a resource. i= number of a resource in a FPGA. Io= reverse current.

3. POWER ESTIMATION TECHIQUE FOR FPGAs

The work of Jason H. Anderson and Farid Najm, shows a method by calculaIng FPGA power consumpIon by FPGA interconnect. They studied two special problems: Switching acIvity predicIon. Interconnect capacitance predicIon. They propose a model for predicIng these parameters when accurate rouIng data is incomplete or unavailable. In this study it is use Xilinx Virtex II PRO commercial FPGA for invesIgaIon. Switching acIvity is studied and examine if zero delay acIvity values can be used reliably as esImates of the calculaIon of routed delay acIvity values.

 PredicIon Methodology Overview

Target parameters: Nets routed delay acIvity predicIon. Interconnect capacitance predicIon. PredicIon parameters: values know before rouIng compleIon. General steps: A set of benchmark circuits are selected and mapped into Virtex II PRO. The circuits are divided into two sets: characteriza3on set and test set. The characterizaIon circuits are analyzed and predicIon and target parameters values are extracted. Then with these parameters, they perform mulI-variable regression analysis to establish an empirical relaIonship between these. Apply predicIon models to predict capacitance and routed delay acIvity values for nets in the test circuits.

3. 1 Switching AcIvity
Switching acIvity of a net in a FPGA is signicant in the calculaIon of power. We can conceive dierent views of this acIvity: Zero delay acIvity Logic delay acIvity Routed delay acIvity. When delays are considered, switching acIvity normally increases because the introducIon of glitches. An understanding of how switching acIvity changes when delays are considered is important because: FPGA power dissipaIon is dominated by interconnecIon. Due to the presence of programmable switches in the interconnecIon network, path delays in FPGAs are dominated by interconnect rather than by logic delays, suggesIng the the eect of glitches will be greater in FPGAs than in ASIC.

Switching AcIvity Analysis

SimulaIon-based approach using 10k random input vector. Two dierent vector sets: represents high input acIvity and low input acIvity. TabulaIon of comparison of total number transiIon in the logic and routed delay simulaIons of each circuit, with the number of transiIons in the zero delay simulaIon. Signicant increase in acIvity when delays are considered. The increase in acIvity are some how less drasIc when low acIvity vector set were used. Conclusion: zero and logic delay acIvity values do not necessarily correlate strongly with routed delay acIvity values.

Switching AcIvity PredicIon Model

The combinaIonal part of a logic circuit can be represented as a Boolean Network. Boolean Network: directed acyclic graph (DAG). Node: single- output logic funcIon. Edges between nodes: input-output dependencies between the corresponding logic funcIons. For a node y in a circuit DAG: Inputs(y)=the set of nodes that are fanins of y. Depth of a node y (Dy)= the length of the longest path from any primary input to y.

Switching AcIvity PredicIon Model

PRy: PredicIve funcIon that represents the severity of glitching on ys outputs. GENy: Amount of glitching generated by y. PROPy: Amount of glitching propagated by ys inputs. Dy: Depth of the node y. PLy: represent the set of dierent path lengths from a primary input to node .

GENy: Amount of glitching generated by y. PROPy: Amount of glitching propagated by ys inputs.

3. 2 Capacitance
Early capacitance predicIon for FPGAs is not well studied, and is very dierent to calculate it in FPGAs than in ASIC because of the programmable nature of FPGA interconnecIon. Early works for esImates capacitance values used generic, non-architecture specic parameters to predict it.

Interconnect Capacitance PredicIon Model

CAD applicaIons are designed to calculate capacitance very quickly as they are needed to the inner loop of design and simulaIons algorithms. So parameters are chosen by a low computaIonal criteria. Some of these are not needed but they are menIoned.

Results

4. Power dissipaIon: FPGA vs. ASIC

ASIC:

Vdd= voltage source supply. Vt= threshold voltage of the transistor.

4.1 ASIC

ASIC
All these techniques are ASIC oriented and their eciency when implemented in FPGA has not yet been demonstrated.

4.2 FPGA
There are three power components: Power-up component ConguraIon component ExecuIon component

4.3 Experimental Results

ASIC: Synopsys Design Compiler, Power Compiler, VCS, Prime Power. FPGA: Quartus II v4.2, Powerplay.

4.3.1 Counters

4.3.1 Counters

4.3.2 Hadamard Transform IP

4.3.2 Hadamard Transform IP

IP power dissipaIon in ASIC

4.3.2 Hadamard Transform IP

5. CONCLUSIONS
FPGA devices will never compete with ASIC for applicaIons where low power is an issue because their intrinsic generic architecture. The FPGA will be conned to circuit prototyping for funcIonal validaIon or recongurable compuIng.

BIBLIOGRAPHIC REFERNCES
[1] AMARA AMARA, Frederic y AMIEL, Thomas. FPGA vs. ASIC for low power applica3ons InsItuto Superior de Electronica de Paris. 2005. [2] ANDERSON, Jason H. NAJM, Farid N. Power es3ma3on Techniques for FPGAs 2004.