Chip Design Training Plan June 2012

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Contents
Section I: Basic Chip Design Technology Training Section II: Product Development Training Section III: Product Verification Training

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Section I: Basic Chip Design Technology Training

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Basic Chip Design Technology Training

Subject 1: Verilog Language Subject 2: Verilog Coding Standard Subject 3: RTL Design Guidelines Subject 4: Testbench Design Guidelines Subject 5: Telecom Basic Subject 6: Small design Exercises

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Verilog Language Training (1)

Chapter 1 Introduction Major features of the Verilog HDL Rationale for synthesis policy Chapter 2 Lexical Conventions How the language interprets How to specify lexical tokens White space Comments Attribute delimiters Numbers Character strings Identifiers Keywords Operators

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Verilog Language Training (2)

Chapter 3 Data Types Registers Nets Constant values Chapter 4 Expressions Operators Operands Chapter 5 Assignments Continuous assignments Procedural assignments Chapter 6 Gate and Switch Level Modeling Gate and switch level primitives Declarations Specifications

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Verilog Language Training (3)

Chapter 7 User-Defined Primitives (UDPs) How a primitive can be defined in the Verilog HDL How these primitives are included in Verilog models Chapter 8 Behavioral Modeling Procedural assignments Behavioral language statements Chapter 9 Tasks and Functions Tasks Functions Procedures to call tasks and functions in a behavioral model How tasks can be used like subroutines How functions can be used to define new operators.

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Verilog Language Training (4)

Chapter 10 Disabling of Named Blocks and Tasks Disable the execution of a task Disable the execution of a block Chapter 11 Procedural Continuous Assignments Type of procedural assignment called a procedural continuous assignment Chapter 12 Hierarchical Structures How model hierarchies are created in the Verilog HDL How parameter values declared in a module can be overridden Macro modules

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Verilog Language Training (5)

Chapter 13 Attributes Attribute framework Attribute classes Attribute types Attribute inheritance Attribute declaration Attribute and access mechanisms Chapter 14 Specify Blocks Verilog HDL constructs in a specify block

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Verilog Coding Standard (1)

Layout Conventions Source File Layout Testbench File Layout Testcase File Layout Function Layout Code Layout Vertical spacing Horizontal spacing Indentation Comments

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Verilog Coding Standard (2)

Naming Conventions Source, Testbench, and Testcase File Names Reset Signal Name Clock Tree Signal Name Constant Names Input and Output Names Wire and Register Names Active Low Variable Names Complex Conditionals Complex Conditionals RTL Mandatory Project Hierarchy

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RTL Design Guideline (1)

Coding Organization Coding Formatting Design Partitioning Circuit Concepts Timing Model Timing Closure Synchronous Design techniques Synchronization Concepts Single signal synchronization Synchronization Pitfall Metastability Bus synchronization 4 Phase Handshaking 2 Phase Handshaking Handshaking without ACK
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RTL Design Guideline (2)

Creating Safe State Machine Pipeline FIFO Design Guide Line RAM interface CPU interface Common Engine Buffer Management Introduce Link Buffer Method Scan Test

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Testbench Design Guideline (1)

Test Structure Design Data Structure Database Structure Coding Conventions Testbench Structure Generator Generate a frame data stream Generate errors Control error insertion Data type in data stream Analyzer Scan even FIFO Report Errors Text display format Testcase Test Progress Test Case Struture
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Testbench Design Guideline (2)

Memory Test guide line Test progress on Mem test Test progress on test Data generate method Fault covering Observe the test result Run test case Text display Wave form display Short Frame, Scale Down, Test Mode

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Telecom Basic (1)

Networking, Switching and Transmission Circuit based Packet based TDM PDH: o DS1/3, E1/3, M13/E13 o Packet mapped DS3 C-bit, E3 G.832 VCAT/LCAS o SDH/SONET PDH mapped (AU/STS, TU/VT) Packet mapped, VCAT/LCAS (HO/LO)

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Telecom Basic (2)

Packet HDLC/PPP GFP ATM PSN: o Ethernet-based switching o MPLS-based forwarding o IP-based (UDP/L2TP) routing Protection Linear SNCP/UPSR MSSP/BLSR

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Telecom Basic (3 )
Clock & Synchronization Jitter & Wander PDH, SDH/SONET Packet: o Network Sync Ethernet IEEE 1588 o Service DCR ACR Bonding IMA MLPPP OAM QoS

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Section 2: Product Development Training

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Slide 19

Product Development Training

Subject 1: Product Requirements Subject 2: RTL Design Subject 3: Testbench Design Subject 4: Simulation Subject 5: Device Driver Design

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Section 3: Product Verification Training

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Slide 21

Product Verification Training

Subject 1: Board Schematic Design Subject 2: Board Layout Design Subject 3: Operating System Modification/Porting Subject 4: Board Bring-up and Debug Subject 5: On-board Testing

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