Vous êtes sur la page 1sur 5

Datorarkitektur I

F 10 - 1

Datorarkitektur I

F 10 - 2

Lets Have a Look into the CPU

THE CONTROL UNIT

I/O 1

I/O 2

I/O n

System Bus 1. Why is a Control Unit Needed inside the CPU? CPU 2. Microoperations and Control Signals 3. The Control Unit - Basic Tasks System Bus 4. Hardwired Control 5. Microprogrammed Control ALU CPU Registers Main Memory

Control Unit Internal CPU Bus

IR PC

Datorarkitektur I

F 10 - 3

Datorarkitektur I

Address Bus
F 10 - 4

Control Bus Fetch instruction Execute instruction

Instruction Execution
Lets Have a Look into the CPU (contd) The CPU executes a sequence of instructions. The execution of an instruction is organized as an instruction cycle: it is performed as a succession of several steps;

The question that has to be answered: How are the elements inside the CPU and the interface to the external datapath controlled in order to work properly?

To perform this control, thats the task of the Control Unit

Each step is executed as a set of several microoperations. The task performed by any microoperation falls in one of the following categories: - Transfer data from one register to another; - Transfer data from a register to an external interface (system bus); - Transfer data from an external interface to a register; - Perform an arithmetic or logic operation, using registers for input and output.

Data Bus

Datorarkitektur I

F 10 - 5

Datorarkitektur I

F 10 - 6

Instruction Execution (contd)


PCin

Microoperations and Control Signals

Control signals In order to allow the execution of a microoperation, one or several control signals have to be issued; they allow the corresponding data transfer and/or computation to be performed. Examples: a) signals for transferring content of register R0 to R1: R0out, R1in b) signals for adding content of Y to that of R0 (result in Z): R0out, Add, Zin c) signals for reading a memory location; address in R3: R3out, MARin, Read The CPU executes an instruction as a sequence of control steps. In each control step one or several microoperations are executed. One clock pulse triggers the activities corresponding to one control step for each clock pulse the control unit generates the control signals corresponding to the microoperations to be executed in the respective control step.

PC
PCout MARin

Status&Cond. Flags

Control unit
IRin

System bus

MAR
MBRin

Clock

IR
IRout

MBR
MBRout Yin R0in

R0
R0out

Clear Y

Y
Yout

Add XOR Zin

ALU
Rn-1in Carry-in

Rn-1 Z
Zout Rn-1out

Datorarkitektur I

F 10 - 7

Datorarkitektur I

F 10 - 8

Microoperations and Control Signals (contd) Microoperations and Control Signals (contd) instruction: ADD R1,R3 R1 R1 + R3 instruction: BR

target

control steps and control signals: fetch ins. PCPC+1 1 2 3 4 5 6 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin R1out, Yin R3out, Add, Zin Zout, R1in, End

unconditional branch (with relative addressing - see lect. 5)

control steps and control signals: fetch ins. PCPC+1 1 2 3 4 5 6 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin PCout, Yin (displacement-eld)IRout, Add, Zin Zout, PCin, End

instruction: ADD

R1,(R3)

R1 R1 + [R3] Comments: The rst (three) control steps are identical for each instruction; they perform instruction fetch and increment the PC. The following steps depend on the actual instruction (stored in the IR). If a control step issues a read, the value will be available in the MBR after one additional step. Several microoperations can be performed in the same control step if they dont conict (for example, only one of them is allowed to output on the bus)

control steps and control signals: fetch ins. PCPC+1 1 2 3 4 5 6 7 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin indirect addressing R3out, MARin, Read R1out, Yin MBRout, Add, Zin Zout, R1in, End

Datorarkitektur I

F 10 - 9

Datorarkitektur I

F 10 - 10

Control Unit

Control Unit (contd)

Status&Cond. Flags

The basic task of the control unit: - for each instruction the control unit causes the CPU to go through a sequence of control steps; - in each control step the control unit issues a set of signals which cause the corresponding microoperations to be executed.

IR

Control signals internal to the CPU Control unit Control signals on system bus Signals from system bus

The control unit is driven by the processor clock. The signals to be generated at a certain moment depend on: - the actual step to be executed; - the condition and status ags of the processor; - the actual instruction executed; - external signals received on the system bus (e.g. interrupt signals).

Clock

Techniques for implementation of the control unit: 1. Hardwired control 2. Microprogrammed control

Datorarkitektur I

F 10 - 11

Datorarkitektur I

F 10 - 12

Hardwired Control
Hardwired Control (contd) In this case, the control unit is a combinatorial circuit; it gets a set of inputs (from IR, ags, clock, system bus) and transforms them into a set of control signals. IR

Instruction decoder I1 I2 I3 In Status&Cond. Flags

Generation of signal Zin: - rst step of all instructions (fetch instruction) - step 5 of ADD with register addressing - step 5 of BR - step 6 of ADD with register-indirect addressing - ------------------Zin = T1 + T5 (ADDreg + BR) + T6 ADDreg_ind + . . .

Reset Step counter and decoder

T1 T2 Encoder block (combinatorial signal generator)

Clock

Tn

Generation of signal End: - step 6 of ADD with register addressing - step 7 of ADD with register-indirect addressing - step 6 of BR - ------------------End = T6 (ADDreg + BR) + T7 ADDreg_ind + . . .

From system bus

End Control signals

Datorarkitektur I

F 10 - 13

Datorarkitektur I

F 10 - 14

Control signals Hardwired Control (contd) Control unit Hardwired control provides highest speed. Clock RISCs are implemented with hardwired control. If the instruction set becomes very complex (CISCs) implementing hardwired control is very difcult. In this case microprogrammed control units are used. In order to allow execution of register-to-register operations in a single clock cycle, RISCs (and other modern processors) use three-bus CPU structures (see following slide). IR PC R0 Status&Cond. Flags

Rn-1

MBR MAR System bus

Datorarkitektur I

F 10 - 15

Datorarkitektur I

ALU

F 10 - 16

Microprogrammed Control
Control word (CW): a sequence of Nsig bits, where Nsig is the total number of control signals; each bit in a CW corresponds to one control signal. Each control step during execution of an instruction denes a certain CW; it represents a combination of 1s and 0s corresponding to the active and nonactive control signals. Microroutine: a sequence of CWs corresponding to the control sequence of a machine instruction. An individual CW in a microroutine is called a microinstruction.

Microprogrammed Control Unit


Status&Cond. Flags

IR

Address generator (AG)

PC INCR

Control store (CS)

gen. addr

Microprogrammed control - basic idea: All microroutines corresponding to the machine instructions are stored in the control store. The control unit generates the sequence of control signals for a certain machine instruction by reading from the control store the CWs of the microroutine corresponding to the respective instruction.

IAB Control buffer/ decoder (CB/D) end, end-fetch branch

Clock

Sequencer

The control unit is implemented just like another very simple CPU, inside the CPU, executing microroutines stored in the control store.

Signals from system bus

Control signals

IAB: Internal Address Bus

Datorarkitektur I

F 10 - 17

Datorarkitektur I

F 10 - 18

Control Store Organization


Microroutine Executed for Conditional Branch Addr-fetch Control store ----------------------------------------end-fetch ----------------------------------------branch addr-fetch ----------------------------------------end ----------------------------------------end Fetch instruction Interrupt routine Execute instr. code 0 Execute instr. code 1 A_fetch +1 +2 +3 A_CB +1 +2 +3 +4 +5 PCout, MARin, Read, Clear Y, Carry-in, Add, Zin Zout, PCin MBRout, IRin end-fetch this produces the jump to A_CB -------------branch to A_CB+2 if N set end PCout, Yin (displacement-eld)IRout, Add, Zin Zout, PCin end

Addr-interr.

Addr-instr0

Addr-instr1

Addr-instrn

----------------------------------------end

Execute instr. code n

The control store contains the microprogram (sometimes called rmware).

The microroutines contain, beside CWs, also branches which have to be interpreted by the microprogrammed controller. The sequencer is controlling the right execution sequence of microinstructions. The sequencer is a small control unit of the control unit.

Datorarkitektur I

F 10 - 19

Summary

The control unit is in charge of coordinating the activities inside the CPU and the interaction with the outside. It is doing this by issuing in each clock cycle the appropriate control signals. A set of control signals activates the microoperations which have to be executed in a given control step. Control units can be implemented hardwired or microprogrammed. A hardwired control unit is a combinatorial circuit which gets a set of inputs and transforms them into a set of control signals. A microprogrammed control unit is implemented like another CPU inside the CPU. It executes microprogrammes stored in the control store. Each instruction of the microprogram practically represents the set of signals which the control unit has to issue in the respective control step. Hardwired controllers are faster then microprogrammed ones. They are used in all RISCs. If the instruction set is complex, hardwired controllers become too complicated. Therefore CISCs are implemented with microprogrammed controllers.