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  • Computer Architecture: Cache Memory

    Transféré par

    Edwin Fock
    34 vues30 pages
    This document discusses cache memory in computer architecture. It describes the key characteristics of cache including location, capacity, unit of transfer, access methods, and performance. Caches are located internally and externally close to the CPU. They have smaller capacity than main memory but faster access times. Caches use block transfers and support direct, sequential, random, and associative access methods. The memory hierarchy includes registers, caches at multiple levels, main memory, and external storage. Faster access requires caches closer to the CPU but with higher cost and complexity.

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    CA Session 02

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    This document discusses cache memory in computer architecture. It describes the key characteristics of cache including location, capacity, unit of transfer, access methods, and performance. Caches are located internally and externally close to the CPU. They have smaller capacity than main memory but faster access times. Caches use block transfers and support direct, sequential, random, and associative access methods. The memory hierarchy includes registers, caches at multiple levels, main memory, and external storage. Faster access requires caches closer to the CPU but with higher cost and complexity.

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    34 vues30 pages

    Computer Architecture: Cache Memory

    Transféré par

    Edwin Fock
    This document discusses cache memory in computer architecture. It describes the key characteristics of cache including location, capacity, unit of transfer, access methods, and performance. Caches are located internally and externally close to the CPU. They have smaller capacity than main memory but faster access times. Caches use block transfers and support direct, sequential, random, and associative access methods. The memory hierarchy includes registers, caches at multiple levels, main memory, and external storage. Faster access requires caches closer to the CPU but with higher cost and complexity.

    Droits d'auteur :

    Attribution Non-Commercial (BY-NC)
    Téléchargez comme PDF, TXT ou lisez en ligne sur Scribd
    Signaler comme contenu inapproprié
    sur 30

    ComputerArchitecture

    CacheMemory

    ARASHHABIBILASHKARI (April ( April 2010)


    ComputerArchitecture 02 1

    Characteristics
    Location Capacity Unitoftransfer Unit of transfer Accessmethod Performance P f Physicaltype Physicalcharacteristics Organisation
    ComputerArchitecture 02 2

    Location
    CPU Internal External l

    ComputerArchitecture 02

    Capacity
    Word size Wordsize
    Thenaturalunitoforganisation

    Number of words Numberofwords


    orBytes

    ComputerArchitecture 02

    UnitofTransfer Unit of Transfer


    Internal
    Usuallygovernedbydatabuswidth

    External
    Usuallyablockwhichismuchlargerthanaword

    Addressable unit Addressableunit


    Smallestlocationwhichcanbeuniquely addressed Wordinternally ClusteronM$disks
    ComputerArchitecture 02 5

    AccessMethods(1) Access Methods (1)


    Sequential q
    Startatthebeginningandreadthroughinorder Accesstimedependsonlocationofdataandprevious location e.g.tape

    Direct
    Individualblockshaveuniqueaddress Accessisbyjumpingtovicinityplussequentialsearch A Accesstimedependsonlocationandprevious ti d d l ti d i location e.g.disk
    ComputerArchitecture 02 6

    AccessMethods(2) Access Methods (2)


    Random
    Individualaddressesidentifylocationsexactly Accesstimeisindependentoflocationorprevious access e.g.RAM

    Associative
    Dataislocatedbyacomparisonwithcontentsofa portionofthestore Access time is independent of location or previous Accesstimeisindependentoflocationorprevious access e.g.cache
    ComputerArchitecture 02 7

    MemoryHierarchy Memory Hierarchy


    Registers
    InCPU

    Internal or Main memory InternalorMainmemory


    Mayincludeoneormorelevelsofcache RAM

    Externalmemory
    Backingstore

    ComputerArchitecture 02

    MemoryHierarchy Memory Hierarchy Diagram

    ComputerArchitecture 02

    Performance
    Access time Accesstime
    Timebetweenpresentingtheaddressandgetting thevaliddata

    MemoryCycletime
    Timemayberequiredforthememoryto recoverbeforenextaccess Cycletimeisaccess+recovery

    TransferRate
    Rateatwhichdatacanbemoved
    ComputerArchitecture 02 10

    PhysicalTypes Physical Types


    Semiconductor
    RAM

    Magnetic
    Disk&Tape

    Optical
    CD&DVD

    ComputerArchitecture 02

    11

    PhysicalCharacteristics Physical Characteristics


    Decay Volatility Erasable bl Powerconsumption

    ComputerArchitecture 02

    12

    Organisation
    Physical arrangement of bits into words Physicalarrangementofbitsintowords Notalwaysobvious e.g.interleaved i l d

    ComputerArchitecture 02

    13

    TheBottomLine The Bottom Line


    How much? Howmuch?
    Capacity

    How fast? Howfast?


    Timeismoney

    Howexpensive?

    ComputerArchitecture 02

    14

    HierarchyList Hierarchy List


    Registers L1Cache L2Cache L2 Cache Mainmemory Diskcache Di k h Disk Optical Tape
    ComputerArchitecture 02 15

    Soyouwantfast? So you want fast?


    It is possible to build a computer which uses Itispossibletobuildacomputerwhichuses onlystaticRAM(seelater) This would be very fast Thiswouldbeveryfast Thiswouldneednocache
    Howcanyoucachecache?

    Thiswouldcostaverylargeamount

    ComputerArchitecture 02

    16

    Cache
    Small amount of fast memory Smallamountoffastmemory SitsbetweennormalmainmemoryandCPU MaybelocatedonCPUchipormodule b l d C hi d l

    ComputerArchitecture 02

    17

    Cache/MainMemoryStructure Cache/Main Memory Structure

    ComputerArchitecture 02

    18

    Cacheoperation Cache operation overview


    CPUrequestscontentsofmemorylocation CPU requests contents of memory location Checkcacheforthisdata Ifpresent,getfromcache(fast) f f h (f ) Ifnotpresent,readrequiredblockfrommain memorytocache ThendeliverfromcachetoCPU Cacheincludestagstoidentifywhichblockof mainmemoryisineachcacheslot main memory is in each cache slot
    ComputerArchitecture 02 19

    CacheReadOperation Cache Read Operation Flowchart

    ComputerArchitecture 02

    20

    CacheDesign Cache Design


    Size MappingFunction ReplacementAlgorithm l l ih WritePolicy BlockSize NumberofCaches Number of Caches

    ComputerArchitecture 02

    21

    Sizedoesmatter Size does matter


    Cost
    Morecacheisexpensive

    Speed
    Morecacheisfaster(uptoapoint) Checkingcachefordatatakestime

    ComputerArchitecture 02

    22

    TypicalCacheOrganization Typical Cache Organization

    ComputerArchitecture 02

    23

    MappingFunction Mapping Function


    Cache of 64kByte Cacheof64kByte Cacheblockof4bytes
    i i.e.cacheis16k(214) li h i 16k (2 )linesof4bytes f4b t

    16MBytesmainmemory 24bitaddress
    (224=16M)

    ComputerArchitecture 02

    24

    WritePolicy Write Policy


    Must not overwrite a cache block unless main Mustnotoverwriteacacheblockunlessmain memoryisuptodate Multiple CPUs may have individual caches MultipleCPUsmayhaveindividualcaches I/Omayaddressmainmemorydirectly

    ComputerArchitecture 02

    25

    Writethrough Write through


    All writes go to main memory as well as cache Allwritesgotomainmemoryaswellascache MultipleCPUscanmonitormainmemory traffictokeeplocal(toCPU)cacheuptodate traffic to keep local (to CPU) cache up to date Lotsoftraffic Slowsdownwrites Rememberboguswritethroughcaches!
    ComputerArchitecture 02 26

    Writeback Write back


    Updates initially made in cache only Updatesinitiallymadeincacheonly Updatebitforcacheslotissetwhenupdate occurs Ifblockistobereplaced,writetomain memoryonlyifupdatebitisset l if d bi i Othercachesgetoutofsync I/Omustaccessmainmemorythroughcache N.B.15%ofmemoryreferencesarewrites N B 15% of memory references are writes
    ComputerArchitecture 02 27

    Pentium4Cache Pentium 4 Cache


    80386 noonchipcache 80486 8k i 16 b 80486 8kusing16bytelinesandfourwaysetassociative li df i i organization Pentium(allversions) twoonchipL1caches
    Data&instructions

    PentiumIII L3cacheaddedoffchip Pentium4


    L1caches
    8k b t 8kbytes 64bytelines fourwaysetassociative

    L2cache
    FeedingbothL1caches Feeding both L1 caches 256k 128bytelines 8waysetassociative

    L3 cache on chip L3cacheonchip


    ComputerArchitecture 02 28

    Pentium4BlockDiagram Pentium 4 Block Diagram

    ComputerArchitecture 02

    29

    Questions

    ComputerArchitecture 02

    30

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