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NOC-HoneyComb : A New structure for Network-On-Chip

Reza Kourdy Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran Mohammad Reza Nouri rad Department of Computer Engineering Islamic Azad University, Khorramabad Branch, Iran

AbstractThe future of on-chip communication is Networks-on-Chip (NoC), meaning that on-chip communication is done through packet based networks. Today System-on-Chips (SoC) uses shared buses as on-chip interconnection architecture. Networks-on-Chip (NoCs) have been suggested as a promising solution to the scalability problem of SoCs. The honeycomb mesh, based on hexagonal plane tessellation, is considered as a multiprocessor interconnection network. Vertex and edge symmetric honeycomb torus network is obtained by adding wraparound edges to the honeycomb mesh. The network cost, defined as the product of degree and diameter, is better for honeycomb networks than for the two other families based on square (mesh-connected computers and tori) and triangular (hexagonal meshes and tori) tessellations. Index Terms honeycomb mesh, honeycomb torus, Network on Chip, System on Chip, NoC Architecture.

1 INTRODUCTION

etwork-on-a-chip (NoC) is a new approach to System-on-a-chip (SoC) design. NoC deals with the design challenges of SoC. It deals with Communication infrastructure between heterogeneous structures. It consists of structured wiring and cross talk is no concern due to routers NoC based systems can accommodate multiple asynchronous clocking. The NoC solution brings a networking method to on-chip communication and brings notable improvements over conventional bus systems. As Integrated circuit technology develops very fast so in future there is a possibility of having billions of transistors on one single chip. Using shared buses to design communication platforms can bring a number of issues such as the increase of wire delay, the controlling of power distribution and power dissipation and also the ability to guarantee signal integrity. To overcome these issues a new technique has been introduced which is called Network-on-Chip (NoC) and it suggests that future on-chip communication should work as a network[1]. Various research and development results on how to interconnect multiprocessor components have been reported in literature. Several surveys of parallel computing architectures exist (e.g., [2], [3]). One of most popular architectures is the mesh-connected computer (see Fig. 1), in which processors are placed in a square or rectangular grid, with each processor being connected by a communication link to its neighbors in up to four directions. Tori are meshes with wraparound connections to achieve vertex and edge symmetry. Meshes and tori are among the most frequent multiprocessor networks available today on the market. It is well known that there are three possible tessellations

of a plane with regular polygons of the same kind: square (Fig. 1), triangular (Fig. 2), and hexagonal (Fig. 3), corresponding to dividing a plane into regular squares, triangles, and hexagons, respectively. The square tessellation is the basis for mesh-connected computers, which are widely studied in literature. The triangular tessellation is used to define hexagonal mesh (Fig. 2) multiprocessor, studied in [4], [5], [6], [7], [8], [9], [10]. Several sources [5], [6], [8] refer to the network as being honeycomb architecture. They begin with hexagonal tesselation but use cells (instead of vertices) as processors. Ben-Natan and Barak [11] mentioned the honeycomb array as a processor network but studied only the contractions of square, triangular, and hexagonal graphs.

Fig.1. Square mesh

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asymptotic performance.

2 TOPOLOGICAL PROPERTIES OF HONEYCOMB MESHES

Honeycomb meshes can be built from hexagons in various ways. The degree of any such network is three. The simplest way to define them is to consider the portion of the hexagonal tessellation which is inside a given convex polygon. We shall consider three types of meshes which differ by their boundary. Honeycomb hexagon mesh (HHM) is inside a regular hexagon (Fig. 3), honeycomb rhombic mesh (HRoM) is inside a rhombus (Fig.5), and honeycomb rectangular mesh (HReM) is inside a rectangle (Fig. 6).

Fig.2. Hexagonal mesh

Fig.3. Honeycomb mesh

Hexagonal tessellations were used in literature for various applications. Examples are cellular phone station placement, the representation of benzenoid hydrocarbons, computer graphics, and image processing. Here, we propose to study the honeycomb mesh interconnection network (Fig. 3), based on the hexagonal tessellation. By adding wraparound edges, we define the corresponding honeycomb torus network. We will study the basic topological properties and communication algorithms for honeycomb meshes and tori. A topology is evaluated in terms of a number of parameters. In this paper, we are interested in the symmetry, diameter, degree, bisection width, recursive decomposition, and routing, broadcasting, and semigroup computation algorithms. The remaining aspects of honeycomb meshes and tori are currently open research problems. Although all characteristics are important, we shall consider the network cost, defined as the product of the degree and diameter (measured with respect to the number of nodes) as the main parameter in our comparison. Honeycomb and hexagonal meshes and mesh-connected computers clearly belong to the same family of networks. Their comparison in all criteria should give the same

Fig.4. Honeycomb torus of size three

Fig.5. Honeycomb rhombic mesh

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agonal mesh, and normal to each of three edge orientations. Fig. 4 shows how to wrap around honeycomb mesh of size three (HM3) to obtain HT3, the honeycomb torus of dimension three. The three lines of mirror symmetry for wraparound edges are shown in dashed lines. The same edge is given the same number. Wraparound edges are actually drawn in Fig. 4; for clarity, they will not be drawn in subsequent figures. For example, edges 4ed5gf in Fig. 4 make a hexagon, and edges 7a1b6c also make a hexagon. Thus, by wrapping around as indicated, we receive new hexagons.

5 NOC- HONEYCOMB ARCHITECTURE

The NoC solution brings a networking method to on-chip communication and brings notable improvements over conventional bus systems.

Fig.6. Honeycomb rectangular mesh

5.1 Introduction to NOC- Honeycomb Today on-chip systems use shared buses as the most common communication infrastructure. But as semiconductor technology improves, more and more subsystems can be connected to each other on a single chip. Shared buses will then no longer be a good communication solution for large designs. 5.2 Reasons for using NoC There are both physical and logical issues that prevent shared buses from being the on chip interconnection solution of the future. Amongst the physical issues we find the increase of wire delay, the control of power distribution and cross- talk between wires. A logical issue is that if more subsystems use a shared bus the usage time of the bus for each subsystem will be less. That generates a low utilization level of IP cores that have to use the bus often. Therefore it has been proposed that NoCs should be used as on-chip communication solutions instead of shared buses[12,13].Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. A NoC is constructed from multiple point-to-point data links interconnected by switches (a.k.a. routers), such that messages can be relayed from any source module to any destination module over several links, by making routing decisions at the switches [14]. 5.3 Different NoC Topologies There are number of different NoC topologies that are used to connect resources to each other through networks and information is sent as packets over the networks.[14] In NOC-honeycomb topology, each computational, storage or I/O resources will have an address and will be interconnected by a network of switches. Addressed packets of data, routed to their destination by the network of switches are used among these resources to communicate with each other. In NOC-honeycomb topology, the overall organization is in the form of a honeycomb, as shown in Fig. 7.The re-

To maximize symmetry, honeycomb (hexagonal) meshes can be built as follows: One hexagon is a honeycomb mesh of size one, denoted HM1. The honeycomb mesh HM2 of size two is obtained by adding six hexagons to the boundary edges of HM1. Inductively, honeycomb mesh HMt of size t is obtained from HMt-1 by adding a layer of hexagons around the boundary of HMt-1. For instance, Fig. 2 is honeycomb mesh of size three, i.e., HM3. Alternatively, the size t of HMt is determined as the number of hexagons between the center and boundary of HMt (inclusive). In honeycomb topology, each computational, storage or I/O resources will have an address and will be interconnected by a network of switches. Addressed packets of data, routed to their destination by the network of switches are used among these resources to communicate with each other. In honeycomb topology, the overall organization is in the form of a honeycomb. The resources-computational, storage and I/O - are organized as nodes of the hexagon with a local switch at the centre that interconnects these resources. Hexagons at the periphery would be primarily for I/O, whereas the ones in the core would have storage and computational resource.

4 HONEYCOMB TORUS NETWORK

Honeycomb torus network can be obtained by joining pairs of nodes of degree two (i.e., their unused ports) of the honeycomb mesh. In order to achieve edge and vertex symmetry, the best choice for wrapping around seems to be the pairs of nodes that are mirror symmetric with respect to three lines, passing through the center of hex-

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REFERENCES
[1] International Technology Roadmap for Semiconductors, 2003. http://public.itrs.net. [2] S.G. Akl, Parallel Computation: Models and Methods. Prentice Hall, 1996. [3] I. Stojmenovic, Direct Interconnection Networks, Parallel and Distributed Computing Handbook, A.Y. Zomaya, ed., pp. 537-567. McGraw-Hill, 1996. [4] M.S. Chen, K.G. Shin, and D.D. Kandlur, Addressing, Routing, and Broadcasting in Hexagonal Mesh Multiprocessors, IEEE Trans. Computers, vol. 39, no. 1, pp. 10-18, Jan. 1990. [5] D. Milutinovic, V. Milutinovic, and B. Soucek, The Honeycomb Architecture, Computer, vol. 20, no. 4, pp. 81-83, Apr. 1987. [6] V. Milutinovic, Mapping of Neural Networks on the Honey- comb Architecture, Proc. IEEE, vol. 77, no. 12, pp. 1,875-1,878, 1989. [7] G. Rote, On the Connection Between Hexagonal and Unidirectional Rectangular Systolic Arrays, Lecture Notes in Computer Science, vol. 227, pp. 70-83. Springer-Verlag, 1986. [8] B. Robic and J. Silc, High-Performance Computing on a Honey-comb Architecture, Proc. Second Intl ACPC Parallel Computation Conf., pp. 22-28. Austria: Springer-Verlag, 1993. [9] K.G. Shin, HARTS: A Distributed Real-Time Architecture, Computer, vol. 24, no. 5, pp. 25-35, May 1991. [10] H.Y. Youn and J.Y. Lee, An Efficient Dictionary Machine Using Hexagonal Processor Arrays, IEEE Trans. Parallel and Distributed Systems, vol. 7, no. 3, pp. 266-273, Mar. 1996. [11] R. Ben-Natan and A. Barak, Parallel Contractions of Grids for Task Assignment to Processor Networks, Networks, vol. 22, pp. 539-562, 1992. [12] Kenneth W. Mai Ron Ho and Mark A. Horowitz. The future of wires. in Proceedings of the ieee. 89:490504, April 2001. [13] T.N. Theis. The future of interconnection technology. in ibm j. research and development. 44:379390, May 2000. [14] NoCSim, http://codesign.cs.tamu.edu/nocsim and Exhibition (DATE), Paris, 2000, pp. 250-256.

Fig.7. A NOC-HoneyComb (Honey Comb Structure for NOC)

sources - computational, storage and I/O - are organized as nodes of the hexagon with a local switch at the centre that interconnects these resources. Hexagons at the periphery would be primarily for I/O, whereas the ones in the core would have storage and computational resource. Each resource, located on a hexagonal node being connected to three switches, can reach 12 resources with a single hop. To further improve the connectivity, switches are directly connected to their next nearest neighbours, as shown in Fig. 7, allowing any resource to reach 27 additional resources with two hops.

6 CONCLUSION
major research challenges in the design of NoCs have been presented. Network on a chip can be viewed as processors with various instruction sets residing on a chip. This paper proposes a method to minimize the total execution time. Network-on-chip designs promise to offer considerable advantages over the traditional bus-based designs its a very flexible network design that is highly scalable, and can be easily changed to accomodate various needs This design is suitable for building networks with low latency and high throughput.

Reza Kourdy received his B.Sc. degree in Computer Engineering and his M.Sc. degree in Computer Architecture both from Azad University of Arak, Iran, in 2002 and 2007, respectively. His research interests include Network-On-Chip Architecture and Fault-tolerance.

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Mohammad Reza Nouri Rad received his B.Sc. Degree in Computer Engineering Software from Azad University of Najafabad, Iran, in 2001, and his M.Sc. Degree in Computer Software from Azad University of Arak, Iran, in 2010. His research interests include NetworkOn-Chip Architecture and Network Security. He is Program Committee of following conferences : WICT 2011 CSNT 2011 CICN 2011 SocProS 2011 CSNT 2012 CICN 2012 BIC-TA 2012