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Objectives:
To be familiar with the design procedure using Decoder and MUX. To implement functions using Decoder and MUX
Problem-1
Given problem is implement a function Y(A,B,C,D) = (0,1,4,6,7,13,15) using decoder. To solve this problem we use 4-to-16-line decoder with active LOW output.
Truth Table:
Input D C B A D15 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 D14 1 1 1 1 1 1 1 1 1 1 1 1 D13 1 1 1 1 1 1 1 1 1 1 1 1 D12 1 1 1 1 1 1 1 1 1 1 1 1 D11 1 1 1 1 1 1 1 1 1 1 1 0 Output D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
1 1 1 0
1 1 0 1
1 0 1 1
0 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
Problem: 2
In this problem a bank four officers namely Vice President, Manager, Principle Officer and Cashier are authorized to open the lock of the vault room under the following conditions: The lock may be opened when all authorized officer are present. The lock may be opened when vice president and cashier are present. The lock may be opened when manager principle officer and cashier are present. Under the following condition we get bellow truth table.
Truth table:
No Input A 0 1 2 3 4 5 6 7 8 0 0 0 0 0 0 0 0 1 Input B 0 0 0 0 1 1 1 1 0 Input C 0 0 1 1 0 0 1 1 0 Input D 0 1 0 1 0 1 0 1 0 Output Y 0 0 0 0 0 0 0 1 0
9 10 11 12 13 14 15
1 1 1 1 1 1 1
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
1 0 1 0 1 0 1
Discussion:
To solve those problem we use 4-to-16-bit decoder circuit. In problem one first we design the circuit and checked out according to the truth table. On the other hand in problem two, first we
develop the truth table according to the question then we got the implementation function. As a result we got the combinational logic circuit and verified it.