SEWP ZC413

Computer Organization & Architecture 8086/8088 - CPU Architecture

The 8086 architecture can be broadly divided into two groups: (i) Execution Unit (EU) (ii) Bus Interface Unit (BIU)
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A d d e r

E C S D I P

S S S S

u s U

I n t e r f a c e n it

In s t r u c t i o n q u e u e

A X B X C X D X S P B P D I S I

A H ( 8 ) A B H ( 8 ) B C H ( 8 ) C D H ( 8 ) D

L ( 8 ) L ( 8 ) L ( 8 ) L ( 8 )

C G R e n e r a l e g is t e r s U

o n t r o l n i t

o n t r o l l i n e s

E A L U

x e c u t io n U n it

F l a g s

The execution unit and the Bus Interface unit operate asynchronously. The EU waits for the instruction object code to be fetched from the memory by the BIU. The BIU fetches or pre-fetches the object code (16-bits at a time) and loads it into the six bytes queue. Whenever the EU is ready to execute a new instruction, it fetches the instruction object code from the front of the instruction queue and executes the instruction in specified number of clock periods. The BIU is independent of the EU and attempts to keep the six-byte queue filled with instruction object codes. Execution Unit (EU) The execution unit consists of General Registers Arithmetic Logic Unit Control unit Flag Registers

General Registers The CPU has eight 16-bit general registers. They are divided into two files of four registers each. They are: (a) The data register file and (b) The pointer and index register file
A B C D H H H H A B C D L L L L A B C D X X X X

Data Register File AX, BX, CX and DX registers are the data registers. Individually AX register can be addressed as AL and AH registers, BX register can be addressed as BL and BH register, CX register can be addressed as CL and CH register, DX register can be addressed as DL and DH.

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Computer Organization & Architecture

The data registers can be used in most arithmetic and logic operations. The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source Index (SI) and Destination Index (DI) registers all are of 16-bits. They can also be used in most arithmetic and logic operations. These registers are usually used to hold offset addresses for addressing within a segment. Offset addressing reduces program size by eliminating the need for each instruction to specify frequently used addresses. The implicit register usage is as follows: AX Register AL Register AH Register BX Register CX Register CL Register DX Register Word Multiplication, Word Division and Word I/O Operation. Byte Multiplication, Byte Division, Byte I/O Translate, and Decimal Arithmetic Byte Multiplication and Byte Division. Base Register and Translate String Operations Variable Shift and Rotate Word Multiplication, Word Division, Indirect I/O.

SI and DI are both 16-bits wide and are used by string manipulation instructions. Both the SI and the DI registers have auto incrementing and auto-decrementing capabilities. Arithmetic Logic Unit (ALU)

(i)

ALU is 16-bits wide. It can do the following 16-bits arithmetic operations Addition (ii) Subtraction (iii) Multiplication (iv) Division

The ALU can also perform logical operations such as (i) NOT Flag Register The Execution Unit has a 16-bit flag register which indicates some conditions affected by the execution of an instruction. Some bits of the flag register control certain operations of the EU. The flag register in the EU contains nine active flags shown in fig.2 O D I T S Z AF PF CF Fig, 2 Flag Register Six of the nine flags are used to indicate some condition produced by an instruction. These condition flags are also called status flags of 8086/8088 microprocessor. These are the Carry flag, Parity flag, Auxiliary carry flag, Zero flag, and Sign flag. The other three Control flags are Trap Flag, Direction Flag and Interrupt flag. Conditional Flags Carry Flag (CF) - This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of the most significant bit position or if there is a borrow to the MSB after subtraction. This flag is also affected when other arithmetic and logical instruction are executed. Parity Flag (PF) - This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the result). This flag can be used to check for data transmission error. Prof. Satish K Shet Prof. Purushotham BV Page 2 / 16 (ii) AND (iii) OR (iv) EXCLUSIVE OR (v) TEST

SEWP ZC413

Computer Organization & Architecture

Auxiliary Carry Flag (AF) - This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from the higher nibble to the lower. The auxiliary carry flag is used for decimal adjust operation. The AF flag is of significance only for byte operations during which the lower order byte of the 16-bit word is used. Zero Flag (Z) - This flag is set when the result of an operation is zero. The flag is reset when the result is not zero. Overflow Flag (O) - This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result exceeded the storage capacity of the destination, and a significant digit has been lost. Sign flag (S) - This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this flag is set the data in assumed to be negative and when this flag is zero it is assumed to be positive. Control Flags - Control flags are used to control certain operations of the processor. The application of these flags are different from that of six conditional flags. The conditional flags are set or reset by the EU on the basis of the result of some arithmetic or logic operations. The control flags are deliberately set or reset with specific instructions included in the program. Trap flag (T) - This is used for single stepping through a program. It is used for debugging the programs. (Discusses with interrupts). Interrupt Flag (I) - It is used to allow / prohibit the interruption of a program. When the flag set, it enables the interrupt from INTR. When the flag is reset (0), it disables the interrupt. Direction Flag (D) - It is used for string instructiion. If the direction flag is set, the pointers are decremented else the pointers are incremented. Bus Interface Unit (BIU) The BIU sends out addresses, fetches instructions from memory, reads data from memory and ports, and writes data to ports and memory. In other words the BIU handles all transfers of data and addresses on the buses for the execution unit. The BIU has 1. An instruction queue 2. An Instruction pointer 3. Segment registers Instruction Queue To speed up program execution, the BIU fetches as many as 6 insturction bytes ahead of time from memory. The prefetched instruction bytes are held for the EU in a first-in-firstout group of register called a queue. The EU decodes an instruction or executes an instruction which does not require the buses. When the EU is ready for its next instruction, it simply reads the instruction from the queue in the BIU. Fetching the next instruction while the current instruction executes, is called pipelining. Instruction Pointer (IP) The Instruction Pointer is a 16-bit register. This register is always used as the effective memory address, and is added to the Code segment with a displacement of four bits to obtain the physical address of the opcode. The code segment cannot be changed by the move instruction. The instruction pointer is incremented after each opcode fetch to point to the next instruction. Segment Registers

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Computer Organization & Architecture

The 8086 microprocessor has 20-bit address lines. All the registers in 8086 are 16-bits in length. Hence to obtain 20-bit addresses from the available 16-bit registers, all 8086 memory addresses are computed by summing the contents of a segment register and a effective memory address. The effective memory address is computed via a variety of addressing modes. The process of adding, to obtain 20-bit address is as follows: The selected segment register contents are shifted-left four bits (i.e., the contents are multiplied by 16 decimal), and then added to the effective memory address to generate the actual physical address output. The four segment registers are Code Segment register [points to the instruction opcode] Data Segment register [points to the data memory] Stack Segment register [points to the Stack memory] Extra Segment register [points to the data memory] For an instruction fetch, the code segment register is automatically added to the logical address (in this case, the contents of the instruction pointer) to compute the value of the instruction address. For stack referencing the stack segment register is automatically added to the logical address (the SP or BP register contents) to compute the value of the stack address. For data reference operations, where either the data or extra segment register is chosen as the base, the logical address can be made up of many different types of values: it can be simply the immediate data value contained in the instruction, or it can be the sum of an immediate data value and a base register, plus an index register selection. Thus any memory location may be addressed without changing the value of the segment base register. Segment registers are also very useful for large programming tasks, which require isolation of program code from the data area, or isolation of module data from the stack information etc. Solved Problems 1. If a physical branch address is 5A230 H when (CS) = 5200 H, what will it be if the (CS) are changed to 7800 H. CS: 52 0 0 Offset: XXXX Physical add. 5A2 3 0 H Hence Offset = Physical add - (Segment address displaced by 4-bits) Offset = 5A230 - 52000 = 8230 H If the CS is changed to 7800 H the Physical address will be 2. 78000 + 8230 = 80230 Given that the EA of a datum is 2359 H and the DS = 490B H, what is the physical address of the datum? DS: 490B0 H EA: 2359 H Physical add. 4B409 Addressing modes of 8086

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Computer Organization & Architecture

When 8086 executes an instruction, it performs the specified function on data. These data are called its operands and may be part of the instruction, reside in one of the internal registers of the microprocessor, stored at an address in memory or held at an I/O port, to access these different types of operands, the 8086 is provided with various addressing modes (Data Addressing Modes). Data Addressing Modes of 8086 The 8086 has 12 addressing modes. The various 8086 addressing modes can be classified into five groups. A. Addressing modes for accessing immediate and register data (register and immediate modes). B. Addressing modes for accessing data in memory (memory modes) C. Addressing modes for accessing I/O ports (I/O modes) D. Relative addressing mode E. Implied addressing mode A. Immediate addressing mode: In this mode, 8 or 16 bit data can be specified as part of the instruction. OP Code Immediate Operand Example 1 : MOV CL, 03 H Moves the 8 bit data 03 H into CL Example 2 MOV DX, 0525 H Moves the 16 bit data 0525 H into DX In the above two examples, the source operand is in immediate mode and the destination operand is in register mode. Register addressing mode: The operand to be accessed is specified as residing in an internal register of 8086. Fig. Below shows internal registers, any one can be used as a source or destination operand, however only the data registers can be accessed as either a byte or word. Register Accumulator Base Count Data Stack pointer Base pointer Source index Destination index Code Segment Data Segment Stack Segment Extra Segment Byte (Reg 8) AL, AH BL, BH CL, CH DL, DH Operand sizes Word (Reg 16) Ax Bx Cx Dx SP BP SI DI CS DS SS ES :

Example 1 : MOV DX (Destination Register) , CX (Source Register) Which moves 16 bit content of CS into DX. Example 2 : MOV CL, DL Page 5 / 16

Prof. Satish K Shet Prof. Purushotham BV

SEWP ZC413

Computer Organization & Architecture Moves 8 bit contents of DL into CL

B. Direct addressing mode: The instruction Opcode is followed by an effective address, this effective address is directly used as the 16 bit offset of the storage location of the operand from the location specified by the current value in the selected segment register. The default segment is always DS. The 20 bit physical address (PA) of the operand in memory is normally obtained as PA = DS: EA But by using a segment override prefix (SOP) in the instruction, any of the four segment registers can be referenced, PA = CS DS : Direct Address SS ES The Execution Unit (EU) has direct access to all registers and data for register and immediate operands. However the EU cannot directly access the memory operands. It must use the BIU, in order to access memory operands. In the direct addressing mode, the 16 bit effective address (EA) is taken directly from the displacement field of the instruction. Example 1: MOV CX, START If the 16 bit value assigned to the offset START by the programmer using an assembler pseudo instruction such as DW is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical address 30540 H. The content of 30540 is moved to CL The content of 30541 is moved to CH Register indirect addressing mode: The EA is specified in either pointer (BX) register or an index (SI or DI) register. The 20 bit physical address is computed using DS and EA. Example: MOV [DI], BX register indirect If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060. The content of BX(2456) is moved to memory locations 50060 H and 50061 H. CS PA = DS BX SS = SI ES DI Based addressing mode: PA = CS DS BX Page 6 / 16

Prof. Satish K Shet Prof. Purushotham BV

SEWP ZC413 SS ES

Computer Organization & Architecture : or BP + displacement

when memory is accessed PA is computed from BX and DS when the stack is accessed PA is computed from BP and SS. Example : MOV AL, START [BX] or MOV AL, [START + BX] based mode EA : [START] + [BX] PA : [DS] + [EA]

The 8 bit content of this memory location is moved to AL. Indexed addressing mode: CS PA = DS SS : ES Example :

SI or DI

+ 8 or 16bit displacement

MOV BH, START [SI] PA : [SART] + [SI] + [DS] The content of this memory is moved into BH. Based Indexed addressing mode: CS PA = DS BX SI SS : or + or + 8 or 16bit displacement ES BP DI Example : MOV ALPHA [SI] [BX], CL If [BX] = 0200, ALPHA 08, [SI] = 1000 H and [DS] = 3000 Physical address (PA) = 31208 8 bit content of CL is moved to 31208 memory address. C. Addressing modes for accessing I/O ports: A standard I/O device uses port addressing modes. For memory mapped I/O, memory addressing modes are used. There are 2 types of port addressing modes.1) Direct 2) Indirect. In direct port mode, the port number is an 8 bit immediate operand. Example OUT 05h, AL; sends the contents of AL to 8 bit port 05h. In indirect port mode, the port number is taken from DX . Ex: IN AL, DX; If [DX] =7890, then it copies 8 bit content of port 7890h in to AL. D. Relative addressing mode: Example: JNC START If CY=O, then PC is loaded with current PC contents plus 8 bit signed value of START, otherwise the next instruction is executed. E. Implied addressing mode: Prof. Satish K Shet Prof. Purushotham BV Page 7 / 16

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Computer Organization & Architecture

Instruction using this mode has no operands. Example: CLC which clears carry flag to zero. INSTRUCTION SET: 1. Data Transfer Instructions: The MOV instruction is used to transfer a byte or a word of data from a source operand to a destination operand. These operands can be internal registers of the 8086 and storage locations in memory. Mnemonic MOV Meaning Move Destination Memory Accumulator Register Register Memory Register Memory Seg. Register Seg. Register (Word Operation) Reg 16 (Word Operation) Memory 16 Format MOV D, S Source Accumulator Memory Register Memory Register Immediate Immediate Reg 16 Mem 16 Seg Reg Seg Reg Operation (S) (D) Flags affected None Example MOV TEMP, AL MOV AX, TEMP MOV AX, BX MOV BP, Stack top MOV COUNT [DI], CX MOV CL, 04 MOV MASK [BX] [SI], 2F MOV ES, CX MOV DS, Seg base MOV BP SS MOV [BX], CS

MOV instruction cannot transfer data directly between a source and a destination that both reside in external memory. INPUT/OUTPUT INSTRUCTIONS: IN acc, port: In transfers a byte or a word from input port to the AL register or the AX register respectively. The port number my be specified either with an immediate byte constant, allowing access to ports numbered 0 through 255 or with a number previously placed in the DX register allowing variable access (by changing the value in DX) to ports numbered from 0 through 65,535. In Operands ACC, imm 8 bit Example IN AL, 0E2H (OR) IN AX, PORT

acc, DX IN AX, DX (OR) IN AL, DX OUT port, acc : Out transfers a byte or a word from the AL register or the AX register respectively to an output port. The port numbers may be specified either with an immediate byte or with a number previously placed in the register DX allowing variable access.No flags are affected. In Operands Imm 8, acc Prof. Satish K Shet Prof. Purushotham BV Example OUT 32, AX (OR) OUT PORT, AL Page 8 / 16

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Computer Organization & Architecture

DX, acc XCHG D, S: Mnemonic XCHG Meaning Exchange Format XCHGD,S

OUT DX, AL (OR) OUT DX, AX

Operation (D) (S)

Flags affected None Example XCHG, AX, BX XCHG TEMP, AX XCHG AL, BL

Destination Accumulator Memory Register Reg 16 Register Register

Source

In the above table register cannot be a segment register Example: For the data given, what is the result of executing the instruction. XCHG [SUM], BX ((DS) + SUM) (BX) if (DS) = 0200, SUM = 1234 PA = 02000 + 1234 = 03234 ASSUME (03234) = FF [BX] = 11AA (03235) = 00 (03234) (BL) (03235) (BH) We get (BX) = 00FF (SUM) = 11AA XLAT (translate): This instruction is useful for translating characters from one code such as ASCII to another such as EBCDIC, this is no operand instruction and is called an instruction with implied addressing mode. The instruction loads AL with the contents of a 20 bit physical address computed from DS, BX and AL. This instruction can be used to read the elements in a table where BX can be loaded with a 16 bit value to point to the starting address (offset from DS) and AL can be loaded with the element number (0 being the first element number) no flags are affected. XLAT instruction is equivalent to MOV AL, [AL] [BX AL [(AL) + (BX) + (DS)] LDS Instruction: LDS register, memory (Loads register and DS with words from memory)

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Computer Organization & Architecture

This instruction copies a word from two memory locations into the register specified in the instruction. It then copies a word from the next two memory locations into the DS register. LDS is useful for pointing SI and DS at the start of the string before using one of the string instructions. LDS affects no flags. Example 1: LDS BX [1234] Copy contents of memory at displacement 1234 in DS to BL. Contents of 1235H to BH. Copy contents at displacement of 1236H and 1237H to DS register. LEA Instruction : Load Effective Address (LEA register, source) This instruction determines the offset of the variable or memory location named as the source and puts this offset in the indicated 16 bit register. LEA will not affect the flags. Examples: LEA BX, PRICES; Load BX with offset and PRICES in DS LEA BP, SS; STACK TOP Load BP with offset of stack-top in SS LEA CX, [BX] [DI]; Loads CX with EA : (BX) + (DI) LES instruction : LES register, memory Example 1: Example 2: LES BX, [789A H]; (BX) [789A] in DS (ES) [789C] in DS LES DI, [BX]; (DI) [BX] in DS (ES) [BX+2] in DS. 2. Flag Control Instructions: Mnemonic LAHF SAHF CLC STC CMC CLI STI Meaning Load AH from flags Store AH into flags Clear carry flag Set carry flag Complement carry flag Clear interrupt flag Set interrupt flag Operation (AH)Flags (flags) (AH) (CF) 0 (CF) 1 (CF) (CF) (IF) 0 (IF) 1 Flags affected None SF,ZF,AF,PF,CF CF CF CF IF IF

Fig. : Flag control Instructions The first two instructions LAHF and SAHF can be used either to read the flags or to change them respectively notice that the data transfer that takes place is always between the AH register and flag register. For instance, we may want to start an operation with certain flags set or reset. Assume that we want to preset all flags to logic 1. To do this we can first load AH with FF and then execute the SAHF instruction. 3. Arithmetic Instructions. Prof. Satish K Shet Prof. Purushotham BV Page 10 / 16

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Computer Organization & Architecture

Addition: It consists of following Instructions. ADD ADC INC

ADD/ADC : ADD destination,source/ADC destination,source: This instruction add a number form source to a number form destination and put the result in the destination.the ADC , instruction also adds the status of carry flag into the result. The source may be an immediate number , a register,or a memory location. The source and destination both cannot be a memory loaction. Example: ADD AL,0F0H; add an immediate number 0F0h to contents of AL. ADC DL,CL; add the contents of CL to the contents of Dlwith Carry. INC : Increment destination:this instructionadds 1 to the specified destination.the destination may be register or memory loaction. INC AL; INC BX. SUBTRACTION: this group of instructions consists of following group of instructions: SUB: subtarction SBB: Substraction with Borrow DEC: decrement NEG: 2s complement of a number. SUB/SBB: subtarction SUB destination,source/SBB destination,source This instruction substract number in source from number in destination and put the result in the destination.The SBB , instruction also subtract the status of carry flag from the result. The source may be an immediate number , a register,or a memory location. The source and destination both cannot be a memory loaction. Example: SUB AL,0F0H; subtract immediate number 0F0H from the contents of AL store the result in AL. SBB DL,CL;substrct contents of CL and status of carry flag from the contents of DL and store the result in DL. DEC Decrement destination: This instruction subtract 1 from the specified destination.the destination may be register or memory loaction. EXAMPLE: DEC AL;substrcat 1 form the content of AL DEC BX; substrcat 1 form the content of BX NEG : form 2s complement of the number EX: NEG AL; AL=0011 0101 Comparison instruction: Prof. Satish K Shet Prof. Purushotham BV Page 11 / 16 after execution Al=1100 1011.

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Computer Organization & Architecture

CMP: this instruction compares a byte /word from a specified source with a byte /word form the specified destination. The source and destination both must be byte or word. The source may be regitsre or immediate number or a memory location. The destination may be register or memory lactaion.The comparison is done by subtarctng source byte or word from the destination byte or word. But the result is not stored inthe destination.source and destination remian unchanged., only flags are updated. EXAMPLE: CMP BL,01h ;compare th emmediate number 01 with byte in BL. CMP CX,BX; compare word in BX with word in CX. Multiplication Instruction: MUL: unsigned multiplication: MUL source: this instruction multiplies the unsigned byte from source an dunsigned byte in AL register or unsigned word from sourceand unsigned word in Ax register. Source can be register or memory lacation. When the byte is multiplyed by Al, the result is stored in AX register.most significand byte is stored inAH, and least significand byte is stored in Al.when a word is multiplyedby the contents of AX , the most significand word of result is stored in DX and least siginficand word is stored in AX. Example: MUL BL: AL x BL , result is in AX MUL BX AX x BX; reult high word in DX and Low word in AX. IMUL : signed multiplication: This instruction multiplies the signed byte from source and signed byte in AL register or signed word from source and signed word in Ax register. Source can be register or memory lacation. When the byte is multiplyed by Al, the result is stored in AX register.most significand byte is stored inAH, and least significand byte is stored in Al.when a word is multiplyed by the contents of AX , the most significand word of result is stored in DX and least siginficand word is stored in AX. Example: IMUL BL IMUL CX. DIVISION INSTRUCTION: DIV source: This instruction is used to divide the unsigened word by a byte or to divide an dunsigned double word by a word.when dividing word by byte , the word must be in AX register. After division Al will conatin8 bit quiotent and AH will conatin 8 bit remainder.when a double word is divide by a word , the most significand word of the double word must be in DX and least significand word must be in AX, after the division AX will conatin a 16 bit quiotent and Dx will contain a 16 bit remainder. Example: DIV CL word in AX/byte in CL. DIV CX ;double word in DX and AX/word in CX Quiotent in AX and remainder in DX. IDIV source: this instruction is used to divide a signed word by signed byte or to divide signed double word by a signe word . rest all is similar to DIV instruction. 4. LOGICAL INSTRUCTIONS AND dst , src: this instruction logically ANDs each bit of the source byte or word with the corresponding bit in the destination an d result is stored in detsination. The source may be

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Computer Organization & Architecture

regitsre or immediate number or a memory location. The destination may be register or memory lactaion. EXAMPLE AND BL,AL ; Before Execution AL=1001 0011=93H After execution BL=0001 0001. OR dst ,src: this instruction logically ORs each bit of the source byte or word with the corresponding bit in the destination an d result is stored in detsination. The source may be regitsre or immediate number or a memory location. The destination may be register or memory lactaion. Example; OR BL,AL Before Execution AL=1001 0011=93h After execution BL=1111 0111=F7 h BL=0111 0101=75h BL=0111 0101=75H

XOR destination, source: this instruction logically XORs each bit of the source byte or word with the corresponding bit in the destination an d result is stored in detsination. The source may be regitsre or immediate number or a memory location. The destination may be register or memory lactaion. Example: XOR BL,AL ; Before Execution AL=1010 1111=AF h BL=1111 After execution BL=0101 1111=5Fh. NOT destination This instruction inverts each bit of byte or word . the destination may be a registre or memory laocation. Example NOT AL ; Before Execution AL=0110 1100 After execution AL =1001 0011. 5. Shift and rotate Instructions SAL/SHL dst , count SAL/SHL instruction: SAL and SHL are the two mnemonics for the same instruction. This instruction shifts each bit in the specified destination to the left and 0 is stored at LSB position. The MSB is shifted into the carry flag. Here the number of shifts are indicated by count SHR instruction:SHR destination,count:this instruction shifts each bit in the specified destinationto the right and 0 is shifted at MSB position.The LSB is shifted into carry flag.Here the number of shifts are indicated by count. SAR instruction: SAR destination,count.:This instruction shifts each bit in the specified destination some number of bit position to the right. As a bit is shifted out of the MSB possition,a copy of the old MSB is put in the MSB position.the The LSB will be shifted into CF. 0000=F0h

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Computer Organization & Architecture

Rotate Instruction: ROL destination,count: this instruction rotates all bits in a specified byte or word to the left some number of bit positions,MSB is placed as anew LSB and new Carry flag. ROR instruction: ROR destination,count: this instruction rotates all bits in a specified byte or word to the right some number of bit position.LSb is placed as anew MSB and new Carryflag. RCL instruction: RCL destination,count: this instruction roates all of the bits in a specified word or byte some number of bit position to the left along with the carry flag.MSB is placed as a new carry and previous carry is placed as a new LSB. RCR instruction: RCR destination,count: this instrcuiction roates all of the bits in a specified word or byte some number of bit position to the right along with the carry flag.LSB is placed as new carry and previous carry is placed as a new MSB. 6. The Jump instruction:this group of instruction will always cause the 8086 to fetch its next instruction form the location specifed or indicated by the instruction rather than from the next location after the JMP instruction.the JMP instructions are basically classified as unconditional jump and conditional jump instructions.A conditional jump instructionalows the programmer to make decision based upon numerical tests. The results of numerical tests are held in the flag bits,which are tested by conditional jump instructions. Example: JMP 8000; Unconditonal jump instruction. JNZ 9000; conditional jump instruction. Programs #1. Write an alp to move a block of data from source location x to destination location y without overlap DATA SEGMENT ORG 300H SRC DB 10H,20H,30H,40H,50H,60H,70H,80H,90H, A0H ORG 400H DST DB 10DUP(?) DATA ENDS CODE SEGMENT ASSUME CS: CODE, DS: DATA START: MOV AX, DATA ; INITILISE DS REGISTER MOV DS, AX LEA SI, SRC ; INITIALIZE SRC POINTER LEA DI, DST ; INITIALIZE DST POINTER MOV CX, 10 ; LOAD CX WITH NUMBER OF BYTES TO BE TRANSFERRED BACK: MOV AL, [SI] MOV [DI], AL ; TRANSFER DATA FROM SRC TO DST INC SI INC DI DEC CX ; REPEAT UNTIL ALL DATA IS TRANSFERRED JNZ BACK MOV AH, 4CH ; TERMINATE THE PROGRAM INT 21H CODE ENDS END START Prof. Satish K Shet Prof. Purushotham BV Page 14 / 16

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Computer Organization & Architecture

#2. Write a program to perform the multiplication of two 16 bit unsigned numbers stored in consecutive locations DATA SEGMENT MULTIPLICAND DW 0FFFFH ; FIRST NUMBER MULTIPLIER DW 00FFH ; SECOND NUMBER PRODUCT DW ?,? ; RESULT OF MULTIPLICATION DATA ENDS CODE SEGMENT ASSUME CS: CODE DS: DATA START:MOV AX, DATA MOV DS, AX MOV AX, MULTIPLICAND MUL MULTIPLIER MOV PRODUCT, AX MOV PRODUCT+2, DX MOV AH, 4CH INT 21H CODE ENDS END START. #3. Program to find the square of the given number DATA SEGMENT X DB 02H SQR DW? DATA ENDS CODE SEGMENT ASSUME DS: DATA CS: CODE START:MOV AX, DATA MOV DS, AX MOV AL, X MUL AL MOV SQR, AX MOV AH 4CH INT 21H CODE ENDS END START #4. Program to add an array of n numbers DATA SEGMENT COUNT DW 10 SRC DB 01 , 02 , 03, 04, 05 ,06, 07 ,08, 09 0A RES DW 0 DATA ENDS CODE SEGMENT ASSUME DS: DATA, CS: CODE ST ART: MOV AX, DATA MOV DS, AX LEA SI, SRC MOV AX , 00 MOV CX, COUNT BACK: ADD AL, [SI] Prof. Satish K Shet Prof. Purushotham BV

; INITIALIZE THE SEGMENT REGISTERS ; TO STORE CARRY ; INITIALIZE THE COUNTER

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JNC L1 INC AH L1: INC SI DEC CX JNZ BACK MOV RES , AX MOV AH, 4CH INT 21H CODE ENDS END START

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