Expt.

No: Date:

4-BIT RIPPLE CARRY ADDER USING VERILOG

AIM
To write a program for 4-bit ripple carry adder in verilog using modelsim5.7g.

SOFTWARE REQUIRED
Modelsim5.7g

PROCEDURE
1. Open Modelsim 5.7g software and work library is created in the directory by creating a project. 2. The VHDL source code is written and compiled if any errors are found they are rectified and recompiled to check for errors. 3. The error free code is simulated and waveforms are observed.

PROGRAM
module ripplecarry(s.c.a.b.cin); input [3:0]a,b; input cin; output c,[3:0]s; wire c1,c2,c3; fa fa0(s[0],c1,a[0],b[0],cin); fa fa1(s[1],c2,a[1],b[1],c1); fa fa2(s[2],c3,a[2],b[2],c2); fa fa3(s[3],c,a[3],b[3],c3); end module module fa(s,c,a,b,cin); input a,b,cin; output s,c; wire w1,w2,w3; xor(s,a,b,cin); and(w1,a,b); and(w2,b,cin); and(w3,cin,a); or(c,w1,w2,w3); end module

OUTPUT

RESULT
Thus a verilog program for 4-bit ripple carry adder is executed using modelsim5.7g.

Expt.No: Date:

4-BIT RIPPLE CARRY ADDER USING VHDL AIM

To write a program for 4-bit ripple carry adder in VHDL using modelsim5.7g.

SOFTWARE REQUIRED
Modelsim5.7g

PROCEDURE
1. Open Modelsim 5.7g software and work library is created in the directory by creating a project. 2. The VHDL source code is written and compiled if any errors are found they are rectified and recompiled to check for errors. 3. The error free code is simulated and waveforms are observed.

PROGRAM
Library ieee; Use ieee.std_logic_1164.all; Entity ripplecarry is port( a,b: in bit_vector(3 downto 0); ci: in bit; s: out bit_vector(3 downto 0); co: out bit); end ripplecarry; Architecture structure of ripplecarry is Component fulladder port (x,y.cin: in bit; cout,sum: out bit); end component; signal c: bit_vector(3 downto 1); begin fa0: fulladder portmap(a[0],b[0],ci,c[1],s[0]); fa1: fulladder portmap(a[1],b[1],c[1],c[2],s[1]); fa2: fulladder portmap(a[2],b[2],c[2],c[3],s[2]); fa3: fulladder portmap(a[3],b[3],c[3],co,s[3]); end structure;

OUTPUT

RESULT
Thus a VHDL program for 4-bit ripple carry adder is executed using modelsim5.7g.

Expt.No: Date:

ARITHMETIC LOGIC UNIT USING VHDL AIM

To write a program for arithmetic logic unit in VHDL using modelsim5.7g.

SOFTWARE REQUIRED
Modelsim5.7g

PROCEDURE
1. Open Modelsim 5.7g software and work library is created in the directory by creating a project. 2. The VHDL source code is written and compiled if any errors are found they are rectified and recompiled to check for errors. 3. The error free code is simulated and waveforms are observed.

PROGRAM
Library ieee; Use ieee.std_logic_1164.all; Entity alu is port( s: in std_logic_vector(2 downto 0); a,b: in std_logic_vector(3 downto 0); z: out std_logic_vector(3 downto 0)); end alu; Architecture behaviour of alu is begin process(s,a,b) begin case s is when 000 => z <= a or b; when 001 => z <= a and b; when 010 => z <= a nor b; when 011 => z <= a nand b; when 100 => z <= a xor b; when 101 => z <= not a or; when 110 => z <= not b; when 111 => z <= a; when others => z <= 0000; end case; end process; end behaviour;

OUTPUT

RESULT
Thus a VHDL program for arithmetic logic unit is executed using modelsim5.7g.

Expt.No: Date:

RIPPLE COUNTER USING VHDL AIM

To write a program for ripple counter in VHDL using modelsim5.7g.

SOFTWARE REQUIRED
Modelsim5.7g

PROCEDURE
1. Open Modelsim 5.7g software and work library is created in the directory by creating a project. 2. The VHDL source code is written and compiled if any errors are found they are rectified and recompiled to check for errors. 3. The error free code is simulated and waveforms are observed.

PROGRAM
library ieee; use ieee.std_logic_1164.all; entity counter is port ( clk : in std_logic; clear : in std_logic; count : out std_logic_vector(3 downto 0)); end counter; architecture structural of counter is component d_ff port ( clk : in std_logic; clear : in std_logic; d : in std_logic; q : out std_logic; nq : out std_logic); end component; signal ncount : std_logic_vector(3 downto 0); begin bit_0 : d_ff port map (clk => clk, clear => clear, d => ncount(0), q => count(0), nq => ncount(0)); bit_1 : d_ff port map (clk => ncount(0), clear => clear, d => ncount(1), q => count(1), nq => ncount(1)); bit_2 : d_ff port map (clk => ncount(1), clear => clear, d => ncount(2), q => count(2), nq => ncount(2)); bit_3 : d_ff port map (clk => ncount(2), clear => clear, d => ncount(3), q => count(3), nq => ncount(3)); end structural;

OUTPUT

RESULT
Thus a VHDL program for ripple counter is executed using modelsim5.7g.