Académique Documents
Professionnel Documents
Culture Documents
Features
Single 3.3 0.3V power supply Fast clock rate - PC133: 133 MHz (CL3) - PC100: 100 MHz (CL2) Fully synchronous operation referenced to clock rising edge 4-bank operation controlled by BA0, BA1 (Bank Address) Programmable Mode registers - /CAS Latency: 2 or 3 - Burst Length: 1, 2, 4, 8 or full page - Burst Type: interleaved or linear burst Byte Control DQML and DQMU Random column access Auto precharge / All banks precharge controlled by A10 Auto and self-refresh Self-refresh mode: standard and low power 4096 refresh cycles/64ms Interface: LVTTL 54-pin 400 mil plastic TSOP II package
EM639165
8Mega x 16bits SDRAM
Preliminary (Rev 1.0, 2/2001)
Ordering Information
Part Number Speed Grade PC133/CL3 PC133/CL3 PC100/CL2 PC100/CL2 Self refresh current (Max.) 2 mA 800 A 2 mA 800 A
Key Specifications
EM639165
- 75/8
10/10 ns 7.5/8 ns 6/6 ns 5.4/6 ns 45/48 ns 67.5/70 ns
Clock Cycle time (min., CL=2) Clock Cycle time (min., CL=3) Access time (max., CL=2) Access time (max., CL=3) Row Active time (max.) Row Cycle time(min.)
Overview
EM639165 is a high-speed Synchronous Dynamic Random Access Memory (SDRAM), organized as 4 banks x 2,097,152 words x 16 bits. All inputs and outputs are referenced to the rising edge of CLK. It achieves very high-speed data rates up to 133MHz, and is suitable for main memories or graphic memories in computer systems. For handheld device application, we also provide a low power option, with self-refresh current under 800 A.
EM639165
BLOCK DIAGRAM
DQ0-15
I/O Buffer
Memory Array
4096 x512x16 Cell Array
Memory Array
4096 x512x16 Cell Array
Memory Array
4096 x512x16 Cell Array
Memory Array
4096 x512x16 Cell Array
Bank #0
Bank #1
Bank #2
Bank #3
A0-11
BA0,1
CLK
CKE
/CS
/RAS
/CAS
/WE
DQM
Preliminary
Rev 1.0
Feb. 2001
EM639165
PIN FUNCTION
CLK
Input
Master Clock: All other inputs are referenced to the rising edge of CLK Clock Enable: CKE controls internal clock.When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self-refresh. After self-refresh mode is started, CKE becomes asynchronous input. Self-refresh is maintained as long as CKE is low. Chip Select: When /CS is high, any command means No Operation. Combination of /RAS, /CAS, /WE defines basic commands. A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified byA0-8. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE , READ , WRITE commands.
CKE
Input
Input Input
A0-11
Input
BA0,1
Input
DQ0-15
Input / Output Data In and Data out are referenced to the rising edge of CLK.
Din Mask / Output Disable: When DQM(U/L) is high in burst write, Din for the current cycle is masked. When DQM(U/L) is high in burst read, Dout is disabled at the next but one cycle. Power Supply for the memory array and peripheral circuitry.
DQMU/L
Input
VDD,VSS VDDQ,VSSQ
Power Supply
Power Supply VDDQ and VSSQ are supplied to the Output Buffers only.
Preliminary
Rev 1.0
Feb. 2001
EM639165
BASIC FUNCTIONS
The EM639165 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh opt ion, and precharge option, respectively . To know the detailed definition of commands, please see the command truth table.
Preliminary
Rev 1.0
Feb. 2001
EM639165
COMMAND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Active Single Bank Precharge Precharge All Banks Column Address Entry &Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry
MNEMONIC DESEL NOP ACT PRE PREA WRITE WRITE A READ READA REFA REFS CKE n-1 H H H H H H H H H H H L CKE n X X X X X X X X X H L H H X X /CS H L L L L L L L L L L H L L L /RAS /CAS X H L L L H H H H L L X H H L X H H H H L L L L L L X H H L /WE BA0,1 A1 1 X H H L L L L H H H H X H L L X X V V X V V V V X X X X X L X X V X X V V V V X X X X X L A1 0 X X V L H L H L H X X X X X L A0-9 X X V X X V V V V X X X X X V*1
Self-Refresh Exit
REFSX L
TBST MRS
H H
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address
Preliminary
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE
Current State /CS /RAS /CAS /WE Address IDLE
H L L L L L L L X H H H L L L L X H H H H L L L L X H H L H H L L X H H L L H H L L X H L X H L H L X H L H L H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
Command Action
DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS NOP NOP ILLEGAL*2 ILLEGAL*2 Bank Active, Latch RA NOP*4 Auto-Refresh*5 Mode Register Set*5 NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL*2 Precharge / Precharge All ILLEGAL ILLEGAL
ROW ACTIVE
H L L L L L L L L
Preliminary
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State READ /CS
H L L L L L L L L
Command Action
DESEL NOP TBST READ /READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TBST READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA,Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst, Latch CA,Begin Terminate Burst, Latch CA,Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst, Precharge ILLEGAL ILLEGAL
WRIT E
H L L L L L L L L
Preliminary
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State READ with AUTO PRECHARGE /CS H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L /RAS /CAS /WE X H H H H L L L L X H H H H L L L L X H H L L H H L L X H H L L H H L L X H L H L H L H L X H L H L H L H L Address X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / READA WRITE / WRITE A ACT PRE / PREA REFA MRS DESEL NOP TBST Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL
READ / ILLEGAL READA WRITE / ILLEGAL WRITEA ACT PRE / PREA REFA MRS Bank Active / ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
Preliminary
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /CS H L L L L L L L ROW ACTIVATING H L L L L L L L /RAS /CAS /WE X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 NOP*4 (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL
Preliminary
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State WRITE RECOVERING /CS H L L L L L L L REFRESHING H L L L L L L L /RAS /CAS /WE X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L Address X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP NOP ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL*2 ILLEGAL ILLEGAL NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Preliminary
10
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE (continued)
Current State MODE REGISTER SETTING /CS H L L L L L L L /RAS /CAS /WE Address X H H H L L L L X H H L H H L L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Command DESEL NOP TBST READ / WRITE ACT PRE / PREA REFA MRS Action NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL
Preliminary
11
Rev 1.0
Feb. 2001
EM639165
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH*1 CKE n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE*2 H H H H H H H L ANY STATE other than listed above H H L L CKE n X H H H H H L X H L H L L L L L L X H L H L /CS X H L L L L X X X X X L H L L L L X X X X X /RAS /CAS X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X /WE X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Power Down) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Susspend at Next Cycle*3 Exit CLK Susspend at Next Cycle*3 Maintain CLK Suspend
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command.
Preliminary
12
Rev 1.0
Feb. 2001
EM639165
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 200s. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation.
CLK /CS /RAS /CAS /WE BA0,1 A11-A0
V
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command.
BA0 BA1 A1 1 A1 0 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
LTMODE
BT
BL
BL 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
BT= 0 1 2 4 8 R R R FP
BT= 1 1 2 4 8 R R R R
BURST LENGTH
SEQUENTIAL INTERLEAVED
Preliminary
13
Rev 1.0
Feb. 2001
EM639165
/CAS Latency
Burst Length
Initial Address A2 0 0 0 0 1 1 1 1 A1 A0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1
BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4
0 1 0 1 0 1 0 1 0 1
Preliminary
14
Rev 1.0
Feb. 2001
EM639165
OPERATIONAL DESCRIPTION
BANK ACTIVATE
The SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row addresses A0-11. The minimum activation interval between one bank and the other bank is tRRD. Maximum 2 ACT commands are allowed within tRC , although the number of banks which are active concurrently is not limited.
READ
After tRCD from the bank activation, a READ command can be issued. 1st output data is available after the /CAS Latency from the READ, followed by (BL -1) consecutive data when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) , and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL after READA. (Need to keep tRAS min.) The next ACT command can be issued after (BL + tRP) from the previous READA.
PRECHARGE
The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA, PRE + A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued.
ACT tRRD Xa Xa Xa 00
PRE tRP
ACT Xb
Xb Xb 01
Qa1
Qa2
Qa3
Precharge all
Preliminary
15
Rev 1.0
Feb. 2001
EM639165
Multi Bank Interleaving READ (BL=4, CL=3)
CLK Command A0-9 A10 A11 BA0,1 DQ
/CAS latency Burst Length ACT tRCD Xa Xa Xa 00 00 Y 0 Xb Xb Xb 10 Qa0 10 Qa1 00 Qa2 Qa3 Qb0 Qb1 Qb2 Y 0 0 READ ACT READ PRE
ACT tRCD Xa Xa Xa 00
READ BL Y 1 tRP
ACT Xa Xa Xa
00
Qa1
Qa2
Qa3
Preliminary
16
Rev 1.0
Feb. 2001
EM639165
WRITE
After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set at the same cycle as the WRITE. Following (BL -1) data are written into the RAM, when the Burst Length is BL. The start address is specified by A0-A9,A11(x4), A0-9(X8), A0-8(X16) and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, the autoprecharge (WRITEA) is performed. Any command (READ, WRITE, PRE, TBST, ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge begins at tWR after the last input data cycle. (Need to keep tRAS min.) The next ACT command can be issued after tRP from the internal precharge timing.
Preliminary
17
Rev 1.0
Feb. 2001
EM639165
BURST INTERRUPTION [ Read Interrupted by Read ]
Burst read operation can be interrupted by new read of any bank. Random column access is allowed READ to READ interval is minimum 1 CLK..
Preliminary
18
Rev 1.0
Feb. 2001
EM639165
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=4.
Command DQ Command
READ
PRE Q0 Q1 Q2
READ
PRE Q0 Q1
CL=3
DQ Command DQ
READ PRE
Q0
Command DQ Command
READ Q0
PRE Q1 Q2
READ
PRE Q0 Q1
CL=2
DQ Command DQ
READ PRE
Q0
Preliminary
19
Rev 1.0
Feb. 2001
EM639165
[Read Interrupted by Burst Terminate]
rupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to
Similarly to the precharge, a burst terminate command can inter- output disable latency is equivalent to the /CAS Latency.
Command DQ Command
READ
TBST Q0 Q1 Q2
READ
TBST Q0 Q1
CL=3
DQ Command DQ
READ TBST
Q0
Command DQ Command
READ Q0
TBST Q1 Q2
READ
TBST Q0 Q1
CL=2
DQ Command DQ
READ TBST
Q0
Preliminary
20
Rev 1.0
Feb. 2001
EM639165
[ Write Interrupted by Write ]
Burst write operation can be interrupted by new write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK.
Preliminary
21
Rev 1.0
Feb. 2001
EM639165
[ Write Interrupted by Precharge ]
Burst write operation can be interrupted by precharge of the same bank.Write recovery time(tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM.
ACT
A0-9,11
Xa
Ya
Xa
A10
BA0-1 DQM
00
00
00
00
tWR
DQ
Da 0
Da 1
A0-9,11
Xa
Ya
Yb
A10
BA0-1
00
00
00
DQ
Da 0
Da 1
Db 0
Db 1
Db 2
Db 3
Preliminary
22
Rev 1.0
Feb. 2001
EM639165
[Write with Auto-Precharge Interrupted by Write or Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after tRP. Auto-precharge interruption by a command to the same bank is inhibited.
ACT
A0-9,11
Ya
Yb
tWR
Xa
A10
Xa
BA0-1
00
10
00
DQ
Da 0
Da 1
Db 0
Db 1
Db 2
Db 3 activate
auto-precharge
interrupted
ACT
A0-9,11
Ya
Yb
tWR
Xa
A10
Xa
BA0-1
00
10
00
DQ
Da 0
Da 1 interrupted
Qb0
Qb1
Qb2
Qb3 activate
auto-precharge
Preliminary
23
Rev 1.0
Feb. 2001
EM639165
[Read with Auto-Precharge Interrupted by Read to another Bank]
Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT command can be issued after tRP. Auto-precharge interruption by a command to the same bank is inhibited.
ACT
A0-9,11
Ya
Yb
Xa
A10
Xa
BA0-1
00
10
00
DQ
Qa0
Qa1
Qb0
Qb1
Qb2
Qb3
auto-precharge
interrupted
activate
[Single Write]
When single write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0).
Preliminary
24
Rev 1.0
Feb. 2001
EM639165
AUTO REFRESH
Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= / CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto-refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRC. Any command must not be supplied to the device before tRC from the REFA command.
Auto-Refresh
CLK /CS NOP or DESELECT /RAS /CAS /WE CKE A0-11 BA0,1 minimum tRFC
Preliminary
25
Rev 1.0
Feb. 2001
EM639165
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the selfrefresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input ,all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRC from the 1st CLK egde following CKE=H, all banks are in the idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then.
Self-Refresh
CLK
Stable CLK
NOP
new command
A0-11 BA0,1
X 00
Preliminary
26
Rev 1.0
Feb. 2001
EM639165
CLK SUSPEND
CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored.
int.CLK
CKE Command
ACT NOP NOP NOP
DQ
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Preliminary
27
Rev 1.0
Feb. 2001
EM639165
DQM CONTROL
DQM is a dual function signal defined as the data mask for writes and the output disable for reads. During writes, DQM(U,L) masks input data word by word. DQM(U,L) to write mask latency is 0. During reads, DQM(U,L) forces output to Hi-Z word by word. DQM(U,L) to output Hi-Z latency is 2.
DQM Function(CL=3)
DQ
D0
D2
D3
Q0
Q1
Q3
masked by DQM(U,L)=H
disabled by DQM(U,L)=H
Preliminary
28
Rev 1.0
Feb. 2001
EM639165
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD VDDQ VI VO IO Pd Topr Tstg
Parameter
Supply Voltage Supply Voltage for Output Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature
Condition
with respect to VSS with respect to VSSQ with respect to VSS with respect to VSSQ
Rating
-0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 -0.5 - 4.6 50
Unit
V V V V mA mW C C
Ta = 25C
Symbol
VDD VSS VDDQ VSSQ VIH*1 VIL*2
Parameter
Supply Voltage Supply Voltage Supply Voltage for output Supply Voltage for output High-Level Input Voltage all inputs Low-level Input Voltage all inputs
Min.
3.0 0 3.0 0 2.0 -0.3
Typ.
3.3 0 3.3 0
Max.
3.6
Unit
V V
V V V V
NOTES: 1. VIH(max)=5.5V for pulse width less than 10ns. 2. VIL(min)=-1.0V for pulse width less than 10ns.
CAPACITANCE
(Ta=0 -70C,VDD=VDDQ=3.3 0 . 3 V , V S S = V S S Q = 0 V , u n l e s s o t h e r w i s e n o t e d )
Symbol
CI(A) CI(C) CI(K) CI/O
Parameter
Input Capacitance, address pin Input Capacitance, contorl pin Input Capacitance, CLK pin Input Capacitance, I/O pin
Test Condition
Min.
2.5 2.5 2.5 4.0
Max.
5.0 5.0 4.0 6.5
Unit pF pF pF pF
Preliminary
29
Rev 1.0
Feb. 2001
EM639165
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 - 70C, VDD=VDDQ=3.30.3V,VSS=VSSQ=0V, unless otherwise noted)
Max.
Symbol
ITEM
Unit
mA mA mA mA mA mA mA
Operating current
Icc1
110 130
Precharge Standby current in Non-Power down mode Precharge Standby current in Power down mode Active Standby current
CKE=VILmax tCLK=15ns CKE=VIHmin CLK=VILmax(fixed) CKE=VIHmin tCLK=15ns(Note) CKE=VIHmin tCLK=VILmax(fixed) CKE=/CS=VIHmin tCLK=15ns(Note) CKE=VIHmin tCLK=VILmax(fixed)
All Bank Active tCLK = min BL=4, CL=3, IOL=0mA
20 15 2 1 30 20 160
mA 20 130 mA
Icc4
Icc5 Icc6
160
160
mA
2 800
2 800
mA A
NOTE: 1. Icc(max) is specified at the output open condition. 2. Input signals are changed one time during 30ns.
Parameter High-Level Output Voltage (DC) Low-level Output Voltage (DC) Off-state Output Current Input Current
Test Conditions
Min. 2.4
Max.
Unit V
V A A
Preliminary
30
Rev 1.0
Feb. 2001
EM639165
AC TIMING REQUIREMENTS
(Ta=0 - 70C, VDD=VDDQ=3.30.3V,VSS=VSSQ=0V, unless otherwise noted)
Input Pulse Levels:0.8V-2.0V Input Timing Measurement Level:1.4V
Symbol
tCLK
Parameter
Min. CLK cycle time
CL=2 CL=3 10 7.5 2.5 2.5 1 1.8 1 67.5 75 20 45 20 15 15 15
-8 Max.
Unit
ns ns ns ns 10 ns ns ns ns ns ns 100K ns ns ns ns ns 64 ms
tCH tCL tT tIS tIH tRC tRFC tRCD tRAS tRP tWR tRRD tRSC tREF
CLK High pulse width CLK Low pulse width Transition time of CLK Input Setup time Input Hold time Row Cycle time Refresh Cycle Time Row to Column Delay Row Active time Row Precharge time Write Recovery time Act to Act Delay time Mode Register Set Cycle time Refresh Interval time
(all inputs) (all inputs)
CLK
1.4V
DQ
1.4V
Any AC timing is referenced to the input signal passing through 1.4V.
Preliminary
31
Rev 1.0
Feb. 2001
EM639165
SWITCHING CHARACTERISTICS
(Ta=0 - 70C, VDD=VDDQ=3.30.3V,VSS=VSSQ=0V, unless otherwise noted)
-75 Symbol Parameter Min. CL=2 tAC Access time from CLK CL=3 tOH Output Hold time from CLK Delay time , output lowimpedance from CLK Delay time , output highimpedance from CLK CL=2 CL=3 3 3 0 3 5.4 5.4 3 3 0 3 6 6 ns ns ns ns ns *1 Max. 6 Min. Max. 6 ns -8 Unit Note
tOLZ tOHZ
NOTE: 1. If clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter.
VOUT 50pF
CLK
1.4V
DQ
1.4V
CLK tOLZ DQ
1.4V
1.4V
tAC
tOH
tOHZ
Preliminary
32
Rev 1.0
Feb. 2001
EM639165
Burst Write (single bank) @BL=4
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR tWR
D0
D0
D0
D0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
ACT # 0
WRITE#0
PRE#0
Preliminary
33
Rev 1.0
Feb. 2001
EM639165
Burst Write (multi bank) @BL=4
10
11
12
13
14
15
16
CLK
tRC tRC
/CS
tRAS tRRD tRP
/RAS
tRCD tRCD tRCD
/CAS
tWR tWR
D0
D0
D0
D0
D1
D1
D1
D1
D0
D0
D0
D0
PRE#0
ACT# 0
WRITE#0 ACT#1
PRE#0
WRITEA#1 (Auto-Precharge)
Preliminary
34
Rev 1.0
Feb. 2001
EM639165
Burst Read (single bank) @BL=4 CL=2
10
11
12
13
14
15
16
CLK
tRC
/CS
tRAS tRP tRAS
/RAS
tRCD tRCD
Q0
Q0
Q0
Q0
Q0
Q0
Q0
Q0
ACT#0
READ# 0
PRE#0
ACT# 0
READ# 0
PRE#0
Preliminary
35
Rev 1.0
Feb. 2001
EM639165
Burst Read (multiple bank) @BL=4 CL=2
10
11
12
13
14
15
16
CLK
tRC tRC
/CS
tRRD tRAS
/RAS
tRCD tRCD tRCD
Q0
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT# 0
READ# 0 ACT# 1
PRE#0
Preliminary
36
Rev 1.0
Feb. 2001
EM639165
Write Interrupted by Write @BL=4
10
11
12
13
14
15
16
CLK /CS
tRRD
/RAS
tRCD
/CAS
tWR
D0
D0
D0
D0
D0
D1
D1
D1
D0
D0
D0
D0
PRE#0 ACT# 1
Preliminary
37
Rev 1.0
Feb. 2001
EM639165
Read Interrupted by Read @BL=4,CL=2
10
11
12
13
14
15
16
CLK /CS
tRRD
/RAS
tRCD tRCD
Q0
Q0
Q0
Q1
Q1
Q1
Q1
Q1
Q0
Q0
Q0
Q0
ACT# 1
Preliminary
38
Rev 1.0
Feb. 2001
EM639165
Write Interrupted by Read, Read Interrupted by Write @BL=4,CL=2
10
11
12
13
14
15
16
CLK /CS
tRRD
/RAS
tRCD tRCD
/CAS
tWR
D0
D0
Q1
Q1
D1
D1
D1
D1
ACT#0
WRITE# 0 ACT#1
READ#1
WRITE# 1
PRE#1
Preliminary
39
Rev 1.0
Feb. 2001
EM639165
Write/Read Terminated by Precharge @BL=4,CL=2
10
11
12
13
14
15
16
CLK
tRC
/CS
tRP tRAS tRP
/RAS
tRCD tRCD
/CAS
tWR
D0
D0
Q0
Q0
ACT#0
WRITE# 0
READ# 0
Preliminary
40
Rev 1.0
Feb. 2001
EM639165
Write/Read Terminated by Burst Terminate @BL=4,CL=2
10
11
12
13
14
15
16
/CAS
tWR
D0
D0
Q0
Q0
D0
D0
D0
D0
ACT#0
WRITE#0
PRE#0
Preliminary
41
Rev 1.0
Feb. 2001
EM639165
Single Write Burst Read @BL=4,CL=2
10
11
12
13
14
15
16
D0
Q0
Q0
Q0
Q0
ACT#0 WRITE# 0
READ# 0
Preliminary
42
Rev 1.0
Feb. 2001
EM639165
Power-Up Sequesce and Intialize
CLK
200s
/CS
tRP tRFC tRFC tRSC
Preliminary
43
Rev 1.0
Feb. 2001
EM639165
Auto Refresh
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
/RAS
tRCD
D0
D0
D0
D0
PRE ALL
REFA
ACT#0
WRITE#0
Preliminary
44
Rev 1.0
Feb. 2001
EM639165
Self Refresh
10
11
12
13
14
15
16
CLK
tRFC
/CS
tRP
PRE ALL Self Refres h Entry All bank m ust be idle before REFS is issued. s
ACT#0
Preliminary
45
Rev 1.0
Feb. 2001
EM639165
CLK Suspension @BL=4,CL=2
10
11
12
13
14
15
16
D0
D0
D0
D0
Q0
Q0
Q0
Q0
READ# 0
Preliminary
46
Rev 1.0
Feb. 2001
EM639165
Power Down
10
11
12
13
14
15
16
PRE ALL
ACT# 0
Preliminary
47
Rev 1.0
Feb. 2001
EM639165
54 Pin TSOP II Package Outline Drawing Information
54 28
HE
0.254
L L1
1 D
27
A1 A2 A
L1
Symbol
A A1 A2 B c D E e HE L L1 S y q Notes: 1. Dimension D & E do not include interiead flash. 2. Dimension B does not include dambar protrusion/intrusion. 3. Dimension S includes end flash. 4. Controlling dimension: mm
Dimension in inch Min Normal Max 0.047 0.002 0.00395 0.0059 0.0411 0.012 0.015 0.016 0.0047 0.0065 0.0083 0.872 0.8755 0.879 0.3960 0.400 0.4040 0.0315 0.462 0.466 0.470 0.016 0.020 0.0235 0.033 0.035 0.004 0 5
Dimension in mm Min Normal Max 1.194 0.05 0.1 0.150 1.044 0.3 0.35 0.40 0.120 1.165 0.210 22.149 22.238 22.327 10.058 10.16 10.262 0.80 11.735 11.8365 11.938 0.406 0.50 0.597 0.84 0.88 0.10 0 5
Preliminary
48
Rev 1.0
Feb. 2001