UCF

Pin Details

Verilog code for all gates. module allgates(A, B, not1, or2, and3, nor4, nand5, xor6, xnor7); input A; input B; output not1; output or2; output and3; output nor4; output nand5; output xor6; output xnor7; reg not1; reg or2; reg and3; reg nor4; reg nand5; reg xor6; reg xnor7; always@(A or B) begin not1 = ~ (A); and3 = (A) & (B); or2 = A | B; nand5 = ~((A) & (B)); nor4 = ~((A) | (B)); xor6 = (A) ^ (B); xnor7 = ~((A) ^ (B)); end endmodule

UCF NET NET NET NET NET NET NET NET NET

file(User constraint file): "A" LOC = " " ; "and3" LOC = " " ; "B" LOC = " " ; "nand5" LOC = " " ; "nor4" LOC = " " ; "not1" LOC = " " ; "or2" LOC = " " ; "xnor7" LOC = " " ; "xor6" LOC = " " ;

PLACE & ROUTE SIMULATION:

POST PLACE & ROUTE SIMULATION:

Verilog code for 4-1 Multiplexer. module mux(en, a, y,sel); input en; input [3:0] a; input[1:0] sel; output y; reg y; always@(en or a) begin if(!en) y=1'b0; else case(sel) 2'b00 : y = a[3]; 2'b01 : y = a[2]; 2'b10 : y = a[1]; 2'b11 : y = a[0]; endcase end endmodule USER CONSTRAINTS: NET "a[0]" LOC = " NET "a[1]" LOC = " NET "a[2]" LOC = " NET "a[3]" LOC = " NET "en" LOC = " NET "sel[0]" LOC = NET "sel[1]" LOC = NET "y" LOC = "

" " " " " ;

; ; ; ;

" " ; " " ; " ;

Multiplexer:

Schematic diagram:

Truth table:

K-Map:

PLACE & ROUTE SIMULATION:

POST PLACE & ROUTE SIMULATION:

Verilog code for Decoder. module decoder(a, en, y); input[1:0] a; input en; output[3:0] y; reg[3:0] y; always@(en or a) begin if(!en) y= 4'b0000; else case(a) 2'b00 : y = 4'b0001; 2'b01 : y = 4'b0010; 2'b10 : y = 4'b0100; 2'b11 : y = 4'b1000; default :y = 4'b0000; endcase end endmodule USER CONSTRAINTS: NET "a[0]" LOC = " " ; NET "a[1]" LOC = " " ; NET "en" LOC = " " ; NET "y[0]" LOC = " " ; NET "y[1]" LOC = " " ; NET "y[2]" LOC = " " ; NET "y[3]" LOC = " " ;

PLACE & ROUTE SIMULATION:

POST PLACE & ROUTE SIMULATION:

Verilog code for 4-bit counter. module counter(clk, reset, count); input clk; input reset; output [3:0] count; reg[3:0] count; integer timer_count1 = 0; reg clk_msec; always@(posedge clk) begin if(timer_count1==4999999) begin timer_count1=0; clk_msec=1'b1; end else begin timer_count1=timer_count1+1; clk_msec=1'b0; end end always@(posedge clk_msec) begin if(~reset) count = 4'b0000; else count = count+1; end endmodule

USER CONSTRAINTS: NET NET NET NET NET "CLK" LOC = " "COUNT[0]" LOC "COUNT[1]" LOC "COUNT[2]" LOC "COUNT[3]" LOC = = = = " ; " " ; " " ; " " ; " " ;

NET "RESET" LOC = "

" ;

Verilog code for Accumulator ACCUMULATOR: module accum(clk,clr,q,d); input clk,clr; output [3:0]q; input [3:0]d; reg [3:0] tmp; always @(posedge clk or posedge clr) begin if(clr) tmp = 4'b0000; else tmp = tmp + d; end assign q = tmp; endmodule OUTPUT:

Verilog code for PRBS generator

PRBS GENRATOR: module input input input input input PRBS(CLK, RESET, DIN, LOAD, SHIFT, Q); CLK; RESET; DIN; LOAD; SHIFT;

output [4:0] Q; parameter N = 5; // Width of the shift register parameter tap0 = 0; // Tap designators. Specify which FF's parameter tap1 = 2; parameter tap2 = 3; parameter tap3 = 4; reg [N-1:0] Q; reg [N-1:0] Q_N; wire TAPS; always @ (posedge CLK or posedge RESET) begin if (RESET) Q <= 0-1; else Q <= Q_N; end assign TAPS = Q[tap0] ^ Q[tap1] ^ Q[tap2] ^ Q[tap3]; always @ (Q or SHIFT or LOAD or DIN or TAPS) begin Q_N = Q; if (LOAD) Q_N = {DIN, Q[N-1:1]}; else if (SHIFT) Q_N = {TAPS, Q[N-1:1]}; end endmodule

OUTPUT:

Verilog code for 4-bit multiplier 4-BIT MULTIPLIER: module multiplier(a, b, res); input a[3:0] ; input b[3:0] ; output res [7:0]; assign res = a * b; endmodule

OUTPUT: PLACE & ROUTE SIMULATION:

POST PLACE & ROUTE SIMULATION: